| blob | 00d30bd700682a6ace4052efb948b5aeece63b53 |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include "imx51-pinfunc.h"
14 #include <dt-bindings/clock/imx5-clock.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
19 / {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 /*
23 * The decompressor and also some bootloaders rely on a
24 * pre-existing /chosen node to be available to insert the
25 * command line and merge other ATAGS info.
26 * Also for U-Boot there must be a pre-existing /memory node.
27 */
28 chosen {};
29 memory { device_type = "memory"; reg = <0 0>; };
31 aliases {
32 ethernet0 = &fec;
33 gpio0 = &gpio1;
34 gpio1 = &gpio2;
35 gpio2 = &gpio3;
36 gpio3 = &gpio4;
37 i2c0 = &i2c1;
38 i2c1 = &i2c2;
39 mmc0 = &esdhc1;
40 mmc1 = &esdhc2;
41 mmc2 = &esdhc3;
42 mmc3 = &esdhc4;
43 serial0 = &uart1;
44 serial1 = &uart2;
45 serial2 = &uart3;
46 spi0 = &ecspi1;
47 spi1 = &ecspi2;
48 spi2 = &cspi;
49 };
51 tzic: tz-interrupt-controller@e0000000 {
52 compatible = "fsl,imx51-tzic", "fsl,tzic";
53 interrupt-controller;
54 #interrupt-cells = <1>;
55 reg = <0xe0000000 0x4000>;
56 };
58 clocks {
59 #address-cells = <1>;
60 #size-cells = <0>;
62 ckil {
63 compatible = "fsl,imx-ckil", "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <32768>;
66 };
68 ckih1 {
69 compatible = "fsl,imx-ckih1", "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 };
74 ckih2 {
75 compatible = "fsl,imx-ckih2", "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <0>;
78 };
80 osc {
81 compatible = "fsl,imx-osc", "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <24000000>;
84 };
85 };
87 cpus {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 cpu: cpu@0 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a8";
93 reg = <0>;
94 clock-latency = <62500>;
95 clocks = <&clks IMX5_CLK_CPU_PODF>;
96 clock-names = "cpu";
97 operating-points = <
98 166000 1000000
99 600000 1050000
100 800000 1100000
101 >;
102 voltage-tolerance = <5>;
103 };
104 };
106 usbphy {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 compatible = "simple-bus";
111 usbphy0: usbphy@0 {
112 compatible = "usb-nop-xceiv";
113 reg = <0>;
114 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
115 clock-names = "main_clk";
116 #phy-cells = <0>;
117 };
118 };
120 display-subsystem {
121 compatible = "fsl,imx-display-subsystem";
122 ports = <&ipu_di0>, <&ipu_di1>;
123 };
125 soc {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "simple-bus";
129 interrupt-parent = <&tzic>;
130 ranges;
132 iram: iram@1ffe0000 {
133 compatible = "mmio-sram";
134 reg = <0x1ffe0000 0x20000>;
135 };
137 ipu: ipu@40000000 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 compatible = "fsl,imx51-ipu";
141 reg = <0x40000000 0x20000000>;
142 interrupts = <11 10>;
143 clocks = <&clks IMX5_CLK_IPU_GATE>,
144 <&clks IMX5_CLK_IPU_DI0_GATE>,
145 <&clks IMX5_CLK_IPU_DI1_GATE>;
146 clock-names = "bus", "di0", "di1";
147 resets = <&src 2>;
149 ipu_di0: port@2 {
150 reg = <2>;
152 ipu_di0_disp1: endpoint {
153 };
154 };
156 ipu_di1: port@3 {
157 reg = <3>;
159 ipu_di1_disp2: endpoint {
160 };
161 };
162 };
164 aips@70000000 { /* AIPS1 */
165 compatible = "fsl,aips-bus", "simple-bus";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 reg = <0x70000000 0x10000000>;
169 ranges;
171 spba@70000000 {
172 compatible = "fsl,spba-bus", "simple-bus";
173 #address-cells = <1>;
174 #size-cells = <1>;
175 reg = <0x70000000 0x40000>;
176 ranges;
178 esdhc1: esdhc@70004000 {
179 compatible = "fsl,imx51-esdhc";
180 reg = <0x70004000 0x4000>;
181 interrupts = <1>;
182 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
183 <&clks IMX5_CLK_DUMMY>,
184 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
185 clock-names = "ipg", "ahb", "per";
186 status = "disabled";
187 };
189 esdhc2: esdhc@70008000 {
190 compatible = "fsl,imx51-esdhc";
191 reg = <0x70008000 0x4000>;
192 interrupts = <2>;
193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
196 clock-names = "ipg", "ahb", "per";
197 bus-width = <4>;
198 status = "disabled";
199 };
201 uart3: serial@7000c000 {
202 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
203 reg = <0x7000c000 0x4000>;
204 interrupts = <33>;
205 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 <&clks IMX5_CLK_UART3_PER_GATE>;
207 clock-names = "ipg", "per";
208 status = "disabled";
209 };
211 ecspi1: ecspi@70010000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx51-ecspi";
215 reg = <0x70010000 0x4000>;
216 interrupts = <36>;
217 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
218 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
219 clock-names = "ipg", "per";
220 status = "disabled";
221 };
223 ssi2: ssi@70014000 {
224 #sound-dai-cells = <0>;
225 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
226 reg = <0x70014000 0x4000>;
227 interrupts = <30>;
228 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
229 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
230 clock-names = "ipg", "baud";
231 dmas = <&sdma 24 1 0>,
232 <&sdma 25 1 0>;
233 dma-names = "rx", "tx";
234 fsl,fifo-depth = <15>;
235 status = "disabled";
236 };
238 esdhc3: esdhc@70020000 {
239 compatible = "fsl,imx51-esdhc";
240 reg = <0x70020000 0x4000>;
241 interrupts = <3>;
242 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
243 <&clks IMX5_CLK_DUMMY>,
244 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
245 clock-names = "ipg", "ahb", "per";
246 bus-width = <4>;
247 status = "disabled";
248 };
250 esdhc4: esdhc@70024000 {
251 compatible = "fsl,imx51-esdhc";
252 reg = <0x70024000 0x4000>;
253 interrupts = <4>;
254 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
255 <&clks IMX5_CLK_DUMMY>,
256 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
257 clock-names = "ipg", "ahb", "per";
258 bus-width = <4>;
259 status = "disabled";
260 };
261 };
263 usbotg: usb@73f80000 {
264 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
265 reg = <0x73f80000 0x0200>;
266 interrupts = <18>;
267 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
268 fsl,usbmisc = <&usbmisc 0>;
269 fsl,usbphy = <&usbphy0>;
270 status = "disabled";
271 };
273 usbh1: usb@73f80200 {
274 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
275 reg = <0x73f80200 0x0200>;
276 interrupts = <14>;
277 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
278 fsl,usbmisc = <&usbmisc 1>;
279 dr_mode = "host";
280 status = "disabled";
281 };
283 usbh2: usb@73f80400 {
284 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
285 reg = <0x73f80400 0x0200>;
286 interrupts = <16>;
287 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
288 fsl,usbmisc = <&usbmisc 2>;
289 dr_mode = "host";
290 status = "disabled";
291 };
293 usbh3: usb@73f80600 {
294 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
295 reg = <0x73f80600 0x0200>;
296 interrupts = <17>;
297 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
298 fsl,usbmisc = <&usbmisc 3>;
299 dr_mode = "host";
300 status = "disabled";
301 };
303 usbmisc: usbmisc@73f80800 {
304 #index-cells = <1>;
305 compatible = "fsl,imx51-usbmisc";
306 reg = <0x73f80800 0x200>;
307 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
308 };
310 gpio1: gpio@73f84000 {
311 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
312 reg = <0x73f84000 0x4000>;
313 interrupts = <50 51>;
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
318 };
320 gpio2: gpio@73f88000 {
321 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
322 reg = <0x73f88000 0x4000>;
323 interrupts = <52 53>;
324 gpio-controller;
325 #gpio-cells = <2>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
328 };
330 gpio3: gpio@73f8c000 {
331 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
332 reg = <0x73f8c000 0x4000>;
333 interrupts = <54 55>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 };
340 gpio4: gpio@73f90000 {
341 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
342 reg = <0x73f90000 0x4000>;
343 interrupts = <56 57>;
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 };
350 kpp: kpp@73f94000 {
351 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
352 reg = <0x73f94000 0x4000>;
353 interrupts = <60>;
354 clocks = <&clks IMX5_CLK_DUMMY>;
355 status = "disabled";
356 };
358 wdog1: wdog@73f98000 {
359 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
360 reg = <0x73f98000 0x4000>;
361 interrupts = <58>;
362 clocks = <&clks IMX5_CLK_DUMMY>;
363 };
365 wdog2: wdog@73f9c000 {
366 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
367 reg = <0x73f9c000 0x4000>;
368 interrupts = <59>;
369 clocks = <&clks IMX5_CLK_DUMMY>;
370 status = "disabled";
371 };
373 gpt: timer@73fa0000 {
374 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
375 reg = <0x73fa0000 0x4000>;
376 interrupts = <39>;
377 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
378 <&clks IMX5_CLK_GPT_HF_GATE>;
379 clock-names = "ipg", "per";
380 };
382 iomuxc: iomuxc@73fa8000 {
383 compatible = "fsl,imx51-iomuxc";
384 reg = <0x73fa8000 0x4000>;
385 };
387 pwm1: pwm@73fb4000 {
388 #pwm-cells = <2>;
389 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
390 reg = <0x73fb4000 0x4000>;
391 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
392 <&clks IMX5_CLK_PWM1_HF_GATE>;
393 clock-names = "ipg", "per";
394 interrupts = <61>;
395 };
397 pwm2: pwm@73fb8000 {
398 #pwm-cells = <2>;
399 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
400 reg = <0x73fb8000 0x4000>;
401 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
402 <&clks IMX5_CLK_PWM2_HF_GATE>;
403 clock-names = "ipg", "per";
404 interrupts = <94>;
405 };
407 uart1: serial@73fbc000 {
408 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
409 reg = <0x73fbc000 0x4000>;
410 interrupts = <31>;
411 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
412 <&clks IMX5_CLK_UART1_PER_GATE>;
413 clock-names = "ipg", "per";
414 status = "disabled";
415 };
417 uart2: serial@73fc0000 {
418 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
419 reg = <0x73fc0000 0x4000>;
420 interrupts = <32>;
421 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
422 <&clks IMX5_CLK_UART2_PER_GATE>;
423 clock-names = "ipg", "per";
424 status = "disabled";
425 };
427 src: src@73fd0000 {
428 compatible = "fsl,imx51-src";
429 reg = <0x73fd0000 0x4000>;
430 #reset-cells = <1>;
431 };
433 clks: ccm@73fd4000{
434 compatible = "fsl,imx51-ccm";
435 reg = <0x73fd4000 0x4000>;
436 interrupts = <0 71 0x04 0 72 0x04>;
437 #clock-cells = <1>;
438 };
439 };
441 aips@80000000 { /* AIPS2 */
442 compatible = "fsl,aips-bus", "simple-bus";
443 #address-cells = <1>;
444 #size-cells = <1>;
445 reg = <0x80000000 0x10000000>;
446 ranges;
448 iim: iim@83f98000 {
449 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
450 reg = <0x83f98000 0x4000>;
451 interrupts = <69>;
452 clocks = <&clks IMX5_CLK_IIM_GATE>;
453 };
455 owire: owire@83fa4000 {
456 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
457 reg = <0x83fa4000 0x4000>;
458 interrupts = <88>;
459 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
460 status = "disabled";
461 };
463 ecspi2: ecspi@83fac000 {
464 #address-cells = <1>;
465 #size-cells = <0>;
466 compatible = "fsl,imx51-ecspi";
467 reg = <0x83fac000 0x4000>;
468 interrupts = <37>;
469 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
470 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
471 clock-names = "ipg", "per";
472 status = "disabled";
473 };
475 sdma: sdma@83fb0000 {
476 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
477 reg = <0x83fb0000 0x4000>;
478 interrupts = <6>;
479 clocks = <&clks IMX5_CLK_SDMA_GATE>,
480 <&clks IMX5_CLK_SDMA_GATE>;
481 clock-names = "ipg", "ahb";
482 #dma-cells = <3>;
483 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
484 };
486 cspi: cspi@83fc0000 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
490 reg = <0x83fc0000 0x4000>;
491 interrupts = <38>;
492 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
493 <&clks IMX5_CLK_CSPI_IPG_GATE>;
494 clock-names = "ipg", "per";
495 status = "disabled";
496 };
498 i2c2: i2c@83fc4000 {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
502 reg = <0x83fc4000 0x4000>;
503 interrupts = <63>;
504 clocks = <&clks IMX5_CLK_I2C2_GATE>;
505 status = "disabled";
506 };
508 i2c1: i2c@83fc8000 {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
512 reg = <0x83fc8000 0x4000>;
513 interrupts = <62>;
514 clocks = <&clks IMX5_CLK_I2C1_GATE>;
515 status = "disabled";
516 };
518 ssi1: ssi@83fcc000 {
519 #sound-dai-cells = <0>;
520 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
521 reg = <0x83fcc000 0x4000>;
522 interrupts = <29>;
523 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
524 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
525 clock-names = "ipg", "baud";
526 dmas = <&sdma 28 0 0>,
527 <&sdma 29 0 0>;
528 dma-names = "rx", "tx";
529 fsl,fifo-depth = <15>;
530 status = "disabled";
531 };
533 audmux: audmux@83fd0000 {
534 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
535 reg = <0x83fd0000 0x4000>;
536 clocks = <&clks IMX5_CLK_DUMMY>;
537 clock-names = "audmux";
538 status = "disabled";
539 };
541 weim: weim@83fda000 {
542 #address-cells = <2>;
543 #size-cells = <1>;
544 compatible = "fsl,imx51-weim";
545 reg = <0x83fda000 0x1000>;
546 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
547 ranges = <
548 0 0 0xb0000000 0x08000000
549 1 0 0xb8000000 0x08000000
550 2 0 0xc0000000 0x08000000
551 3 0 0xc8000000 0x04000000
552 4 0 0xcc000000 0x02000000
553 5 0 0xce000000 0x02000000
554 >;
555 status = "disabled";
556 };
558 nfc: nand@83fdb000 {
559 #address-cells = <1>;
560 #size-cells = <1>;
561 compatible = "fsl,imx51-nand";
562 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
563 interrupts = <8>;
564 clocks = <&clks IMX5_CLK_NFC_GATE>;
565 status = "disabled";
566 };
568 pata: pata@83fe0000 {
569 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
570 reg = <0x83fe0000 0x4000>;
571 interrupts = <70>;
572 clocks = <&clks IMX5_CLK_PATA_GATE>;
573 status = "disabled";
574 };
576 ssi3: ssi@83fe8000 {
577 #sound-dai-cells = <0>;
578 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
579 reg = <0x83fe8000 0x4000>;
580 interrupts = <96>;
581 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
582 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
583 clock-names = "ipg", "baud";
584 dmas = <&sdma 46 0 0>,
585 <&sdma 47 0 0>;
586 dma-names = "rx", "tx";
587 fsl,fifo-depth = <15>;
588 status = "disabled";
589 };
591 fec: ethernet@83fec000 {
592 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
593 reg = <0x83fec000 0x4000>;
594 interrupts = <87>;
595 clocks = <&clks IMX5_CLK_FEC_GATE>,
596 <&clks IMX5_CLK_FEC_GATE>,
597 <&clks IMX5_CLK_FEC_GATE>;
598 clock-names = "ipg", "ahb", "ptp";
599 status = "disabled";
600 };
601 };
602 };
603 };