| blob | 4e776e036cbcf4026a4fc9f0a93550a33dc8454e |
1 /*
2 * Copyright 2014-2017 Toradex AG
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
44 #include <dt-bindings/gpio/gpio.h>
46 / {
47 model = "Toradex Apalis iMX6Q/D Module";
48 compatible = "toradex,apalis_imx6q", "fsl,imx6q";
50 backlight: backlight {
51 compatible = "pwm-backlight";
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_gpio_bl_on>;
54 pwms = <&pwm4 0 5000000>;
55 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
56 status = "disabled";
57 };
59 reg_1p8v: regulator-1p8v {
60 compatible = "regulator-fixed";
61 regulator-name = "1P8V";
62 regulator-min-microvolt = <1800000>;
63 regulator-max-microvolt = <1800000>;
64 regulator-always-on;
65 };
67 reg_2p5v: regulator-2p5v {
68 compatible = "regulator-fixed";
69 regulator-name = "2P5V";
70 regulator-min-microvolt = <2500000>;
71 regulator-max-microvolt = <2500000>;
72 regulator-always-on;
73 };
75 reg_3p3v: regulator-3p3v {
76 compatible = "regulator-fixed";
77 regulator-name = "3P3V";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 regulator-always-on;
81 };
83 reg_usb_otg_vbus: regulator-usb-otg-vbus {
84 compatible = "regulator-fixed";
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
87 regulator-name = "usb_otg_vbus";
88 regulator-min-microvolt = <5000000>;
89 regulator-max-microvolt = <5000000>;
90 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
91 enable-active-high;
92 status = "disabled";
93 };
95 /* on module USB hub */
96 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
97 compatible = "regulator-fixed";
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
100 regulator-name = "usb_host_vbus_hub";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
104 startup-delay-us = <2000>;
105 enable-active-high;
106 status = "okay";
107 };
109 reg_usb_host_vbus: regulator-usb-host-vbus {
110 compatible = "regulator-fixed";
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
113 regulator-name = "usb_host_vbus";
114 regulator-min-microvolt = <5000000>;
115 regulator-max-microvolt = <5000000>;
116 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
117 enable-active-high;
118 vin-supply = <®_usb_host_vbus_hub>;
119 status = "disabled";
120 };
122 sound {
123 compatible = "fsl,imx-audio-sgtl5000";
124 model = "imx6q-apalis-sgtl5000";
125 ssi-controller = <&ssi1>;
126 audio-codec = <&codec>;
127 audio-routing =
128 "LINE_IN", "Line In Jack",
129 "MIC_IN", "Mic Jack",
130 "Mic Jack", "Mic Bias",
131 "Headphone Jack", "HP_OUT";
132 mux-int-port = <1>;
133 mux-ext-port = <4>;
134 };
136 sound_spdif: sound-spdif {
137 compatible = "fsl,imx-audio-spdif";
138 model = "imx-spdif";
139 spdif-controller = <&spdif>;
140 spdif-in;
141 spdif-out;
142 status = "disabled";
143 };
144 };
146 &audmux {
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_audmux>;
149 status = "okay";
150 };
152 &can1 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_flexcan1>;
155 status = "disabled";
156 };
158 &can2 {
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_flexcan2>;
161 status = "disabled";
162 };
164 /* Apalis SPI1 */
165 &ecspi1 {
166 cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_ecspi1>;
169 status = "disabled";
170 };
172 /* Apalis SPI2 */
173 &ecspi2 {
174 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_ecspi2>;
177 status = "disabled";
178 };
180 &fec {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_enet>;
183 phy-mode = "rgmii";
184 phy-handle = <ðphy>;
185 phy-reset-duration = <10>;
186 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
187 status = "okay";
189 mdio {
190 #address-cells = <1>;
191 #size-cells = <0>;
193 ethphy: ethernet-phy@7 {
194 interrupt-parent = <&gpio1>;
195 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
196 reg = <7>;
197 };
198 };
199 };
201 &hdmi {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_hdmi_ddc>;
204 status = "disabled";
205 };
207 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
208 &i2c1 {
209 clock-frequency = <100000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c1>;
212 status = "disabled";
213 };
215 /*
216 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
217 * touch screen controller
218 */
219 &i2c2 {
220 clock-frequency = <100000>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_i2c2>;
223 status = "okay";
225 pmic: pfuze100@8 {
226 compatible = "fsl,pfuze100";
227 reg = <0x08>;
229 regulators {
230 sw1a_reg: sw1ab {
231 regulator-min-microvolt = <300000>;
232 regulator-max-microvolt = <1875000>;
233 regulator-boot-on;
234 regulator-always-on;
235 regulator-ramp-delay = <6250>;
236 };
238 sw1c_reg: sw1c {
239 regulator-min-microvolt = <300000>;
240 regulator-max-microvolt = <1875000>;
241 regulator-boot-on;
242 regulator-always-on;
243 regulator-ramp-delay = <6250>;
244 };
246 sw3a_reg: sw3a {
247 regulator-min-microvolt = <400000>;
248 regulator-max-microvolt = <1975000>;
249 regulator-boot-on;
250 regulator-always-on;
251 };
253 swbst_reg: swbst {
254 regulator-min-microvolt = <5000000>;
255 regulator-max-microvolt = <5150000>;
256 regulator-boot-on;
257 regulator-always-on;
258 };
260 snvs_reg: vsnvs {
261 regulator-min-microvolt = <1000000>;
262 regulator-max-microvolt = <3000000>;
263 regulator-boot-on;
264 regulator-always-on;
265 };
267 vref_reg: vrefddr {
268 regulator-boot-on;
269 regulator-always-on;
270 };
272 vgen1_reg: vgen1 {
273 regulator-min-microvolt = <800000>;
274 regulator-max-microvolt = <1550000>;
275 regulator-boot-on;
276 regulator-always-on;
277 };
279 vgen2_reg: vgen2 {
280 regulator-min-microvolt = <800000>;
281 regulator-max-microvolt = <1550000>;
282 regulator-boot-on;
283 regulator-always-on;
284 };
286 vgen3_reg: vgen3 {
287 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <3300000>;
289 regulator-boot-on;
290 regulator-always-on;
291 };
293 vgen4_reg: vgen4 {
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <3300000>;
296 regulator-boot-on;
297 regulator-always-on;
298 };
300 vgen5_reg: vgen5 {
301 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <3300000>;
303 regulator-boot-on;
304 regulator-always-on;
305 };
307 vgen6_reg: vgen6 {
308 regulator-min-microvolt = <1800000>;
309 regulator-max-microvolt = <3300000>;
310 regulator-boot-on;
311 regulator-always-on;
312 };
313 };
314 };
316 codec: sgtl5000@a {
317 compatible = "fsl,sgtl5000";
318 reg = <0x0a>;
319 clocks = <&clks IMX6QDL_CLK_CKO>;
320 VDDA-supply = <®_2p5v>;
321 VDDIO-supply = <®_3p3v>;
322 };
324 /* STMPE811 touch screen controller */
325 stmpe811@41 {
326 compatible = "st,stmpe811";
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_touch_int>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 reg = <0x41>;
332 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
333 interrupt-parent = <&gpio4>;
334 interrupt-controller;
335 id = <0>;
336 blocks = <0x5>;
337 irq-trigger = <0x1>;
339 stmpe_touchscreen {
340 compatible = "st,stmpe-ts";
341 /* 3.25 MHz ADC clock speed */
342 st,adc-freq = <1>;
343 /* 8 sample average control */
344 st,ave-ctrl = <3>;
345 /* 7 length fractional part in z */
346 st,fraction-z = <7>;
347 /*
348 * 50 mA typical 80 mA max touchscreen drivers
349 * current limit value
350 */
351 st,i-drive = <1>;
352 /* 12-bit ADC */
353 st,mod-12b = <1>;
354 /* internal ADC reference */
355 st,ref-sel = <0>;
356 /* ADC converstion time: 80 clocks */
357 st,sample-time = <4>;
358 /* 1 ms panel driver settling time */
359 st,settling = <3>;
360 /* 5 ms touch detect interrupt delay */
361 st,touch-det-delay = <5>;
362 };
363 };
364 };
366 /*
367 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
368 * board)
369 */
370 &i2c3 {
371 clock-frequency = <100000>;
372 pinctrl-names = "default", "recovery";
373 pinctrl-0 = <&pinctrl_i2c3>;
374 pinctrl-1 = <&pinctrl_i2c3_recovery>;
375 scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
376 sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
377 status = "disabled";
378 };
380 &pwm1 {
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_pwm1>;
383 status = "disabled";
384 };
386 &pwm2 {
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_pwm2>;
389 status = "disabled";
390 };
392 &pwm3 {
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_pwm3>;
395 status = "disabled";
396 };
398 &pwm4 {
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_pwm4>;
401 status = "disabled";
402 };
404 &spdif {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_spdif>;
407 status = "disabled";
408 };
410 &ssi1 {
411 status = "okay";
412 };
414 &uart1 {
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
417 fsl,dte-mode;
418 uart-has-rtscts;
419 status = "disabled";
420 };
422 &uart2 {
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_uart2_dte>;
425 fsl,dte-mode;
426 uart-has-rtscts;
427 status = "disabled";
428 };
430 &uart4 {
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_uart4_dte>;
433 fsl,dte-mode;
434 status = "disabled";
435 };
437 &uart5 {
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_uart5_dte>;
440 fsl,dte-mode;
441 status = "disabled";
442 };
444 &usbotg {
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_usbotg>;
447 disable-over-current;
448 status = "disabled";
449 };
451 /* MMC1 */
452 &usdhc1 {
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
455 vqmmc-supply = <®_3p3v>;
456 bus-width = <8>;
457 voltage-ranges = <3300 3300>;
458 status = "disabled";
459 };
461 /* SD1 */
462 &usdhc2 {
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_usdhc2>;
465 vqmmc-supply = <®_3p3v>;
466 bus-width = <4>;
467 voltage-ranges = <3300 3300>;
468 status = "disabled";
469 };
471 /* eMMC */
472 &usdhc3 {
473 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_usdhc3>;
475 vqmmc-supply = <®_3p3v>;
476 bus-width = <8>;
477 voltage-ranges = <3300 3300>;
478 non-removable;
479 status = "okay";
480 };
482 &weim {
483 status = "disabled";
484 };
486 &iomuxc {
487 /* pins used on module */
488 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_reset_moci>;
491 pinctrl_apalis_gpio1: gpio2io04grp {
492 fsl,pins = <
493 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
494 >;
495 };
497 pinctrl_apalis_gpio2: gpio2io05grp {
498 fsl,pins = <
499 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
500 >;
501 };
503 pinctrl_apalis_gpio3: gpio2io06grp {
504 fsl,pins = <
505 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
506 >;
507 };
509 pinctrl_apalis_gpio4: gpio2io07grp {
510 fsl,pins = <
511 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
512 >;
513 };
515 pinctrl_apalis_gpio5: gpio6io10grp {
516 fsl,pins = <
517 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
518 >;
519 };
521 pinctrl_apalis_gpio6: gpio6io09grp {
522 fsl,pins = <
523 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
524 >;
525 };
527 pinctrl_apalis_gpio7: gpio1io02grp {
528 fsl,pins = <
529 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
530 >;
531 };
533 pinctrl_apalis_gpio8: gpio1io06grp {
534 fsl,pins = <
535 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
536 >;
537 };
539 pinctrl_audmux: audmuxgrp {
540 fsl,pins = <
541 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
542 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
543 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
544 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
545 /* SGTL5000 sys_mclk */
546 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
547 >;
548 };
550 pinctrl_cam_mclk: cammclkgrp {
551 fsl,pins = <
552 /* CAM sys_mclk */
553 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
554 >;
555 };
557 pinctrl_ecspi1: ecspi1grp {
558 fsl,pins = <
559 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
560 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
561 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
562 /* SPI1 cs */
563 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
564 >;
565 };
567 pinctrl_ecspi2: ecspi2grp {
568 fsl,pins = <
569 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
570 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
571 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
572 /* SPI2 cs */
573 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
574 >;
575 };
577 pinctrl_enet: enetgrp {
578 fsl,pins = <
579 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
580 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
581 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
582 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
583 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
584 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
585 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
586 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
587 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
588 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
589 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
590 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
591 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
592 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
593 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
594 /* Ethernet PHY reset */
595 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
596 /* Ethernet PHY interrupt */
597 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1
598 >;
599 };
601 pinctrl_flexcan1: flexcan1grp {
602 fsl,pins = <
603 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
604 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
605 >;
606 };
608 pinctrl_flexcan2: flexcan2grp {
609 fsl,pins = <
610 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
611 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
612 >;
613 };
615 pinctrl_gpio_bl_on: gpioblon {
616 fsl,pins = <
617 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
618 >;
619 };
621 pinctrl_gpio_keys: gpio1io04grp {
622 fsl,pins = <
623 /* Power button */
624 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
625 >;
626 };
628 pinctrl_hdmi_cec: hdmicecgrp {
629 fsl,pins = <
630 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
631 >;
632 };
634 pinctrl_hdmi_ddc: hdmiddcgrp {
635 fsl,pins = <
636 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
637 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
638 >;
639 };
641 pinctrl_i2c1: i2c1grp {
642 fsl,pins = <
643 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
644 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
645 >;
646 };
648 pinctrl_i2c2: i2c2grp {
649 fsl,pins = <
650 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
651 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
652 >;
653 };
655 pinctrl_i2c3: i2c3grp {
656 fsl,pins = <
657 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
658 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
659 >;
660 };
662 pinctrl_i2c3_recovery: i2c3recoverygrp {
663 fsl,pins = <
664 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
665 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
666 >;
667 };
669 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
670 fsl,pins = <
671 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1
672 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1
673 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1
674 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1
675 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1
676 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1
677 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1
678 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1
679 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
680 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1
681 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1
682 >;
683 };
685 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
686 fsl,pins = <
687 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61
688 /* DE */
689 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61
690 /* HSync */
691 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61
692 /* VSync */
693 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61
694 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61
695 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61
696 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61
697 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61
698 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61
699 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61
700 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61
701 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61
702 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61
703 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61
704 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61
705 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61
706 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61
707 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61
708 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61
709 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61
710 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61
711 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61
712 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61
713 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61
714 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61
715 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61
716 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61
717 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61
718 >;
719 };
721 pinctrl_ipu2_vdac: ipu2vdacgrp {
722 fsl,pins = <
723 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
724 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1
725 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1
726 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1
727 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9
728 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9
729 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9
730 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9
731 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9
732 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9
733 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9
734 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9
735 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9
736 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9
737 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9
738 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9
739 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9
740 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9
741 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9
742 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9
743 >;
744 };
746 pinctrl_mmc_cd: gpiommccdgrp {
747 fsl,pins = <
748 /* MMC1 CD */
749 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
750 >;
751 };
753 pinctrl_pwm1: pwm1grp {
754 fsl,pins = <
755 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
756 >;
757 };
759 pinctrl_pwm2: pwm2grp {
760 fsl,pins = <
761 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
762 >;
763 };
765 pinctrl_pwm3: pwm3grp {
766 fsl,pins = <
767 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
768 >;
769 };
771 pinctrl_pwm4: pwm4grp {
772 fsl,pins = <
773 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
774 >;
775 };
777 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
778 fsl,pins = <
779 /* USBH_EN */
780 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
781 >;
782 };
784 pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
785 fsl,pins = <
786 /* USBH_HUB_EN */
787 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
788 >;
789 };
791 pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
792 fsl,pins = <
793 /* USBO1 power en */
794 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
795 >;
796 };
798 pinctrl_reset_moci: gpioresetmocigrp {
799 fsl,pins = <
800 /* RESET_MOCI control */
801 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
802 >;
803 };
805 pinctrl_sd_cd: gpiosdcdgrp {
806 fsl,pins = <
807 /* SD1 CD */
808 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
809 >;
810 };
812 pinctrl_spdif: spdifgrp {
813 fsl,pins = <
814 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
815 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
816 >;
817 };
819 pinctrl_touch_int: gpiotouchintgrp {
820 fsl,pins = <
821 /* STMPE811 interrupt */
822 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
823 >;
824 };
826 pinctrl_uart1_dce: uart1dcegrp {
827 fsl,pins = <
828 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
829 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
830 >;
831 };
833 /* DTE mode */
834 pinctrl_uart1_dte: uart1dtegrp {
835 fsl,pins = <
836 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
837 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
838 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
839 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
840 >;
841 };
843 /* Additional DTR, DSR, DCD */
844 pinctrl_uart1_ctrl: uart1ctrlgrp {
845 fsl,pins = <
846 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
847 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
848 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
849 >;
850 };
852 pinctrl_uart2_dce: uart2dcegrp {
853 fsl,pins = <
854 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
855 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
856 >;
857 };
859 /* DTE mode */
860 pinctrl_uart2_dte: uart2dtegrp {
861 fsl,pins = <
862 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
863 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
864 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
865 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
866 >;
867 };
869 pinctrl_uart4_dce: uart4dcegrp {
870 fsl,pins = <
871 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
872 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
873 >;
874 };
876 /* DTE mode */
877 pinctrl_uart4_dte: uart4dtegrp {
878 fsl,pins = <
879 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
880 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
881 >;
882 };
884 pinctrl_uart5_dce: uart5dcegrp {
885 fsl,pins = <
886 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
887 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
888 >;
889 };
891 /* DTE mode */
892 pinctrl_uart5_dte: uart5dtegrp {
893 fsl,pins = <
894 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
895 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
896 >;
897 };
899 pinctrl_usbotg: usbotggrp {
900 fsl,pins = <
901 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
902 >;
903 };
905 pinctrl_usdhc1_4bit: usdhc1grp_4bit {
906 fsl,pins = <
907 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
908 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
909 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
910 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
911 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
912 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
913 >;
914 };
916 pinctrl_usdhc1_8bit: usdhc1grp_8bit {
917 fsl,pins = <
918 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
919 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
920 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
921 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
922 >;
923 };
925 pinctrl_usdhc2: usdhc2grp {
926 fsl,pins = <
927 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
928 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
929 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
930 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
931 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
932 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
933 >;
934 };
936 pinctrl_usdhc3: usdhc3grp {
937 fsl,pins = <
938 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
939 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
940 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
941 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
942 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
943 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
944 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
945 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
946 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
947 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
948 /* eMMC reset */
949 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
950 >;
951 };
953 pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
954 fsl,pins = <
955 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
956 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
957 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
958 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
959 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
960 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
961 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
962 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
963 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
964 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
965 /* eMMC reset */
966 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
967 >;
968 };
970 pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
971 fsl,pins = <
972 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
973 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
974 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
975 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
976 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
977 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
978 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
979 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
980 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
981 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
982 /* eMMC reset */
983 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
984 >;
985 };
986 };