arch/arm/boot/dts/imx6sx-softing-vining-2000.dts

   1 /*
   2  * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/input/input.h>
  13 #include "imx6sx.dtsi"
  14
  15 / {
  16         model = "Softing VIN|ING 2000";
  17         compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";
  18
  19         chosen {
  20                 stdout-path = &uart1;
  21         };
  22
  23         memory {
  24                 reg = <0x80000000 0x40000000>;
  25         };
  26
  27         reg_usb_otg1_vbus: regulator-usb_otg1_vbus {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "usb_otg1_vbus";
  30                 pinctrl-names = "default";
  31                 pinctrl-0 = <&pinctrl_usb_otg1>;
  32                 regulator-min-microvolt = <5000000>;
  33                 regulator-max-microvolt = <5000000>;
  34                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  35                 enable-active-high;
  36         };
  37
  38         reg_peri_3v3: regulator-peri_3v3 {
  39                 compatible = "regulator-fixed";
  40                 regulator-name = "peri_3v3";
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-max-microvolt = <3300000>;
  43         };
  44
  45         pwmleds {
  46                 compatible = "pwm-leds";
  47
  48                 red {
  49                         label = "red";
  50                         max-brightness = <255>;
  51                         pwms = <&pwm6 0 50000>;
  52                 };
  53
  54                 green {
  55                         label = "green";
  56                         max-brightness = <255>;
  57                         pwms = <&pwm2 0 50000>;
  58                 };
  59
  60                 blue {
  61                         label = "blue";
  62                         max-brightness = <255>;
  63                         pwms = <&pwm1 0 50000>;
  64                 };
  65         };
  66 };
  67
  68 &adc1 {
  69         vref-supply = <&reg_peri_3v3>;
  70         status = "okay";
  71 };
  72
  73 &cpu0 {
  74         /*
  75          * This board has a shared rail of reg_arm and reg_soc (supplied by
  76          * sw1a_reg) which is modeled below, but still this module behaves
  77          * unstable without higher voltages. Hence, set higher voltages here.
  78          */
  79         operating-points = <
  80                 /* kHz    uV */
  81                 996000  1250000
  82                 792000  1175000
  83                 396000  1175000
  84                 198000  1175000
  85                 >;
  86         fsl,soc-operating-points = <
  87                 /* ARM kHz  SOC uV */
  88                 996000  1250000
  89                 792000  1175000
  90                 396000  1175000
  91                 198000  1175000
  92         >;
  93 };
  94
  95 &ecspi4 {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_ecspi4>;
  98         cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
  99         status = "okay";
 100 };
 101
 102 &fec1 {
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_enet1>;
 105         phy-supply = <&reg_peri_3v3>;
 106         phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 107         phy-reset-duration = <5>;
 108         phy-mode = "rmii";
 109         phy-handle = <&ethphy0>;
 110         status = "okay";
 111
 112         mdio {
 113                 #address-cells = <1>;
 114                 #size-cells = <0>;
 115
 116                 ethphy0: ethernet0-phy@0 {
 117                         reg = <0>;
 118                         max-speed = <100>;
 119                         interrupt-parent = <&gpio2>;
 120                         interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
 121                 };
 122         };
 123 };
 124
 125 &fec2 {
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&pinctrl_enet2>;
 128         phy-supply = <&reg_peri_3v3>;
 129         phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
 130         phy-reset-duration = <5>;
 131         phy-mode = "rmii";
 132         phy-handle = <&ethphy1>;
 133         status = "okay";
 134
 135         mdio {
 136                 #address-cells = <1>;
 137                 #size-cells = <0>;
 138
 139                 ethphy1: ethernet1-phy@0 {
 140                         reg = <0>;
 141                         max-speed = <100>;
 142                         interrupt-parent = <&gpio2>;
 143                         interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
 144                 };
 145         };
 146 };
 147
 148 &flexcan1 {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_flexcan1>;
 151         status = "okay";
 152 };
 153
 154 &flexcan2 {
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_flexcan2>;
 157         status = "okay";
 158 };
 159
 160 &i2c1 {
 161         clock-frequency = <100000>;
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&pinctrl_i2c1>;
 164         status = "okay";
 165
 166         proximity: sx9500@28 {
 167                 compatible = "semtech,sx9500";
 168                 reg = <0x28>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&pinctrl_sx9500>;
 171                 interrupt-parent = <&gpio2>;
 172                 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
 173                 reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
 174         };
 175
 176         pmic: pfuze100@8 {
 177                 compatible = "fsl,pfuze200";
 178                 reg = <0x08>;
 179
 180                 regulators {
 181                         sw1a_reg: sw1ab {
 182                                 regulator-min-microvolt = <300000>;
 183                                 regulator-max-microvolt = <1875000>;
 184                                 regulator-boot-on;
 185                                 regulator-always-on;
 186                                 regulator-ramp-delay = <6250>;
 187                         };
 188
 189                         sw2_reg: sw2 {
 190                                 regulator-min-microvolt = <800000>;
 191                                 regulator-max-microvolt = <3300000>;
 192                                 regulator-boot-on;
 193                                 regulator-always-on;
 194                         };
 195
 196                         sw3a_reg: sw3a {
 197                                 regulator-min-microvolt = <400000>;
 198                                 regulator-max-microvolt = <1975000>;
 199                                 regulator-boot-on;
 200                                 regulator-always-on;
 201                         };
 202
 203                         sw3b_reg: sw3b {
 204                                 regulator-min-microvolt = <400000>;
 205                                 regulator-max-microvolt = <1975000>;
 206                                 regulator-boot-on;
 207                                 regulator-always-on;
 208                         };
 209
 210                         snvs_reg: vsnvs {
 211                                 regulator-min-microvolt = <1000000>;
 212                                 regulator-max-microvolt = <3000000>;
 213                                 regulator-boot-on;
 214                                 regulator-always-on;
 215                         };
 216
 217                         vref_reg: vrefddr {
 218                                 regulator-boot-on;
 219                                 regulator-always-on;
 220                         };
 221
 222                         vgen1_reg: vgen1 {
 223                                 regulator-min-microvolt = <800000>;
 224                                 regulator-max-microvolt = <1550000>;
 225                                 regulator-always-on;
 226                         };
 227
 228                         vgen2_reg: vgen2 {
 229                                 regulator-min-microvolt = <800000>;
 230                                 regulator-max-microvolt = <1550000>;
 231                         };
 232
 233                         vgen3_reg: vgen3 {
 234                                 regulator-min-microvolt = <1800000>;
 235                                 regulator-max-microvolt = <3300000>;
 236                                 regulator-always-on;
 237                         };
 238
 239                         vgen4_reg: vgen4 {
 240                                 regulator-min-microvolt = <1800000>;
 241                                 regulator-max-microvolt = <3300000>;
 242                                 regulator-always-on;
 243                         };
 244
 245                         vgen5_reg: vgen5 {
 246                                 regulator-min-microvolt = <1800000>;
 247                                 regulator-max-microvolt = <3300000>;
 248                                 regulator-always-on;
 249                         };
 250
 251                         vgen6_reg: vgen6 {
 252                                 regulator-min-microvolt = <1800000>;
 253                                 regulator-max-microvolt = <3300000>;
 254                                 regulator-always-on;
 255                         };
 256                 };
 257         };
 258 };
 259
 260 &i2c3 {
 261         clock-frequency = <100000>;
 262         pinctrl-names = "default";
 263         pinctrl-0 = <&pinctrl_i2c3>;
 264         status = "okay";
 265 };
 266
 267 &iomuxc {
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&pinctrl_gpios>;
 270
 271         pinctrl_ecspi4: ecspi4grp {
 272                 fsl,pins = <
 273                         MX6SX_PAD_SD3_CLK__ECSPI4_SCLK          0x130b1
 274                         MX6SX_PAD_SD3_DATA3__ECSPI4_MISO        0x130b1
 275                         MX6SX_PAD_SD3_CMD__ECSPI4_MOSI          0x130b1
 276                         MX6SX_PAD_SD3_DATA2__GPIO7_IO_4         0x30b0
 277                 >;
 278         };
 279
 280         pinctrl_enet1: enet1grp {
 281                 fsl,pins = <
 282                         MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x30c1
 283                         MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x30c1
 284                         MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0f9
 285                         MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0f9
 286                         MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x30c1
 287                         MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0f9
 288                         MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4000a038
 289                         /* LAN8720 PHY Reset */
 290                         MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9        0x10b0
 291                         /* MDIO */
 292                         MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0f9
 293                         MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0f9
 294                         /* IRQ from PHY */
 295                         MX6SX_PAD_KEY_ROW2__GPIO2_IO_17         0x10b0
 296                 >;
 297         };
 298
 299         pinctrl_enet2: enet2grp {
 300                 fsl,pins = <
 301                         MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0x1b0b0
 302                         MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0x1b0b0
 303                         MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x1b0b0
 304                         MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x1b0b0
 305                         MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x1b0b0
 306                         MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0x1b0b0
 307                         MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4000a038
 308                         /* LAN8720 PHY Reset */
 309                         MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21       0x10b0
 310                         /* MDIO */
 311                         MX6SX_PAD_ENET1_COL__ENET2_MDC          0xa0f9
 312                         MX6SX_PAD_ENET1_CRS__ENET2_MDIO         0xa0f9
 313                         /* IRQ from PHY */
 314                         MX6SX_PAD_KEY_ROW4__GPIO2_IO_19         0x10b0
 315                 >;
 316         };
 317
 318         pinctrl_flexcan1: flexcan1grp {
 319                 fsl,pins = <
 320                         MX6SX_PAD_QSPI1B_DQS__CAN1_TX           0x1b0b0
 321                         MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX         0x1b0b0
 322                 >;
 323         };
 324
 325         pinctrl_flexcan2: flexcan2grp {
 326                 fsl,pins = <
 327                         MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX         0x1b0b0
 328                         MX6SX_PAD_QSPI1A_DQS__CAN2_TX           0x1b0b0
 329                 >;
 330         };
 331
 332         pinctrl_gpios: gpiosgrp {
 333                 fsl,pins = <
 334                         /* reset external uC */
 335                         MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19     0x10b0
 336                         /* IRQ from external uC */
 337                         MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x10b0
 338                         /* overcurrent detection */
 339                         MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8        0x10b0
 340                 >;
 341         };
 342
 343         pinctrl_i2c1: i2c1grp {
 344                 fsl,pins = <
 345                         MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
 346                         MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
 347                 >;
 348         };
 349
 350         pinctrl_i2c3: i2c3grp {
 351                 fsl,pins = <
 352                         MX6SX_PAD_NAND_ALE__I2C3_SDA            0x4001b8b1
 353                         MX6SX_PAD_NAND_CLE__I2C3_SCL            0x4001b8b1
 354                 >;
 355         };
 356
 357         pinctrl_pwm1: pwm1grp-1 {
 358                 fsl,pins = <
 359                         /* blue LED */
 360                         MX6SX_PAD_RGMII2_RD3__PWM1_OUT          0x1b0b1
 361                 >;
 362         };
 363
 364         pinctrl_pwm2: pwm2grp-1 {
 365                 fsl,pins = <
 366                         /* green LED */
 367                         MX6SX_PAD_RGMII2_RD2__PWM2_OUT          0x1b0b1
 368                 >;
 369         };
 370
 371         pinctrl_pwm6: pwm6grp-1 {
 372                 fsl,pins = <
 373                         /* red LED */
 374                         MX6SX_PAD_RGMII2_TD2__PWM6_OUT          0x1b0b1
 375                 >;
 376         };
 377
 378         pinctrl_sx9500: sx9500grp {
 379                 fsl,pins = <
 380                         /* Reset */
 381                         MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x838
 382                         /* IRQ */
 383                         MX6SX_PAD_KEY_ROW1__GPIO2_IO_16         0x70e0
 384                 >;
 385         };
 386
 387         pinctrl_uart1: uart1grp {
 388                 fsl,pins = <
 389                         MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
 390                         MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
 391                 >;
 392         };
 393
 394         pinctrl_uart2: uart2grp {
 395                 fsl,pins = <
 396                         MX6SX_PAD_GPIO1_IO06__UART2_TX          0x1b0b1
 397                         MX6SX_PAD_GPIO1_IO07__UART2_RX          0x1b0b1
 398                 >;
 399         };
 400
 401         pinctrl_usb_otg1: usbotg1grp {
 402                 fsl,pins = <
 403                         MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
 404                 >;
 405         };
 406
 407         pinctrl_usb_otg1_id: usbotg1idgrp {
 408                 fsl,pins = <
 409                         MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
 410                 >;
 411         };
 412
 413         pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
 414                 fsl,pins = <
 415                         MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
 416                         MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
 417                         MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
 418                         MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
 419                         MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
 420                         MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
 421                         MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28       0x1b000
 422                         MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26       0x10b0
 423                 >;
 424         };
 425
 426         pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
 427                 fsl,pins = <
 428                         MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x100b9
 429                         MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x170b9
 430                         MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x170b9
 431                         MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x170b9
 432                         MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x170b9
 433                         MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x170b9
 434                 >;
 435         };
 436
 437         pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
 438                 fsl,pins = <
 439                         MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x100f9
 440                         MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x170f9
 441                         MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x170f9
 442                         MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x170f9
 443                         MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x170f9
 444                         MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x170f9
 445                 >;
 446         };
 447
 448         pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
 449                 fsl,pins = <
 450                         MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
 451                         MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
 452                         MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
 453                         MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
 454                         MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
 455                         MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
 456                         MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x17059
 457                         MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x17059
 458                         MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x17059
 459                         MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x17059
 460                         MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B   0x17068
 461                 >;
 462         };
 463
 464         pinctrl_usdhc4_100mhz: usdhc4-100mhz {
 465                 fsl,pins = <
 466                         MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100b9
 467                         MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170b9
 468                         MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170b9
 469                         MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170b9
 470                         MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170b9
 471                         MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170b9
 472                         MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170b9
 473                         MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170b9
 474                         MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170b9
 475                         MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170b9
 476                 >;
 477         };
 478
 479         pinctrl_usdhc4_200mhz: usdhc4-200mhz {
 480                 fsl,pins = <
 481                         MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x100f9
 482                         MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x170f9
 483                         MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x170f9
 484                         MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x170f9
 485                         MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x170f9
 486                         MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x170f9
 487                         MX6SX_PAD_SD4_DATA4__USDHC4_DATA4       0x170f9
 488                         MX6SX_PAD_SD4_DATA5__USDHC4_DATA5       0x170f9
 489                         MX6SX_PAD_SD4_DATA6__USDHC4_DATA6       0x170f9
 490                         MX6SX_PAD_SD4_DATA7__USDHC4_DATA7       0x170f9
 491                 >;
 492         };
 493 };
 494
 495 &pwm1 {
 496         pinctrl-names = "default";
 497         pinctrl-0 = <&pinctrl_pwm1>;
 498         status = "okay";
 499 };
 500
 501 &pwm2 {
 502         pinctrl-names = "default";
 503         pinctrl-0 = <&pinctrl_pwm2>;
 504         status = "okay";
 505 };
 506
 507 &pwm6 {
 508         pinctrl-names = "default";
 509         pinctrl-0 = <&pinctrl_pwm6>;
 510         status = "okay";
 511 };
 512
 513 &reg_arm {
 514         vin-supply = <&sw1a_reg>;
 515 };
 516
 517 &reg_soc {
 518         vin-supply = <&sw1a_reg>;
 519 };
 520
 521 &snvs_poweroff {
 522         status = "okay";
 523 };
 524
 525 &uart1 {
 526         pinctrl-names = "default";
 527         pinctrl-0 = <&pinctrl_uart1>;
 528         status = "okay";
 529 };
 530
 531 &uart2 {
 532         pinctrl-names = "default";
 533         pinctrl-0 = <&pinctrl_uart2>;
 534         status = "okay";
 535 };
 536
 537 &usbotg1 {
 538         vbus-supply = <&reg_usb_otg1_vbus>;
 539         pinctrl-names = "default";
 540         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 541         status = "okay";
 542 };
 543
 544 &usbotg2 {
 545         dr_mode = "host";
 546         status = "okay";
 547 };
 548
 549 &usdhc2 {
 550         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 551         pinctrl-0 = <&pinctrl_usdhc2_50mhz>;
 552         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 553         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 554         cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
 555         keep-power-in-suspend;
 556         status = "okay";
 557 };
 558
 559 &usdhc4 {
 560         /* hs200-mode is currently unsupported because Vccq is on 3.1V, but
 561          * not on necessary 1.8V.
 562          */
 563         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 564         pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
 565         pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
 566         pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
 567         bus-width = <8>;
 568         keep-power-in-suspend;
 569         non-removable;
 570         cap-mmc-hw-reset;
 571         status = "okay";
 572 };