arch/arm/boot/dts/imx6ul-14x14-evk.dts

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include "imx6ul.dtsi"
  12
  13 / {
  14         model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
  15         compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
  16
  17         chosen {
  18                 stdout-path = &uart1;
  19         };
  20
  21         memory {
  22                 reg = <0x80000000 0x20000000>;
  23         };
  24
  25         backlight_display: backlight-display {
  26                 compatible = "pwm-backlight";
  27                 pwms = <&pwm1 0 5000000>;
  28                 brightness-levels = <0 4 8 16 32 64 128 255>;
  29                 default-brightness-level = <6>;
  30                 status = "okay";
  31         };
  32
  33
  34         reg_sd1_vmmc: regulator-sd1-vmmc {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "VSD_3V3";
  37                 regulator-min-microvolt = <3300000>;
  38                 regulator-max-microvolt = <3300000>;
  39                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  40                 enable-active-high;
  41         };
  42
  43         sound {
  44                 compatible = "simple-audio-card";
  45                 simple-audio-card,name = "mx6ul-wm8960";
  46                 simple-audio-card,format = "i2s";
  47                 simple-audio-card,bitclock-master = <&dailink_master>;
  48                 simple-audio-card,frame-master = <&dailink_master>;
  49                 simple-audio-card,widgets =
  50                         "Microphone", "Mic Jack",
  51                         "Line", "Line In",
  52                         "Line", "Line Out",
  53                         "Speaker", "Speaker",
  54                         "Headphone", "Headphone Jack";
  55                 simple-audio-card,routing =
  56                         "Headphone Jack", "HP_L",
  57                         "Headphone Jack", "HP_R",
  58                         "Speaker", "SPK_LP",
  59                         "Speaker", "SPK_LN",
  60                         "Speaker", "SPK_RP",
  61                         "Speaker", "SPK_RN",
  62                         "LINPUT1", "Mic Jack",
  63                         "LINPUT3", "Mic Jack",
  64                         "RINPUT1", "Mic Jack",
  65                         "RINPUT2", "Mic Jack";
  66
  67                 simple-audio-card,cpu {
  68                         sound-dai = <&sai2>;
  69                 };
  70
  71                 dailink_master: simple-audio-card,codec {
  72                         sound-dai = <&codec>;
  73                         clocks = <&clks IMX6UL_CLK_SAI2>;
  74                 };
  75         };
  76
  77         panel {
  78                 compatible = "innolux,at043tn24";
  79                 backlight = <&backlight_display>;
  80
  81                 port {
  82                         panel_in: endpoint {
  83                                 remote-endpoint = <&display_out>;
  84                         };
  85                 };
  86         };
  87 };
  88
  89 &clks {
  90         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
  91         assigned-clock-rates = <786432000>;
  92 };
  93
  94 &i2c2 {
  95         clock_frequency = <100000>;
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_i2c2>;
  98         status = "okay";
  99
 100         codec: wm8960@1a {
 101                 #sound-dai-cells = <0>;
 102                 compatible = "wlf,wm8960";
 103                 reg = <0x1a>;
 104                 wlf,shared-lrclk;
 105         };
 106 };
 107
 108 &fec1 {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_enet1>;
 111         phy-mode = "rmii";
 112         phy-handle = <&ethphy0>;
 113         status = "okay";
 114 };
 115
 116 &fec2 {
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_enet2>;
 119         phy-mode = "rmii";
 120         phy-handle = <&ethphy1>;
 121         status = "okay";
 122
 123         mdio {
 124                 #address-cells = <1>;
 125                 #size-cells = <0>;
 126
 127                 ethphy0: ethernet-phy@2 {
 128                         reg = <2>;
 129                         micrel,led-mode = <1>;
 130                         clocks = <&clks IMX6UL_CLK_ENET_REF>;
 131                         clock-names = "rmii-ref";
 132                 };
 133
 134                 ethphy1: ethernet-phy@1 {
 135                         reg = <1>;
 136                         micrel,led-mode = <1>;
 137                         clocks = <&clks IMX6UL_CLK_ENET2_REF>;
 138                         clock-names = "rmii-ref";
 139                 };
 140         };
 141 };
 142
 143
 144 &lcdif {
 145         assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
 146         assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
 147         pinctrl-names = "default";
 148         pinctrl-0 = <&pinctrl_lcdif_dat
 149                      &pinctrl_lcdif_ctrl>;
 150         status = "okay";
 151
 152         port {
 153                 display_out: endpoint {
 154                         remote-endpoint = <&panel_in>;
 155                 };
 156         };
 157 };
 158
 159 &pwm1 {
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_pwm1>;
 162         status = "okay";
 163 };
 164
 165 &qspi {
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_qspi>;
 168         status = "okay";
 169
 170         flash0: n25q256a@0 {
 171                 #address-cells = <1>;
 172                 #size-cells = <1>;
 173                 compatible = "micron,n25q256a";
 174                 spi-max-frequency = <29000000>;
 175                 reg = <0>;
 176         };
 177 };
 178
 179 &sai2 {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_sai2>;
 182         assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
 183                           <&clks IMX6UL_CLK_SAI2>;
 184         assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 185         assigned-clock-rates = <0>, <12288000>;
 186         fsl,sai-mclk-direction-output;
 187         status = "okay";
 188 };
 189
 190 &snvs_poweroff {
 191         status = "okay";
 192 };
 193
 194 &tsc {
 195         pinctrl-names = "default";
 196         pinctrl-0 = <&pinctrl_tsc>;
 197         xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 198         measure-delay-time = <0xffff>;
 199         pre-charge-time = <0xfff>;
 200         status = "okay";
 201 };
 202
 203 &uart1 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_uart1>;
 206         status = "okay";
 207 };
 208
 209 &uart2 {
 210         pinctrl-names = "default";
 211         pinctrl-0 = <&pinctrl_uart2>;
 212         uart-has-rtscts;
 213         status = "okay";
 214 };
 215
 216 &usbotg1 {
 217         dr_mode = "otg";
 218         status = "okay";
 219 };
 220
 221 &usbotg2 {
 222         dr_mode = "host";
 223         disable-over-current;
 224         status = "okay";
 225 };
 226
 227 &usbphy1 {
 228         fsl,tx-d-cal = <106>;
 229 };
 230
 231 &usbphy2 {
 232         fsl,tx-d-cal = <106>;
 233 };
 234
 235 &usdhc1 {
 236         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 237         pinctrl-0 = <&pinctrl_usdhc1>;
 238         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 239         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 240         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 241         keep-power-in-suspend;
 242         wakeup-source;
 243         vmmc-supply = <&reg_sd1_vmmc>;
 244         status = "okay";
 245 };
 246
 247 &usdhc2 {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pinctrl_usdhc2>;
 250         no-1-8-v;
 251         keep-power-in-suspend;
 252         wakeup-source;
 253         status = "okay";
 254 };
 255
 256 &wdog1 {
 257         pinctrl-names = "default";
 258         pinctrl-0 = <&pinctrl_wdog>;
 259         fsl,ext-reset-output;
 260 };
 261
 262 &iomuxc {
 263         pinctrl-names = "default";
 264
 265         pinctrl_csi1: csi1grp {
 266                 fsl,pins = <
 267                         MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
 268                         MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
 269                         MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
 270                         MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
 271                         MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
 272                         MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
 273                         MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
 274                         MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
 275                         MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
 276                         MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
 277                         MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
 278                         MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
 279                 >;
 280         };
 281
 282         pinctrl_enet1: enet1grp {
 283                 fsl,pins = <
 284                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 285                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 286                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 287                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 288                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 289                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 290                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 291                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 292                 >;
 293         };
 294
 295         pinctrl_enet2: enet2grp {
 296                 fsl,pins = <
 297                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 298                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 299                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 300                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 301                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 302                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 303                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 304                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 305                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 306                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 307                 >;
 308         };
 309
 310         pinctrl_flexcan1: flexcan1grp{
 311                 fsl,pins = <
 312                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 313                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 314                 >;
 315         };
 316
 317         pinctrl_flexcan2: flexcan2grp{
 318                 fsl,pins = <
 319                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 320                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 321                 >;
 322         };
 323
 324         pinctrl_i2c1: i2c1grp {
 325                 fsl,pins = <
 326                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 327                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 328                 >;
 329         };
 330
 331         pinctrl_i2c2: i2c2grp {
 332                 fsl,pins = <
 333                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 334                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 335                 >;
 336         };
 337
 338         pinctrl_lcdif_dat: lcdifdatgrp {
 339                 fsl,pins = <
 340                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 341                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 342                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 343                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 344                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 345                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 346                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 347                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 348                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 349                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 350                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 351                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 352                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 353                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 354                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 355                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 356                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 357                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 358                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
 359                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
 360                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
 361                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
 362                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
 363                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
 364                 >;
 365         };
 366
 367         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 368                 fsl,pins = <
 369                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 370                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 371                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 372                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 373                         /* used for lcd reset */
 374                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
 375                 >;
 376         };
 377
 378         pinctrl_qspi: qspigrp {
 379                 fsl,pins = <
 380                         MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
 381                         MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
 382                         MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
 383                         MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
 384                         MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
 385                         MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
 386                 >;
 387         };
 388
 389         pinctrl_sai2: sai2grp {
 390                 fsl,pins = <
 391                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
 392                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
 393                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
 394                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
 395                         MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
 396                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
 397                 >;
 398         };
 399
 400         pinctrl_pwm1: pwm1grp {
 401                 fsl,pins = <
 402                         MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
 403                 >;
 404         };
 405
 406         pinctrl_sim2: sim2grp {
 407                 fsl,pins = <
 408                         MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
 409                         MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
 410                         MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
 411                         MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
 412                         MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
 413                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
 414                 >;
 415         };
 416
 417         pinctrl_tsc: tscgrp {
 418                 fsl,pins = <
 419                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
 420                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
 421                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
 422                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
 423                 >;
 424         };
 425
 426         pinctrl_uart1: uart1grp {
 427                 fsl,pins = <
 428                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 429                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 430                 >;
 431         };
 432
 433         pinctrl_uart2: uart2grp {
 434                 fsl,pins = <
 435                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 436                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 437                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
 438                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
 439                 >;
 440         };
 441
 442         pinctrl_usdhc1: usdhc1grp {
 443                 fsl,pins = <
 444                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 445                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 446                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 447                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 448                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 449                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 450                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
 451                         MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
 452                         MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
 453                 >;
 454         };
 455
 456         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 457                 fsl,pins = <
 458                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 459                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
 460                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
 461                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
 462                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
 463                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
 464
 465                 >;
 466         };
 467
 468         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 469                 fsl,pins = <
 470                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 471                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
 472                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
 473                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
 474                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
 475                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
 476                 >;
 477         };
 478
 479         pinctrl_usdhc2: usdhc2grp {
 480                 fsl,pins = <
 481                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
 482                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
 483                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
 484                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
 485                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
 486                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
 487                 >;
 488         };
 489
 490         pinctrl_wdog: wdoggrp {
 491                 fsl,pins = <
 492                         MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
 493                 >;
 494         };
 495 };