| blob | 9aa2bb998552b78f3b9875ee570aec1496ba0fab |
1 /*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * Copyright 2016 Toradex AG
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
44 #include <dt-bindings/clock/imx7d-clock.h>
45 #include <dt-bindings/power/imx7-power.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/input/input.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include "imx7d-pinfunc.h"
51 / {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 /*
55 * The decompressor and also some bootloaders rely on a
56 * pre-existing /chosen node to be available to insert the
57 * command line and merge other ATAGS info.
58 * Also for U-Boot there must be a pre-existing /memory node.
59 */
60 chosen {};
61 memory { device_type = "memory"; reg = <0 0>; };
63 aliases {
64 gpio0 = &gpio1;
65 gpio1 = &gpio2;
66 gpio2 = &gpio3;
67 gpio3 = &gpio4;
68 gpio4 = &gpio5;
69 gpio5 = &gpio6;
70 gpio6 = &gpio7;
71 i2c0 = &i2c1;
72 i2c1 = &i2c2;
73 i2c2 = &i2c3;
74 i2c3 = &i2c4;
75 mmc0 = &usdhc1;
76 mmc1 = &usdhc2;
77 mmc2 = &usdhc3;
78 serial0 = &uart1;
79 serial1 = &uart2;
80 serial2 = &uart3;
81 serial3 = &uart4;
82 serial4 = &uart5;
83 serial5 = &uart6;
84 serial6 = &uart7;
85 spi0 = &ecspi1;
86 spi1 = &ecspi2;
87 spi2 = &ecspi3;
88 spi3 = &ecspi4;
89 };
91 cpus {
92 #address-cells = <1>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
96 compatible = "arm,cortex-a7";
97 device_type = "cpu";
98 reg = <0>;
99 clock-frequency = <792000000>;
100 clock-latency = <61036>; /* two CLK32 periods */
101 clocks = <&clks IMX7D_CLK_ARM>;
102 };
103 };
105 ckil: clock-cki {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <32768>;
109 clock-output-names = "ckil";
110 };
112 osc: clock-osc {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <24000000>;
116 clock-output-names = "osc";
117 };
119 usbphynop1: usbphynop1 {
120 compatible = "usb-nop-xceiv";
121 clocks = <&clks IMX7D_USB_PHY1_CLK>;
122 clock-names = "main_clk";
123 #phy-cells = <0>;
124 };
126 usbphynop3: usbphynop3 {
127 compatible = "usb-nop-xceiv";
128 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
129 clock-names = "main_clk";
130 #phy-cells = <0>;
131 };
134 replicator {
135 /*
136 * non-configurable replicators don't show up on the
137 * AMBA bus. As such no need to add "arm,primecell"
138 */
139 compatible = "arm,coresight-replicator";
141 ports {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 /* replicator output ports */
145 port@0 {
146 reg = <0>;
147 replicator_out_port0: endpoint {
148 remote-endpoint = <&tpiu_in_port>;
149 };
150 };
152 port@1 {
153 reg = <1>;
154 replicator_out_port1: endpoint {
155 remote-endpoint = <&etr_in_port>;
156 };
157 };
159 /* replicator input port */
160 port@2 {
161 reg = <0>;
162 replicator_in_port0: endpoint {
163 slave-mode;
164 remote-endpoint = <&etf_out_port>;
165 };
166 };
167 };
168 };
170 timer {
171 compatible = "arm,armv7-timer";
172 interrupt-parent = <&intc>;
173 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
174 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
175 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
176 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
177 };
179 soc {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 compatible = "simple-bus";
183 interrupt-parent = <&gpc>;
184 ranges;
186 funnel@30041000 {
187 compatible = "arm,coresight-funnel", "arm,primecell";
188 reg = <0x30041000 0x1000>;
189 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
190 clock-names = "apb_pclk";
192 ca_funnel_ports: ports {
193 #address-cells = <1>;
194 #size-cells = <0>;
196 /* funnel input ports */
197 port@0 {
198 reg = <0>;
199 ca_funnel_in_port0: endpoint {
200 slave-mode;
201 remote-endpoint = <&etm0_out_port>;
202 };
203 };
205 /* funnel output port */
206 port@2 {
207 reg = <0>;
208 ca_funnel_out_port0: endpoint {
209 remote-endpoint = <&hugo_funnel_in_port0>;
210 };
211 };
213 /* the other input ports are not connect to anything */
214 };
215 };
217 etm@3007c000 {
218 compatible = "arm,coresight-etm3x", "arm,primecell";
219 reg = <0x3007c000 0x1000>;
220 cpu = <&cpu0>;
221 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
222 clock-names = "apb_pclk";
224 port {
225 etm0_out_port: endpoint {
226 remote-endpoint = <&ca_funnel_in_port0>;
227 };
228 };
229 };
231 funnel@30083000 {
232 compatible = "arm,coresight-funnel", "arm,primecell";
233 reg = <0x30083000 0x1000>;
234 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
235 clock-names = "apb_pclk";
237 ports {
238 #address-cells = <1>;
239 #size-cells = <0>;
241 /* funnel input ports */
242 port@0 {
243 reg = <0>;
244 hugo_funnel_in_port0: endpoint {
245 slave-mode;
246 remote-endpoint = <&ca_funnel_out_port0>;
247 };
248 };
250 port@1 {
251 reg = <1>;
252 hugo_funnel_in_port1: endpoint {
253 slave-mode; /* M4 input */
254 };
255 };
257 port@2 {
258 reg = <0>;
259 hugo_funnel_out_port0: endpoint {
260 remote-endpoint = <&etf_in_port>;
261 };
262 };
264 /* the other input ports are not connect to anything */
265 };
266 };
268 etf@30084000 {
269 compatible = "arm,coresight-tmc", "arm,primecell";
270 reg = <0x30084000 0x1000>;
271 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
272 clock-names = "apb_pclk";
274 ports {
275 #address-cells = <1>;
276 #size-cells = <0>;
278 port@0 {
279 reg = <0>;
280 etf_in_port: endpoint {
281 slave-mode;
282 remote-endpoint = <&hugo_funnel_out_port0>;
283 };
284 };
286 port@1 {
287 reg = <0>;
288 etf_out_port: endpoint {
289 remote-endpoint = <&replicator_in_port0>;
290 };
291 };
292 };
293 };
295 etr@30086000 {
296 compatible = "arm,coresight-tmc", "arm,primecell";
297 reg = <0x30086000 0x1000>;
298 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
299 clock-names = "apb_pclk";
301 port {
302 etr_in_port: endpoint {
303 slave-mode;
304 remote-endpoint = <&replicator_out_port1>;
305 };
306 };
307 };
309 tpiu@30087000 {
310 compatible = "arm,coresight-tpiu", "arm,primecell";
311 reg = <0x30087000 0x1000>;
312 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
313 clock-names = "apb_pclk";
315 port {
316 tpiu_in_port: endpoint {
317 slave-mode;
318 remote-endpoint = <&replicator_out_port1>;
319 };
320 };
321 };
323 intc: interrupt-controller@31001000 {
324 compatible = "arm,cortex-a7-gic";
325 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
326 #interrupt-cells = <3>;
327 interrupt-controller;
328 interrupt-parent = <&intc>;
329 reg = <0x31001000 0x1000>,
330 <0x31002000 0x2000>,
331 <0x31004000 0x2000>,
332 <0x31006000 0x2000>;
333 };
335 aips1: aips-bus@30000000 {
336 compatible = "fsl,aips-bus", "simple-bus";
337 #address-cells = <1>;
338 #size-cells = <1>;
339 reg = <0x30000000 0x400000>;
340 ranges;
342 gpio1: gpio@30200000 {
343 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
344 reg = <0x30200000 0x10000>;
345 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
346 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
347 gpio-controller;
348 #gpio-cells = <2>;
349 interrupt-controller;
350 #interrupt-cells = <2>;
351 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
352 };
354 gpio2: gpio@30210000 {
355 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
356 reg = <0x30210000 0x10000>;
357 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
359 gpio-controller;
360 #gpio-cells = <2>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
363 gpio-ranges = <&iomuxc 0 13 32>;
364 };
366 gpio3: gpio@30220000 {
367 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
368 reg = <0x30220000 0x10000>;
369 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 gpio-ranges = <&iomuxc 0 45 29>;
376 };
378 gpio4: gpio@30230000 {
379 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
380 reg = <0x30230000 0x10000>;
381 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
383 gpio-controller;
384 #gpio-cells = <2>;
385 interrupt-controller;
386 #interrupt-cells = <2>;
387 gpio-ranges = <&iomuxc 0 74 24>;
388 };
390 gpio5: gpio@30240000 {
391 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
392 reg = <0x30240000 0x10000>;
393 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
395 gpio-controller;
396 #gpio-cells = <2>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
399 gpio-ranges = <&iomuxc 0 98 18>;
400 };
402 gpio6: gpio@30250000 {
403 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
404 reg = <0x30250000 0x10000>;
405 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 gpio-ranges = <&iomuxc 0 116 23>;
412 };
414 gpio7: gpio@30260000 {
415 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
416 reg = <0x30260000 0x10000>;
417 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
419 gpio-controller;
420 #gpio-cells = <2>;
421 interrupt-controller;
422 #interrupt-cells = <2>;
423 gpio-ranges = <&iomuxc 0 139 16>;
424 };
426 wdog1: wdog@30280000 {
427 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
428 reg = <0x30280000 0x10000>;
429 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
431 };
433 wdog2: wdog@30290000 {
434 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
435 reg = <0x30290000 0x10000>;
436 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
438 status = "disabled";
439 };
441 wdog3: wdog@302a0000 {
442 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
443 reg = <0x302a0000 0x10000>;
444 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
446 status = "disabled";
447 };
449 wdog4: wdog@302b0000 {
450 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
451 reg = <0x302b0000 0x10000>;
452 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
454 status = "disabled";
455 };
457 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
458 compatible = "fsl,imx7d-iomuxc-lpsr";
459 reg = <0x302c0000 0x10000>;
460 fsl,input-sel = <&iomuxc>;
461 };
463 gpt1: gpt@302d0000 {
464 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
465 reg = <0x302d0000 0x10000>;
466 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&clks IMX7D_CLK_DUMMY>,
468 <&clks IMX7D_GPT1_ROOT_CLK>;
469 clock-names = "ipg", "per";
470 };
472 gpt2: gpt@302e0000 {
473 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
474 reg = <0x302e0000 0x10000>;
475 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&clks IMX7D_CLK_DUMMY>,
477 <&clks IMX7D_GPT2_ROOT_CLK>;
478 clock-names = "ipg", "per";
479 status = "disabled";
480 };
482 gpt3: gpt@302f0000 {
483 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
484 reg = <0x302f0000 0x10000>;
485 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clks IMX7D_CLK_DUMMY>,
487 <&clks IMX7D_GPT3_ROOT_CLK>;
488 clock-names = "ipg", "per";
489 status = "disabled";
490 };
492 gpt4: gpt@30300000 {
493 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
494 reg = <0x30300000 0x10000>;
495 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clks IMX7D_CLK_DUMMY>,
497 <&clks IMX7D_GPT4_ROOT_CLK>;
498 clock-names = "ipg", "per";
499 status = "disabled";
500 };
502 iomuxc: iomuxc@30330000 {
503 compatible = "fsl,imx7d-iomuxc";
504 reg = <0x30330000 0x10000>;
505 };
507 gpr: iomuxc-gpr@30340000 {
508 compatible = "fsl,imx7d-iomuxc-gpr",
509 "fsl,imx6q-iomuxc-gpr", "syscon";
510 reg = <0x30340000 0x10000>;
511 };
513 ocotp: ocotp-ctrl@30350000 {
514 compatible = "fsl,imx7d-ocotp", "syscon";
515 reg = <0x30350000 0x10000>;
516 clocks = <&clks IMX7D_OCOTP_CLK>;
517 };
519 anatop: anatop@30360000 {
520 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
521 "syscon", "simple-bus";
522 reg = <0x30360000 0x10000>;
523 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
525 #address-cells = <1>;
526 #size-cells = <0>;
528 reg_1p0d: regulator-vdd1p0d@30360210 {
529 reg = <0x30360210>;
530 compatible = "fsl,anatop-regulator";
531 regulator-name = "vdd1p0d";
532 regulator-min-microvolt = <800000>;
533 regulator-max-microvolt = <1200000>;
534 anatop-reg-offset = <0x210>;
535 anatop-vol-bit-shift = <8>;
536 anatop-vol-bit-width = <5>;
537 anatop-min-bit-val = <8>;
538 anatop-min-voltage = <800000>;
539 anatop-max-voltage = <1200000>;
540 anatop-enable-bit = <0>;
541 };
542 };
544 snvs: snvs@30370000 {
545 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
546 reg = <0x30370000 0x10000>;
548 snvs_rtc: snvs-rtc-lp {
549 compatible = "fsl,sec-v4.0-mon-rtc-lp";
550 regmap = <&snvs>;
551 offset = <0x34>;
552 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
554 };
556 snvs_poweroff: snvs-poweroff {
557 compatible = "syscon-poweroff";
558 regmap = <&snvs>;
559 offset = <0x38>;
560 value = <0x60>;
561 mask = <0x60>;
562 };
564 snvs_pwrkey: snvs-powerkey {
565 compatible = "fsl,sec-v4.0-pwrkey";
566 regmap = <&snvs>;
567 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
568 linux,keycode = <KEY_POWER>;
569 wakeup-source;
570 };
571 };
573 clks: ccm@30380000 {
574 compatible = "fsl,imx7d-ccm";
575 reg = <0x30380000 0x10000>;
576 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
578 #clock-cells = <1>;
579 clocks = <&ckil>, <&osc>;
580 clock-names = "ckil", "osc";
581 };
583 src: src@30390000 {
584 compatible = "fsl,imx7d-src", "syscon";
585 reg = <0x30390000 0x10000>;
586 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
587 #reset-cells = <1>;
588 };
590 gpc: gpc@303a0000 {
591 compatible = "fsl,imx7d-gpc";
592 reg = <0x303a0000 0x10000>;
593 interrupt-controller;
594 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
595 #interrupt-cells = <3>;
596 interrupt-parent = <&intc>;
597 #power-domain-cells = <1>;
599 pgc {
600 #address-cells = <1>;
601 #size-cells = <0>;
603 pgc_pcie_phy: pgc-power-domain@1 {
604 #power-domain-cells = <0>;
605 reg = <1>;
606 power-supply = <®_1p0d>;
607 };
608 };
609 };
610 };
612 aips2: aips-bus@30400000 {
613 compatible = "fsl,aips-bus", "simple-bus";
614 #address-cells = <1>;
615 #size-cells = <1>;
616 reg = <0x30400000 0x400000>;
617 ranges;
619 adc1: adc@30610000 {
620 compatible = "fsl,imx7d-adc";
621 reg = <0x30610000 0x10000>;
622 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
624 clock-names = "adc";
625 status = "disabled";
626 };
628 adc2: adc@30620000 {
629 compatible = "fsl,imx7d-adc";
630 reg = <0x30620000 0x10000>;
631 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
633 clock-names = "adc";
634 status = "disabled";
635 };
637 ecspi4: ecspi@30630000 {
638 #address-cells = <1>;
639 #size-cells = <0>;
640 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
641 reg = <0x30630000 0x10000>;
642 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
644 <&clks IMX7D_ECSPI4_ROOT_CLK>;
645 clock-names = "ipg", "per";
646 status = "disabled";
647 };
649 pwm1: pwm@30660000 {
650 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
651 reg = <0x30660000 0x10000>;
652 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
654 <&clks IMX7D_PWM1_ROOT_CLK>;
655 clock-names = "ipg", "per";
656 #pwm-cells = <3>;
657 status = "disabled";
658 };
660 pwm2: pwm@30670000 {
661 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
662 reg = <0x30670000 0x10000>;
663 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
665 <&clks IMX7D_PWM2_ROOT_CLK>;
666 clock-names = "ipg", "per";
667 #pwm-cells = <3>;
668 status = "disabled";
669 };
671 pwm3: pwm@30680000 {
672 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
673 reg = <0x30680000 0x10000>;
674 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
676 <&clks IMX7D_PWM3_ROOT_CLK>;
677 clock-names = "ipg", "per";
678 #pwm-cells = <3>;
679 status = "disabled";
680 };
682 pwm4: pwm@30690000 {
683 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
684 reg = <0x30690000 0x10000>;
685 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
687 <&clks IMX7D_PWM4_ROOT_CLK>;
688 clock-names = "ipg", "per";
689 #pwm-cells = <3>;
690 status = "disabled";
691 };
693 lcdif: lcdif@30730000 {
694 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
695 reg = <0x30730000 0x10000>;
696 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
698 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
699 clock-names = "pix", "axi";
700 status = "disabled";
701 };
702 };
704 aips3: aips-bus@30800000 {
705 compatible = "fsl,aips-bus", "simple-bus";
706 #address-cells = <1>;
707 #size-cells = <1>;
708 reg = <0x30800000 0x400000>;
709 ranges;
711 ecspi1: ecspi@30820000 {
712 #address-cells = <1>;
713 #size-cells = <0>;
714 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
715 reg = <0x30820000 0x10000>;
716 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
718 <&clks IMX7D_ECSPI1_ROOT_CLK>;
719 clock-names = "ipg", "per";
720 status = "disabled";
721 };
723 ecspi2: ecspi@30830000 {
724 #address-cells = <1>;
725 #size-cells = <0>;
726 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
727 reg = <0x30830000 0x10000>;
728 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
730 <&clks IMX7D_ECSPI2_ROOT_CLK>;
731 clock-names = "ipg", "per";
732 status = "disabled";
733 };
735 ecspi3: ecspi@30840000 {
736 #address-cells = <1>;
737 #size-cells = <0>;
738 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
739 reg = <0x30840000 0x10000>;
740 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
742 <&clks IMX7D_ECSPI3_ROOT_CLK>;
743 clock-names = "ipg", "per";
744 status = "disabled";
745 };
747 uart1: serial@30860000 {
748 compatible = "fsl,imx7d-uart",
749 "fsl,imx6q-uart";
750 reg = <0x30860000 0x10000>;
751 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
753 <&clks IMX7D_UART1_ROOT_CLK>;
754 clock-names = "ipg", "per";
755 status = "disabled";
756 };
758 uart2: serial@30890000 {
759 compatible = "fsl,imx7d-uart",
760 "fsl,imx6q-uart";
761 reg = <0x30890000 0x10000>;
762 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
764 <&clks IMX7D_UART2_ROOT_CLK>;
765 clock-names = "ipg", "per";
766 status = "disabled";
767 };
769 uart3: serial@30880000 {
770 compatible = "fsl,imx7d-uart",
771 "fsl,imx6q-uart";
772 reg = <0x30880000 0x10000>;
773 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
775 <&clks IMX7D_UART3_ROOT_CLK>;
776 clock-names = "ipg", "per";
777 status = "disabled";
778 };
780 sai1: sai@308a0000 {
781 #sound-dai-cells = <0>;
782 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
783 reg = <0x308a0000 0x10000>;
784 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
786 <&clks IMX7D_SAI1_ROOT_CLK>,
787 <&clks IMX7D_CLK_DUMMY>,
788 <&clks IMX7D_CLK_DUMMY>;
789 clock-names = "bus", "mclk1", "mclk2", "mclk3";
790 dma-names = "rx", "tx";
791 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
792 status = "disabled";
793 };
795 sai2: sai@308b0000 {
796 #sound-dai-cells = <0>;
797 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
798 reg = <0x308b0000 0x10000>;
799 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
801 <&clks IMX7D_SAI2_ROOT_CLK>,
802 <&clks IMX7D_CLK_DUMMY>,
803 <&clks IMX7D_CLK_DUMMY>;
804 clock-names = "bus", "mclk1", "mclk2", "mclk3";
805 dma-names = "rx", "tx";
806 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
807 status = "disabled";
808 };
810 sai3: sai@308c0000 {
811 #sound-dai-cells = <0>;
812 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
813 reg = <0x308c0000 0x10000>;
814 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
816 <&clks IMX7D_SAI3_ROOT_CLK>,
817 <&clks IMX7D_CLK_DUMMY>,
818 <&clks IMX7D_CLK_DUMMY>;
819 clock-names = "bus", "mclk1", "mclk2", "mclk3";
820 dma-names = "rx", "tx";
821 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
822 status = "disabled";
823 };
825 flexcan1: can@30a00000 {
826 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
827 reg = <0x30a00000 0x10000>;
828 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clks IMX7D_CLK_DUMMY>,
830 <&clks IMX7D_CAN1_ROOT_CLK>;
831 clock-names = "ipg", "per";
832 status = "disabled";
833 };
835 flexcan2: can@30a10000 {
836 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
837 reg = <0x30a10000 0x10000>;
838 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&clks IMX7D_CLK_DUMMY>,
840 <&clks IMX7D_CAN2_ROOT_CLK>;
841 clock-names = "ipg", "per";
842 status = "disabled";
843 };
845 i2c1: i2c@30a20000 {
846 #address-cells = <1>;
847 #size-cells = <0>;
848 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
849 reg = <0x30a20000 0x10000>;
850 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
852 status = "disabled";
853 };
855 i2c2: i2c@30a30000 {
856 #address-cells = <1>;
857 #size-cells = <0>;
858 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
859 reg = <0x30a30000 0x10000>;
860 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
862 status = "disabled";
863 };
865 i2c3: i2c@30a40000 {
866 #address-cells = <1>;
867 #size-cells = <0>;
868 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
869 reg = <0x30a40000 0x10000>;
870 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
872 status = "disabled";
873 };
875 i2c4: i2c@30a50000 {
876 #address-cells = <1>;
877 #size-cells = <0>;
878 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
879 reg = <0x30a50000 0x10000>;
880 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
882 status = "disabled";
883 };
885 uart4: serial@30a60000 {
886 compatible = "fsl,imx7d-uart",
887 "fsl,imx6q-uart";
888 reg = <0x30a60000 0x10000>;
889 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
891 <&clks IMX7D_UART4_ROOT_CLK>;
892 clock-names = "ipg", "per";
893 status = "disabled";
894 };
896 uart5: serial@30a70000 {
897 compatible = "fsl,imx7d-uart",
898 "fsl,imx6q-uart";
899 reg = <0x30a70000 0x10000>;
900 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
902 <&clks IMX7D_UART5_ROOT_CLK>;
903 clock-names = "ipg", "per";
904 status = "disabled";
905 };
907 uart6: serial@30a80000 {
908 compatible = "fsl,imx7d-uart",
909 "fsl,imx6q-uart";
910 reg = <0x30a80000 0x10000>;
911 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
913 <&clks IMX7D_UART6_ROOT_CLK>;
914 clock-names = "ipg", "per";
915 status = "disabled";
916 };
918 uart7: serial@30a90000 {
919 compatible = "fsl,imx7d-uart",
920 "fsl,imx6q-uart";
921 reg = <0x30a90000 0x10000>;
922 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
924 <&clks IMX7D_UART7_ROOT_CLK>;
925 clock-names = "ipg", "per";
926 status = "disabled";
927 };
929 usbotg1: usb@30b10000 {
930 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
931 reg = <0x30b10000 0x200>;
932 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&clks IMX7D_USB_CTRL_CLK>;
934 fsl,usbphy = <&usbphynop1>;
935 fsl,usbmisc = <&usbmisc1 0>;
936 phy-clkgate-delay-us = <400>;
937 status = "disabled";
938 };
940 usbh: usb@30b30000 {
941 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
942 reg = <0x30b30000 0x200>;
943 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&clks IMX7D_USB_CTRL_CLK>;
945 fsl,usbphy = <&usbphynop3>;
946 fsl,usbmisc = <&usbmisc3 0>;
947 phy_type = "hsic";
948 dr_mode = "host";
949 phy-clkgate-delay-us = <400>;
950 status = "disabled";
951 };
953 usbmisc1: usbmisc@30b10200 {
954 #index-cells = <1>;
955 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
956 reg = <0x30b10200 0x200>;
957 };
959 usbmisc3: usbmisc@30b30200 {
960 #index-cells = <1>;
961 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
962 reg = <0x30b30200 0x200>;
963 };
965 usdhc1: usdhc@30b40000 {
966 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
967 reg = <0x30b40000 0x10000>;
968 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
970 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
971 <&clks IMX7D_USDHC1_ROOT_CLK>;
972 clock-names = "ipg", "ahb", "per";
973 bus-width = <4>;
974 status = "disabled";
975 };
977 usdhc2: usdhc@30b50000 {
978 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
979 reg = <0x30b50000 0x10000>;
980 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
982 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
983 <&clks IMX7D_USDHC2_ROOT_CLK>;
984 clock-names = "ipg", "ahb", "per";
985 bus-width = <4>;
986 status = "disabled";
987 };
989 usdhc3: usdhc@30b60000 {
990 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
991 reg = <0x30b60000 0x10000>;
992 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
994 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
995 <&clks IMX7D_USDHC3_ROOT_CLK>;
996 clock-names = "ipg", "ahb", "per";
997 bus-width = <4>;
998 status = "disabled";
999 };
1001 sdma: sdma@30bd0000 {
1002 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1003 reg = <0x30bd0000 0x10000>;
1004 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
1006 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
1007 clock-names = "ipg", "ahb";
1008 #dma-cells = <3>;
1009 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1010 };
1012 fec1: ethernet@30be0000 {
1013 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1014 reg = <0x30be0000 0x10000>;
1015 interrupt-names = "int0", "int1", "int2", "pps";
1016 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1018 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1019 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1021 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1022 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1023 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1024 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1025 clock-names = "ipg", "ahb", "ptp",
1026 "enet_clk_ref", "enet_out";
1027 fsl,num-tx-queues=<3>;
1028 fsl,num-rx-queues=<3>;
1029 status = "disabled";
1030 };
1031 };
1033 dma_apbh: dma-apbh@33000000 {
1034 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1035 reg = <0x33000000 0x2000>;
1036 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1040 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1041 #dma-cells = <1>;
1042 dma-channels = <4>;
1043 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1044 };
1046 gpmi: gpmi-nand@33002000{
1047 compatible = "fsl,imx7d-gpmi-nand";
1048 #address-cells = <1>;
1049 #size-cells = <1>;
1050 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1051 reg-names = "gpmi-nand", "bch";
1052 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1053 interrupt-names = "bch";
1054 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1055 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1056 clock-names = "gpmi_io", "gpmi_bch_apb";
1057 dmas = <&dma_apbh 0>;
1058 dma-names = "rx-tx";
1059 status = "disabled";
1060 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1061 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1062 };
1063 };
1064 };