arch/arm/boot/dts/logicpd-som-lv.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #include <dt-bindings/input/input.h>
   8
   9 / {
  10         cpus {
  11                 cpu@0 {
  12                         cpu0-supply = <&vcc>;
  13                 };
  14         };
  15
  16         memory@80000000 {
  17                 device_type = "memory";
  18                 reg = <0x80000000 0>;
  19         };
  20
  21         wl12xx_vmmc: wl12xx_vmmc {
  22                 compatible = "regulator-fixed";
  23                 regulator-name = "vwl1271";
  24                 regulator-min-microvolt = <1800000>;
  25                 regulator-max-microvolt = <1800000>;
  26                 gpio = <&gpio1 3 0>;   /* gpio_3 */
  27                 startup-delay-us = <70000>;
  28                 enable-active-high;
  29                 vin-supply = <&vmmc2>;
  30         };
  31
  32         /* HS USB Host PHY on PORT 1 */
  33         hsusb2_phy: hsusb2_phy {
  34                 compatible = "usb-nop-xceiv";
  35                 reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
  36                 #phy-cells = <0>;
  37         };
  38 };
  39
  40 &gpmc {
  41         ranges = <0 0 0x30000000 0x1000000>;    /* CS0: 16MB for NAND */
  42
  43         nand@0,0 {
  44                 compatible = "ti,omap2-nand";
  45                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  46                 interrupt-parent = <&gpmc>;
  47                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  48                              <1 IRQ_TYPE_NONE>; /* termcount */
  49                 linux,mtd-name = "micron,mt29f4g16abbda3w";
  50                 nand-bus-width = <16>;
  51                 ti,nand-ecc-opt = "bch8";
  52                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  53                 gpmc,sync-clk-ps = <0>;
  54                 gpmc,cs-on-ns = <0>;
  55                 gpmc,cs-rd-off-ns = <44>;
  56                 gpmc,cs-wr-off-ns = <44>;
  57                 gpmc,adv-on-ns = <6>;
  58                 gpmc,adv-rd-off-ns = <34>;
  59                 gpmc,adv-wr-off-ns = <44>;
  60                 gpmc,we-off-ns = <40>;
  61                 gpmc,oe-off-ns = <54>;
  62                 gpmc,access-ns = <64>;
  63                 gpmc,rd-cycle-ns = <82>;
  64                 gpmc,wr-cycle-ns = <82>;
  65                 gpmc,wr-access-ns = <40>;
  66                 gpmc,wr-data-mux-bus-ns = <0>;
  67                 gpmc,device-width = <2>;
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70         };
  71 };
  72
  73 &i2c1 {
  74         clock-frequency = <2600000>;
  75
  76         twl: twl@48 {
  77                 reg = <0x48>;
  78                 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  79                 interrupt-parent = <&intc>;
  80                 twl_audio: audio {
  81                         compatible = "ti,twl4030-audio";
  82                         codec {
  83                         };
  84                 };
  85         };
  86 };
  87
  88 &i2c2 {
  89         clock-frequency = <400000>;
  90 };
  91
  92 &i2c3 {
  93         clock-frequency = <400000>;
  94 };
  95
  96 &mmc3 {
  97         interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
  98         pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
  99         pinctrl-names = "default";
 100         vmmc-supply = <&wl12xx_vmmc>;
 101         non-removable;
 102         bus-width = <4>;
 103         cap-power-off-card;
 104         #address-cells = <1>;
 105         #size-cells = <0>;
 106         wlcore: wlcore@2 {
 107                 compatible = "ti,wl1273";
 108                 reg = <2>;
 109                 interrupt-parent = <&gpio1>;
 110                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */
 111                 ref-clock-frequency = <26000000>;
 112         };
 113 };
 114
 115 &usbhshost {
 116         port2-mode = "ehci-phy";
 117 };
 118
 119 &usbhsehci {
 120         phys = <0 &hsusb2_phy>;
 121 };
 122
 123
 124 &omap3_pmx_core {
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&hsusb2_pins>;
 127
 128         mmc3_pins: pinmux_mm3_pins {
 129                 pinctrl-single,pins = <
 130                         OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
 131                         OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
 132                         OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
 133                         OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
 134                         OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
 135                         OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */
 136                 >;
 137         };
 138         mcbsp2_pins: pinmux_mcbsp2_pins {
 139                 pinctrl-single,pins = <
 140                         OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
 141                         OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx */
 142                         OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr */
 143                         OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx */
 144                 >;
 145         };
 146         uart2_pins: pinmux_uart2_pins {
 147                 pinctrl-single,pins = <
 148                         OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)        /* uart2_cts.uart2_cts */
 149                         OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)       /* uart2_rts .uart2_rts*/
 150                         OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)       /* uart2_tx.uart2_tx */
 151                         OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)        /* uart2_rx.uart2_rx */
 152                         OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)       /* GPIO_162,BT_EN */
 153                 >;
 154         };
 155         mcspi1_pins: pinmux_mcspi1_pins {
 156                 pinctrl-single,pins = <
 157                         OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
 158                         OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
 159                         OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
 160                         OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
 161                 >;
 162         };
 163
 164         hsusb2_pins: pinmux_hsusb2_pins {
 165                 pinctrl-single,pins = <
 166                         OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
 167                         OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
 168                         OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
 169                         OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
 170                         OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
 171                         OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
 172                 >;
 173         };
 174
 175         hsusb_otg_pins: pinmux_hsusb_otg_pins {
 176                 pinctrl-single,pins = <
 177                         OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)        /* hsusb0_clk.hsusb0_clk */
 178                         OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)       /* hsusb0_stp.hsusb0_stp */
 179                         OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)        /* hsusb0_dir.hsusb0_dir */
 180                         OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)        /* hsusb0_nxt.hsusb0_nxt */
 181                         OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)        /* hsusb0_data0.hsusb0_data0 */
 182                         OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)        /* hsusb0_data1.hsusb0_data1 */
 183                         OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)        /* hsusb0_data2.hsusb0_data2 */
 184                         OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)        /* hsusb0_data3.hsusb0_data3 */
 185                         OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)        /* hsusb0_data4.hsusb0_data4 */
 186                         OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)        /* hsusb0_data5.hsusb0_data5 */
 187                         OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)        /* hsusb0_data6.hsusb0_data6 */
 188                         OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)        /* hsusb0_data7.hsusb0_data7 */
 189                 >;
 190         };
 191
 192
 193 };
 194
 195 &omap3_pmx_wkup {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&hsusb2_reset_pin>;
 198         hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
 199                 pinctrl-single,pins = <
 200                         OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4)        /* sys_boot2.gpio_4 */
 201                 >;
 202         };
 203         wl127x_gpio: pinmux_wl127x_gpio_pin {
 204                 pinctrl-single,pins = <
 205                         OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4)         /* sys_boot0.gpio_2 */
 206                         OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)        /* sys_boot1.gpio_3 */
 207                 >;
 208         };
 209 };
 210
 211 &omap3_pmx_core2 {
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&hsusb2_2_pins>;
 214         hsusb2_2_pins: pinmux_hsusb2_2_pins {
 215                 pinctrl-single,pins = <
 216                         OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
 217                         OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
 218                         OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
 219                         OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
 220                         OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
 221                         OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
 222                 >;
 223         };
 224 };
 225
 226 &uart2 {
 227         interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&uart2_pins>;
 230 };
 231
 232 &mcspi1 {
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&mcspi1_pins>;
 235 };
 236
 237 #include "twl4030.dtsi"
 238 #include "twl4030_omap3.dtsi"
 239
 240 &twl {
 241         twl_power: power {
 242                 compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
 243                 ti,use_poweroff;
 244         };
 245 };
 246
 247 &twl_gpio {
 248         ti,use-leds;
 249 };