| blob | c31dad98f989d26a7f3ae1252fce5bfce62432aa |
1 /*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
48 #include "skeleton64.dtsi"
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/thermal/thermal.h>
52 / {
53 compatible = "fsl,ls1021a";
54 interrupt-parent = <&gic>;
56 aliases {
57 crypto = &crypto;
58 ethernet0 = &enet0;
59 ethernet1 = &enet1;
60 ethernet2 = &enet2;
61 serial0 = &lpuart0;
62 serial1 = &lpuart1;
63 serial2 = &lpuart2;
64 serial3 = &lpuart3;
65 serial4 = &lpuart4;
66 serial5 = &lpuart5;
67 sysclk = &sysclk;
68 };
70 cpus {
71 #address-cells = <1>;
72 #size-cells = <0>;
74 cpu0: cpu@f00 {
75 compatible = "arm,cortex-a7";
76 device_type = "cpu";
77 reg = <0xf00>;
78 clocks = <&clockgen 1 0>;
79 #cooling-cells = <2>;
80 };
82 cpu1: cpu@f01 {
83 compatible = "arm,cortex-a7";
84 device_type = "cpu";
85 reg = <0xf01>;
86 clocks = <&clockgen 1 0>;
87 };
88 };
90 sysclk: sysclk {
91 compatible = "fixed-clock";
92 #clock-cells = <0>;
93 clock-frequency = <100000000>;
94 clock-output-names = "sysclk";
95 };
97 timer {
98 compatible = "arm,armv7-timer";
99 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
103 };
105 pmu {
106 compatible = "arm,cortex-a7-pmu";
107 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-affinity = <&cpu0>, <&cpu1>;
110 };
112 reboot {
113 compatible = "syscon-reboot";
114 regmap = <&dcfg>;
115 offset = <0xb0>;
116 mask = <0x02>;
117 };
119 soc {
120 compatible = "simple-bus";
121 #address-cells = <2>;
122 #size-cells = <2>;
123 device_type = "soc";
124 interrupt-parent = <&gic>;
125 ranges;
127 gic: interrupt-controller@1400000 {
128 compatible = "arm,gic-400", "arm,cortex-a7-gic";
129 #interrupt-cells = <3>;
130 interrupt-controller;
131 reg = <0x0 0x1401000 0x0 0x1000>,
132 <0x0 0x1402000 0x0 0x2000>,
133 <0x0 0x1404000 0x0 0x2000>,
134 <0x0 0x1406000 0x0 0x2000>;
135 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
137 };
139 msi1: msi-controller@1570e00 {
140 compatible = "fsl,ls1021a-msi";
141 reg = <0x0 0x1570e00 0x0 0x8>;
142 msi-controller;
143 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
144 };
146 msi2: msi-controller@1570e08 {
147 compatible = "fsl,ls1021a-msi";
148 reg = <0x0 0x1570e08 0x0 0x8>;
149 msi-controller;
150 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
151 };
153 ifc: ifc@1530000 {
154 compatible = "fsl,ifc", "simple-bus";
155 reg = <0x0 0x1530000 0x0 0x10000>;
156 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
157 };
159 dcfg: dcfg@1ee0000 {
160 compatible = "fsl,ls1021a-dcfg", "syscon";
161 reg = <0x0 0x1ee0000 0x0 0x10000>;
162 big-endian;
163 };
165 qspi: quadspi@1550000 {
166 compatible = "fsl,ls1021a-qspi";
167 #address-cells = <1>;
168 #size-cells = <0>;
169 reg = <0x0 0x1550000 0x0 0x10000>,
170 <0x0 0x40000000 0x0 0x40000000>;
171 reg-names = "QuadSPI", "QuadSPI-memory";
172 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
173 clock-names = "qspi_en", "qspi";
174 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
175 big-endian;
176 status = "disabled";
177 };
179 esdhc: esdhc@1560000 {
180 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
181 reg = <0x0 0x1560000 0x0 0x10000>;
182 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
183 clock-frequency = <0>;
184 voltage-ranges = <1800 1800 3300 3300>;
185 sdhci,auto-cmd12;
186 big-endian;
187 bus-width = <4>;
188 status = "disabled";
189 };
191 sata: sata@3200000 {
192 compatible = "fsl,ls1021a-ahci";
193 reg = <0x0 0x3200000 0x0 0x10000>,
194 <0x0 0x20220520 0x0 0x4>;
195 reg-names = "ahci", "sata-ecc";
196 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clockgen 4 1>;
198 dma-coherent;
199 status = "disabled";
200 };
202 scfg: scfg@1570000 {
203 compatible = "fsl,ls1021a-scfg", "syscon";
204 reg = <0x0 0x1570000 0x0 0x10000>;
205 big-endian;
206 };
208 crypto: crypto@1700000 {
209 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
210 fsl,sec-era = <7>;
211 #address-cells = <1>;
212 #size-cells = <1>;
213 reg = <0x0 0x1700000 0x0 0x100000>;
214 ranges = <0x0 0x0 0x1700000 0x100000>;
215 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
217 sec_jr0: jr@10000 {
218 compatible = "fsl,sec-v5.0-job-ring",
219 "fsl,sec-v4.0-job-ring";
220 reg = <0x10000 0x10000>;
221 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
222 };
224 sec_jr1: jr@20000 {
225 compatible = "fsl,sec-v5.0-job-ring",
226 "fsl,sec-v4.0-job-ring";
227 reg = <0x20000 0x10000>;
228 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
229 };
231 sec_jr2: jr@30000 {
232 compatible = "fsl,sec-v5.0-job-ring",
233 "fsl,sec-v4.0-job-ring";
234 reg = <0x30000 0x10000>;
235 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
236 };
238 sec_jr3: jr@40000 {
239 compatible = "fsl,sec-v5.0-job-ring",
240 "fsl,sec-v4.0-job-ring";
241 reg = <0x40000 0x10000>;
242 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
243 };
245 };
247 clockgen: clocking@1ee1000 {
248 compatible = "fsl,ls1021a-clockgen";
249 reg = <0x0 0x1ee1000 0x0 0x1000>;
250 #clock-cells = <2>;
251 clocks = <&sysclk>;
252 };
254 tmu: tmu@1f00000 {
255 compatible = "fsl,qoriq-tmu";
256 reg = <0x0 0x1f00000 0x0 0x10000>;
257 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
258 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
259 fsl,tmu-calibration = <0x00000000 0x0000000f
260 0x00000001 0x00000017
261 0x00000002 0x0000001e
262 0x00000003 0x00000026
263 0x00000004 0x0000002e
264 0x00000005 0x00000035
265 0x00000006 0x0000003d
266 0x00000007 0x00000044
267 0x00000008 0x0000004c
268 0x00000009 0x00000053
269 0x0000000a 0x0000005b
270 0x0000000b 0x00000064
272 0x00010000 0x00000011
273 0x00010001 0x0000001c
274 0x00010002 0x00000024
275 0x00010003 0x0000002b
276 0x00010004 0x00000034
277 0x00010005 0x00000039
278 0x00010006 0x00000042
279 0x00010007 0x0000004c
280 0x00010008 0x00000051
281 0x00010009 0x0000005a
282 0x0001000a 0x00000063
284 0x00020000 0x00000013
285 0x00020001 0x00000019
286 0x00020002 0x00000024
287 0x00020003 0x0000002c
288 0x00020004 0x00000035
289 0x00020005 0x0000003d
290 0x00020006 0x00000046
291 0x00020007 0x00000050
292 0x00020008 0x00000059
294 0x00030000 0x00000002
295 0x00030001 0x0000000d
296 0x00030002 0x00000019
297 0x00030003 0x00000024>;
298 #thermal-sensor-cells = <1>;
299 };
301 thermal-zones {
302 cpu_thermal: cpu-thermal {
303 polling-delay-passive = <1000>;
304 polling-delay = <5000>;
306 thermal-sensors = <&tmu 0>;
308 trips {
309 cpu_alert: cpu-alert {
310 temperature = <85000>;
311 hysteresis = <2000>;
312 type = "passive";
313 };
314 cpu_crit: cpu-crit {
315 temperature = <95000>;
316 hysteresis = <2000>;
317 type = "critical";
318 };
319 };
321 cooling-maps {
322 map0 {
323 trip = <&cpu_alert>;
324 cooling-device =
325 <&cpu0 THERMAL_NO_LIMIT
326 THERMAL_NO_LIMIT>;
327 };
328 };
329 };
330 };
332 dspi0: dspi@2100000 {
333 compatible = "fsl,ls1021a-v1.0-dspi";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 reg = <0x0 0x2100000 0x0 0x10000>;
337 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
338 clock-names = "dspi";
339 clocks = <&clockgen 4 1>;
340 spi-num-chipselects = <6>;
341 big-endian;
342 status = "disabled";
343 };
345 dspi1: dspi@2110000 {
346 compatible = "fsl,ls1021a-v1.0-dspi";
347 #address-cells = <1>;
348 #size-cells = <0>;
349 reg = <0x0 0x2110000 0x0 0x10000>;
350 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
351 clock-names = "dspi";
352 clocks = <&clockgen 4 1>;
353 spi-num-chipselects = <6>;
354 big-endian;
355 status = "disabled";
356 };
358 i2c0: i2c@2180000 {
359 compatible = "fsl,vf610-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 reg = <0x0 0x2180000 0x0 0x10000>;
363 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
364 clock-names = "i2c";
365 clocks = <&clockgen 4 1>;
366 status = "disabled";
367 };
369 i2c1: i2c@2190000 {
370 compatible = "fsl,vf610-i2c";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 reg = <0x0 0x2190000 0x0 0x10000>;
374 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
375 clock-names = "i2c";
376 clocks = <&clockgen 4 1>;
377 status = "disabled";
378 };
380 i2c2: i2c@21a0000 {
381 compatible = "fsl,vf610-i2c";
382 #address-cells = <1>;
383 #size-cells = <0>;
384 reg = <0x0 0x21a0000 0x0 0x10000>;
385 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
386 clock-names = "i2c";
387 clocks = <&clockgen 4 1>;
388 status = "disabled";
389 };
391 uart0: serial@21c0500 {
392 compatible = "fsl,16550-FIFO64", "ns16550a";
393 reg = <0x0 0x21c0500 0x0 0x100>;
394 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
395 clock-frequency = <0>;
396 fifo-size = <15>;
397 status = "disabled";
398 };
400 uart1: serial@21c0600 {
401 compatible = "fsl,16550-FIFO64", "ns16550a";
402 reg = <0x0 0x21c0600 0x0 0x100>;
403 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
404 clock-frequency = <0>;
405 fifo-size = <15>;
406 status = "disabled";
407 };
409 uart2: serial@21d0500 {
410 compatible = "fsl,16550-FIFO64", "ns16550a";
411 reg = <0x0 0x21d0500 0x0 0x100>;
412 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
413 clock-frequency = <0>;
414 fifo-size = <15>;
415 status = "disabled";
416 };
418 uart3: serial@21d0600 {
419 compatible = "fsl,16550-FIFO64", "ns16550a";
420 reg = <0x0 0x21d0600 0x0 0x100>;
421 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
422 clock-frequency = <0>;
423 fifo-size = <15>;
424 status = "disabled";
425 };
427 gpio0: gpio@2300000 {
428 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
429 reg = <0x0 0x2300000 0x0 0x10000>;
430 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
431 gpio-controller;
432 #gpio-cells = <2>;
433 interrupt-controller;
434 #interrupt-cells = <2>;
435 };
437 gpio1: gpio@2310000 {
438 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
439 reg = <0x0 0x2310000 0x0 0x10000>;
440 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
441 gpio-controller;
442 #gpio-cells = <2>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
445 };
447 gpio2: gpio@2320000 {
448 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
449 reg = <0x0 0x2320000 0x0 0x10000>;
450 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
451 gpio-controller;
452 #gpio-cells = <2>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
455 };
457 gpio3: gpio@2330000 {
458 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
459 reg = <0x0 0x2330000 0x0 0x10000>;
460 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
461 gpio-controller;
462 #gpio-cells = <2>;
463 interrupt-controller;
464 #interrupt-cells = <2>;
465 };
467 lpuart0: serial@2950000 {
468 compatible = "fsl,ls1021a-lpuart";
469 reg = <0x0 0x2950000 0x0 0x1000>;
470 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&sysclk>;
472 clock-names = "ipg";
473 status = "disabled";
474 };
476 lpuart1: serial@2960000 {
477 compatible = "fsl,ls1021a-lpuart";
478 reg = <0x0 0x2960000 0x0 0x1000>;
479 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&clockgen 4 1>;
481 clock-names = "ipg";
482 status = "disabled";
483 };
485 lpuart2: serial@2970000 {
486 compatible = "fsl,ls1021a-lpuart";
487 reg = <0x0 0x2970000 0x0 0x1000>;
488 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&clockgen 4 1>;
490 clock-names = "ipg";
491 status = "disabled";
492 };
494 lpuart3: serial@2980000 {
495 compatible = "fsl,ls1021a-lpuart";
496 reg = <0x0 0x2980000 0x0 0x1000>;
497 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&clockgen 4 1>;
499 clock-names = "ipg";
500 status = "disabled";
501 };
503 lpuart4: serial@2990000 {
504 compatible = "fsl,ls1021a-lpuart";
505 reg = <0x0 0x2990000 0x0 0x1000>;
506 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&clockgen 4 1>;
508 clock-names = "ipg";
509 status = "disabled";
510 };
512 lpuart5: serial@29a0000 {
513 compatible = "fsl,ls1021a-lpuart";
514 reg = <0x0 0x29a0000 0x0 0x1000>;
515 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clockgen 4 1>;
517 clock-names = "ipg";
518 status = "disabled";
519 };
521 wdog0: watchdog@2ad0000 {
522 compatible = "fsl,imx21-wdt";
523 reg = <0x0 0x2ad0000 0x0 0x10000>;
524 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clockgen 4 1>;
526 clock-names = "wdog-en";
527 big-endian;
528 };
530 sai1: sai@2b50000 {
531 #sound-dai-cells = <0>;
532 compatible = "fsl,vf610-sai";
533 reg = <0x0 0x2b50000 0x0 0x10000>;
534 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
536 <&clockgen 4 1>, <&clockgen 4 1>;
537 clock-names = "bus", "mclk1", "mclk2", "mclk3";
538 dma-names = "tx", "rx";
539 dmas = <&edma0 1 47>,
540 <&edma0 1 46>;
541 status = "disabled";
542 };
544 sai2: sai@2b60000 {
545 #sound-dai-cells = <0>;
546 compatible = "fsl,vf610-sai";
547 reg = <0x0 0x2b60000 0x0 0x10000>;
548 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
550 <&clockgen 4 1>, <&clockgen 4 1>;
551 clock-names = "bus", "mclk1", "mclk2", "mclk3";
552 dma-names = "tx", "rx";
553 dmas = <&edma0 1 45>,
554 <&edma0 1 44>;
555 status = "disabled";
556 };
558 edma0: edma@2c00000 {
559 #dma-cells = <2>;
560 compatible = "fsl,vf610-edma";
561 reg = <0x0 0x2c00000 0x0 0x10000>,
562 <0x0 0x2c10000 0x0 0x10000>,
563 <0x0 0x2c20000 0x0 0x10000>;
564 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
566 interrupt-names = "edma-tx", "edma-err";
567 dma-channels = <32>;
568 big-endian;
569 clock-names = "dmamux0", "dmamux1";
570 clocks = <&clockgen 4 1>,
571 <&clockgen 4 1>;
572 };
574 dcu: dcu@2ce0000 {
575 compatible = "fsl,ls1021a-dcu";
576 reg = <0x0 0x2ce0000 0x0 0x10000>;
577 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clockgen 4 0>,
579 <&clockgen 4 0>;
580 clock-names = "dcu", "pix";
581 big-endian;
582 status = "disabled";
583 };
585 mdio0: mdio@2d24000 {
586 compatible = "gianfar";
587 device_type = "mdio";
588 #address-cells = <1>;
589 #size-cells = <0>;
590 reg = <0x0 0x2d24000 0x0 0x4000>;
591 };
593 ptp_clock@2d10e00 {
594 compatible = "fsl,etsec-ptp";
595 reg = <0x0 0x2d10e00 0x0 0xb0>;
596 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
597 fsl,tclk-period = <5>;
598 fsl,tmr-prsc = <2>;
599 fsl,tmr-add = <0xaaaaaaab>;
600 fsl,tmr-fiper1 = <999999995>;
601 fsl,tmr-fiper2 = <99990>;
602 fsl,max-adj = <499999999>;
603 };
605 enet0: ethernet@2d10000 {
606 compatible = "fsl,etsec2";
607 device_type = "network";
608 #address-cells = <2>;
609 #size-cells = <2>;
610 interrupt-parent = <&gic>;
611 model = "eTSEC";
612 fsl,magic-packet;
613 ranges;
614 dma-coherent;
616 queue-group@2d10000 {
617 #address-cells = <2>;
618 #size-cells = <2>;
619 reg = <0x0 0x2d10000 0x0 0x1000>;
620 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
623 };
625 queue-group@2d14000 {
626 #address-cells = <2>;
627 #size-cells = <2>;
628 reg = <0x0 0x2d14000 0x0 0x1000>;
629 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
632 };
633 };
635 enet1: ethernet@2d50000 {
636 compatible = "fsl,etsec2";
637 device_type = "network";
638 #address-cells = <2>;
639 #size-cells = <2>;
640 interrupt-parent = <&gic>;
641 model = "eTSEC";
642 ranges;
643 dma-coherent;
645 queue-group@2d50000 {
646 #address-cells = <2>;
647 #size-cells = <2>;
648 reg = <0x0 0x2d50000 0x0 0x1000>;
649 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
652 };
654 queue-group@2d54000 {
655 #address-cells = <2>;
656 #size-cells = <2>;
657 reg = <0x0 0x2d54000 0x0 0x1000>;
658 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
661 };
662 };
664 enet2: ethernet@2d90000 {
665 compatible = "fsl,etsec2";
666 device_type = "network";
667 #address-cells = <2>;
668 #size-cells = <2>;
669 interrupt-parent = <&gic>;
670 model = "eTSEC";
671 ranges;
672 dma-coherent;
674 queue-group@2d90000 {
675 #address-cells = <2>;
676 #size-cells = <2>;
677 reg = <0x0 0x2d90000 0x0 0x1000>;
678 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
681 };
683 queue-group@2d94000 {
684 #address-cells = <2>;
685 #size-cells = <2>;
686 reg = <0x0 0x2d94000 0x0 0x1000>;
687 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
690 };
691 };
693 usb2: usb@8600000 {
694 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
695 reg = <0x0 0x8600000 0x0 0x1000>;
696 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
697 dr_mode = "host";
698 phy_type = "ulpi";
699 };
701 usb3: usb3@3100000 {
702 compatible = "snps,dwc3";
703 reg = <0x0 0x3100000 0x0 0x10000>;
704 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
705 dr_mode = "host";
706 snps,quirk-frame-length-adjustment = <0x20>;
707 snps,dis_rxdet_inp3_quirk;
708 };
710 pcie@3400000 {
711 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
712 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
713 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
714 reg-names = "regs", "config";
715 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
716 fsl,pcie-scfg = <&scfg 0>;
717 #address-cells = <3>;
718 #size-cells = <2>;
719 device_type = "pci";
720 num-lanes = <4>;
721 bus-range = <0x0 0xff>;
722 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
723 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
724 msi-parent = <&msi1>, <&msi2>;
725 #interrupt-cells = <1>;
726 interrupt-map-mask = <0 0 0 7>;
727 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
728 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
729 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
730 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
731 };
733 pcie@3500000 {
734 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
735 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
736 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
737 reg-names = "regs", "config";
738 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
739 fsl,pcie-scfg = <&scfg 1>;
740 #address-cells = <3>;
741 #size-cells = <2>;
742 device_type = "pci";
743 num-lanes = <4>;
744 bus-range = <0x0 0xff>;
745 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
746 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
747 msi-parent = <&msi1>, <&msi2>;
748 #interrupt-cells = <1>;
749 interrupt-map-mask = <0 0 0 7>;
750 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
751 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
752 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
753 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
754 };
756 can0: can@2a70000 {
757 compatible = "fsl,ls1021ar2-flexcan";
758 reg = <0x0 0x2a70000 0x0 0x1000>;
759 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
761 clock-names = "ipg", "per";
762 big-endian;
763 };
765 can1: can@2a80000 {
766 compatible = "fsl,ls1021ar2-flexcan";
767 reg = <0x0 0x2a80000 0x0 0x1000>;
768 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
770 clock-names = "ipg", "per";
771 big-endian;
772 };
774 can2: can@2a90000 {
775 compatible = "fsl,ls1021ar2-flexcan";
776 reg = <0x0 0x2a90000 0x0 0x1000>;
777 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
779 clock-names = "ipg", "per";
780 big-endian;
781 };
783 can3: can@2aa0000 {
784 compatible = "fsl,ls1021ar2-flexcan";
785 reg = <0x0 0x2aa0000 0x0 0x1000>;
786 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
788 clock-names = "ipg", "per";
789 big-endian;
790 };
791 };
792 };