| blob | bd0cd3204273d3fc4434ce2ac7ac2cf92deb4ef4 |
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
45 #include "skeleton.dtsi"
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/clock/sun4i-a10-ccu.h>
51 #include <dt-bindings/reset/sun4i-a10-ccu.h>
53 / {
54 interrupt-parent = <&gic>;
56 aliases {
57 ethernet0 = &gmac;
58 };
60 chosen {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
65 framebuffer@0 {
66 compatible = "allwinner,simple-framebuffer",
67 "simple-framebuffer";
68 allwinner,pipeline = "de_be0-lcd0-hdmi";
69 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
70 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
71 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
72 <&ccu CLK_HDMI>;
73 status = "disabled";
74 };
76 framebuffer@1 {
77 compatible = "allwinner,simple-framebuffer",
78 "simple-framebuffer";
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
81 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
82 <&ccu CLK_DRAM_DE_BE0>;
83 status = "disabled";
84 };
86 framebuffer@2 {
87 compatible = "allwinner,simple-framebuffer",
88 "simple-framebuffer";
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
91 <&ccu CLK_AHB_DE_BE0>,
92 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
93 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
94 status = "disabled";
95 };
96 };
98 cpus {
99 #address-cells = <1>;
100 #size-cells = <0>;
102 cpu0: cpu@0 {
103 compatible = "arm,cortex-a7";
104 device_type = "cpu";
105 reg = <0>;
106 clocks = <&ccu CLK_CPU>;
107 clock-latency = <244144>; /* 8 32k periods */
108 operating-points = <
109 /* kHz uV */
110 960000 1400000
111 912000 1400000
112 864000 1300000
113 720000 1200000
114 528000 1100000
115 312000 1000000
116 144000 1000000
117 >;
118 #cooling-cells = <2>;
119 cooling-min-level = <0>;
120 cooling-max-level = <6>;
121 };
123 cpu@1 {
124 compatible = "arm,cortex-a7";
125 device_type = "cpu";
126 reg = <1>;
127 };
128 };
130 thermal-zones {
131 cpu_thermal {
132 /* milliseconds */
133 polling-delay-passive = <250>;
134 polling-delay = <1000>;
135 thermal-sensors = <&rtp>;
137 cooling-maps {
138 map0 {
139 trip = <&cpu_alert0>;
140 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
141 };
142 };
144 trips {
145 cpu_alert0: cpu_alert0 {
146 /* milliCelsius */
147 temperature = <75000>;
148 hysteresis = <2000>;
149 type = "passive";
150 };
152 cpu_crit: cpu_crit {
153 /* milliCelsius */
154 temperature = <100000>;
155 hysteresis = <2000>;
156 type = "critical";
157 };
158 };
159 };
160 };
162 memory {
163 reg = <0x40000000 0x80000000>;
164 };
166 timer {
167 compatible = "arm,armv7-timer";
168 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
170 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
171 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
172 };
174 pmu {
175 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
176 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
178 };
180 clocks {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges;
185 osc24M: clk@1c20050 {
186 #clock-cells = <0>;
187 compatible = "fixed-clock";
188 clock-frequency = <24000000>;
189 clock-output-names = "osc24M";
190 };
192 osc32k: clk@0 {
193 #clock-cells = <0>;
194 compatible = "fixed-clock";
195 clock-frequency = <32768>;
196 clock-output-names = "osc32k";
197 };
199 /*
200 * The following two are dummy clocks, placeholders
201 * used in the gmac_tx clock. The gmac driver will
202 * choose one parent depending on the PHY interface
203 * mode, using clk_set_rate auto-reparenting.
204 *
205 * The actual TX clock rate is not controlled by the
206 * gmac_tx clock.
207 */
208 mii_phy_tx_clk: clk@1 {
209 #clock-cells = <0>;
210 compatible = "fixed-clock";
211 clock-frequency = <25000000>;
212 clock-output-names = "mii_phy_tx";
213 };
215 gmac_int_tx_clk: clk@2 {
216 #clock-cells = <0>;
217 compatible = "fixed-clock";
218 clock-frequency = <125000000>;
219 clock-output-names = "gmac_int_tx";
220 };
222 gmac_tx_clk: clk@1c20164 {
223 #clock-cells = <0>;
224 compatible = "allwinner,sun7i-a20-gmac-clk";
225 reg = <0x01c20164 0x4>;
226 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
227 clock-output-names = "gmac_tx";
228 };
229 };
232 de: display-engine {
233 compatible = "allwinner,sun7i-a20-display-engine";
234 allwinner,pipelines = <&fe0>, <&fe1>;
235 status = "disabled";
236 };
238 soc@1c00000 {
239 compatible = "simple-bus";
240 #address-cells = <1>;
241 #size-cells = <1>;
242 ranges;
244 sram-controller@1c00000 {
245 compatible = "allwinner,sun4i-a10-sram-controller";
246 reg = <0x01c00000 0x30>;
247 #address-cells = <1>;
248 #size-cells = <1>;
249 ranges;
251 sram_a: sram@0 {
252 compatible = "mmio-sram";
253 reg = <0x00000000 0xc000>;
254 #address-cells = <1>;
255 #size-cells = <1>;
256 ranges = <0 0x00000000 0xc000>;
258 emac_sram: sram-section@8000 {
259 compatible = "allwinner,sun4i-a10-sram-a3-a4";
260 reg = <0x8000 0x4000>;
261 status = "disabled";
262 };
263 };
265 sram_d: sram@10000 {
266 compatible = "mmio-sram";
267 reg = <0x00010000 0x1000>;
268 #address-cells = <1>;
269 #size-cells = <1>;
270 ranges = <0 0x00010000 0x1000>;
272 otg_sram: sram-section@0 {
273 compatible = "allwinner,sun4i-a10-sram-d";
274 reg = <0x0000 0x1000>;
275 status = "disabled";
276 };
277 };
278 };
280 nmi_intc: interrupt-controller@1c00030 {
281 compatible = "allwinner,sun7i-a20-sc-nmi";
282 interrupt-controller;
283 #interrupt-cells = <2>;
284 reg = <0x01c00030 0x0c>;
285 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
286 };
288 dma: dma-controller@1c02000 {
289 compatible = "allwinner,sun4i-a10-dma";
290 reg = <0x01c02000 0x1000>;
291 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&ccu CLK_AHB_DMA>;
293 #dma-cells = <2>;
294 };
296 nfc: nand@1c03000 {
297 compatible = "allwinner,sun4i-a10-nand";
298 reg = <0x01c03000 0x1000>;
299 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
301 clock-names = "ahb", "mod";
302 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
303 dma-names = "rxtx";
304 status = "disabled";
305 #address-cells = <1>;
306 #size-cells = <0>;
307 };
309 spi0: spi@1c05000 {
310 compatible = "allwinner,sun4i-a10-spi";
311 reg = <0x01c05000 0x1000>;
312 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
314 clock-names = "ahb", "mod";
315 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
316 <&dma SUN4I_DMA_DEDICATED 26>;
317 dma-names = "rx", "tx";
318 status = "disabled";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 num-cs = <4>;
322 };
324 spi1: spi@1c06000 {
325 compatible = "allwinner,sun4i-a10-spi";
326 reg = <0x01c06000 0x1000>;
327 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
329 clock-names = "ahb", "mod";
330 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
331 <&dma SUN4I_DMA_DEDICATED 8>;
332 dma-names = "rx", "tx";
333 status = "disabled";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 num-cs = <1>;
337 };
339 emac: ethernet@1c0b000 {
340 compatible = "allwinner,sun4i-a10-emac";
341 reg = <0x01c0b000 0x1000>;
342 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&ccu CLK_AHB_EMAC>;
344 allwinner,sram = <&emac_sram 1>;
345 status = "disabled";
346 };
348 mdio: mdio@1c0b080 {
349 compatible = "allwinner,sun4i-a10-mdio";
350 reg = <0x01c0b080 0x14>;
351 status = "disabled";
352 #address-cells = <1>;
353 #size-cells = <0>;
354 };
356 tcon0: lcd-controller@1c0c000 {
357 compatible = "allwinner,sun7i-a20-tcon";
358 reg = <0x01c0c000 0x1000>;
359 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
360 resets = <&ccu RST_TCON0>;
361 reset-names = "lcd";
362 clocks = <&ccu CLK_AHB_LCD0>,
363 <&ccu CLK_TCON0_CH0>,
364 <&ccu CLK_TCON0_CH1>;
365 clock-names = "ahb",
366 "tcon-ch0",
367 "tcon-ch1";
368 clock-output-names = "tcon0-pixel-clock";
369 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
371 ports {
372 #address-cells = <1>;
373 #size-cells = <0>;
375 tcon0_in: port@0 {
376 #address-cells = <1>;
377 #size-cells = <0>;
378 reg = <0>;
380 tcon0_in_be0: endpoint@0 {
381 reg = <0>;
382 remote-endpoint = <&be0_out_tcon0>;
383 };
385 tcon0_in_be1: endpoint@1 {
386 reg = <1>;
387 remote-endpoint = <&be1_out_tcon0>;
388 };
389 };
391 tcon0_out: port@1 {
392 #address-cells = <1>;
393 #size-cells = <0>;
394 reg = <1>;
396 tcon0_out_hdmi: endpoint@1 {
397 reg = <1>;
398 remote-endpoint = <&hdmi_in_tcon0>;
399 allwinner,tcon-channel = <1>;
400 };
401 };
402 };
403 };
405 tcon1: lcd-controller@1c0d000 {
406 compatible = "allwinner,sun7i-a20-tcon";
407 reg = <0x01c0d000 0x1000>;
408 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
409 resets = <&ccu RST_TCON1>;
410 reset-names = "lcd";
411 clocks = <&ccu CLK_AHB_LCD1>,
412 <&ccu CLK_TCON1_CH0>,
413 <&ccu CLK_TCON1_CH1>;
414 clock-names = "ahb",
415 "tcon-ch0",
416 "tcon-ch1";
417 clock-output-names = "tcon1-pixel-clock";
418 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
420 ports {
421 #address-cells = <1>;
422 #size-cells = <0>;
424 tcon1_in: port@0 {
425 #address-cells = <1>;
426 #size-cells = <0>;
427 reg = <0>;
429 tcon1_in_be0: endpoint@0 {
430 reg = <0>;
431 remote-endpoint = <&be0_out_tcon1>;
432 };
434 tcon1_in_be1: endpoint@1 {
435 reg = <1>;
436 remote-endpoint = <&be1_out_tcon1>;
437 };
438 };
440 tcon1_out: port@1 {
441 #address-cells = <1>;
442 #size-cells = <0>;
443 reg = <1>;
445 tcon1_out_hdmi: endpoint@1 {
446 reg = <1>;
447 remote-endpoint = <&hdmi_in_tcon1>;
448 allwinner,tcon-channel = <1>;
449 };
450 };
451 };
452 };
454 mmc0: mmc@1c0f000 {
455 compatible = "allwinner,sun7i-a20-mmc";
456 reg = <0x01c0f000 0x1000>;
457 clocks = <&ccu CLK_AHB_MMC0>,
458 <&ccu CLK_MMC0>,
459 <&ccu CLK_MMC0_OUTPUT>,
460 <&ccu CLK_MMC0_SAMPLE>;
461 clock-names = "ahb",
462 "mmc",
463 "output",
464 "sample";
465 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
466 status = "disabled";
467 #address-cells = <1>;
468 #size-cells = <0>;
469 };
471 mmc1: mmc@1c10000 {
472 compatible = "allwinner,sun7i-a20-mmc";
473 reg = <0x01c10000 0x1000>;
474 clocks = <&ccu CLK_AHB_MMC1>,
475 <&ccu CLK_MMC1>,
476 <&ccu CLK_MMC1_OUTPUT>,
477 <&ccu CLK_MMC1_SAMPLE>;
478 clock-names = "ahb",
479 "mmc",
480 "output",
481 "sample";
482 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
483 status = "disabled";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 };
488 mmc2: mmc@1c11000 {
489 compatible = "allwinner,sun7i-a20-mmc";
490 reg = <0x01c11000 0x1000>;
491 clocks = <&ccu CLK_AHB_MMC2>,
492 <&ccu CLK_MMC2>,
493 <&ccu CLK_MMC2_OUTPUT>,
494 <&ccu CLK_MMC2_SAMPLE>;
495 clock-names = "ahb",
496 "mmc",
497 "output",
498 "sample";
499 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
500 status = "disabled";
501 #address-cells = <1>;
502 #size-cells = <0>;
503 };
505 mmc3: mmc@1c12000 {
506 compatible = "allwinner,sun7i-a20-mmc";
507 reg = <0x01c12000 0x1000>;
508 clocks = <&ccu CLK_AHB_MMC3>,
509 <&ccu CLK_MMC3>,
510 <&ccu CLK_MMC3_OUTPUT>,
511 <&ccu CLK_MMC3_SAMPLE>;
512 clock-names = "ahb",
513 "mmc",
514 "output",
515 "sample";
516 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
517 status = "disabled";
518 #address-cells = <1>;
519 #size-cells = <0>;
520 };
522 usb_otg: usb@1c13000 {
523 compatible = "allwinner,sun4i-a10-musb";
524 reg = <0x01c13000 0x0400>;
525 clocks = <&ccu CLK_AHB_OTG>;
526 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
527 interrupt-names = "mc";
528 phys = <&usbphy 0>;
529 phy-names = "usb";
530 extcon = <&usbphy 0>;
531 allwinner,sram = <&otg_sram 1>;
532 status = "disabled";
533 };
535 usbphy: phy@1c13400 {
536 #phy-cells = <1>;
537 compatible = "allwinner,sun7i-a20-usb-phy";
538 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
539 reg-names = "phy_ctrl", "pmu1", "pmu2";
540 clocks = <&ccu CLK_USB_PHY>;
541 clock-names = "usb_phy";
542 resets = <&ccu RST_USB_PHY0>,
543 <&ccu RST_USB_PHY1>,
544 <&ccu RST_USB_PHY2>;
545 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
546 status = "disabled";
547 };
549 ehci0: usb@1c14000 {
550 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
551 reg = <0x01c14000 0x100>;
552 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&ccu CLK_AHB_EHCI0>;
554 phys = <&usbphy 1>;
555 phy-names = "usb";
556 status = "disabled";
557 };
559 ohci0: usb@1c14400 {
560 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
561 reg = <0x01c14400 0x100>;
562 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
564 phys = <&usbphy 1>;
565 phy-names = "usb";
566 status = "disabled";
567 };
569 crypto: crypto-engine@1c15000 {
570 compatible = "allwinner,sun7i-a20-crypto",
571 "allwinner,sun4i-a10-crypto";
572 reg = <0x01c15000 0x1000>;
573 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
575 clock-names = "ahb", "mod";
576 };
578 hdmi: hdmi@1c16000 {
579 compatible = "allwinner,sun7i-a20-hdmi",
580 "allwinner,sun5i-a10s-hdmi";
581 reg = <0x01c16000 0x1000>;
582 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
584 <&ccu CLK_PLL_VIDEO0_2X>,
585 <&ccu CLK_PLL_VIDEO1_2X>;
586 clock-names = "ahb", "mod", "pll-0", "pll-1";
587 dmas = <&dma SUN4I_DMA_NORMAL 16>,
588 <&dma SUN4I_DMA_NORMAL 16>,
589 <&dma SUN4I_DMA_DEDICATED 24>;
590 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
591 status = "disabled";
593 ports {
594 #address-cells = <1>;
595 #size-cells = <0>;
597 hdmi_in: port@0 {
598 #address-cells = <1>;
599 #size-cells = <0>;
600 reg = <0>;
602 hdmi_in_tcon0: endpoint@0 {
603 reg = <0>;
604 remote-endpoint = <&tcon0_out_hdmi>;
605 };
607 hdmi_in_tcon1: endpoint@1 {
608 reg = <1>;
609 remote-endpoint = <&tcon1_out_hdmi>;
610 };
611 };
613 hdmi_out: port@1 {
614 #address-cells = <1>;
615 #size-cells = <0>;
616 reg = <1>;
617 };
618 };
619 };
621 spi2: spi@1c17000 {
622 compatible = "allwinner,sun4i-a10-spi";
623 reg = <0x01c17000 0x1000>;
624 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
626 clock-names = "ahb", "mod";
627 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
628 <&dma SUN4I_DMA_DEDICATED 28>;
629 dma-names = "rx", "tx";
630 status = "disabled";
631 #address-cells = <1>;
632 #size-cells = <0>;
633 num-cs = <1>;
634 };
636 ahci: sata@1c18000 {
637 compatible = "allwinner,sun4i-a10-ahci";
638 reg = <0x01c18000 0x1000>;
639 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
641 status = "disabled";
642 };
644 ehci1: usb@1c1c000 {
645 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
646 reg = <0x01c1c000 0x100>;
647 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&ccu CLK_AHB_EHCI1>;
649 phys = <&usbphy 2>;
650 phy-names = "usb";
651 status = "disabled";
652 };
654 ohci1: usb@1c1c400 {
655 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
656 reg = <0x01c1c400 0x100>;
657 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
659 phys = <&usbphy 2>;
660 phy-names = "usb";
661 status = "disabled";
662 };
664 spi3: spi@1c1f000 {
665 compatible = "allwinner,sun4i-a10-spi";
666 reg = <0x01c1f000 0x1000>;
667 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
669 clock-names = "ahb", "mod";
670 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
671 <&dma SUN4I_DMA_DEDICATED 30>;
672 dma-names = "rx", "tx";
673 status = "disabled";
674 #address-cells = <1>;
675 #size-cells = <0>;
676 num-cs = <1>;
677 };
679 ccu: clock@1c20000 {
680 compatible = "allwinner,sun7i-a20-ccu";
681 reg = <0x01c20000 0x400>;
682 clocks = <&osc24M>, <&osc32k>;
683 clock-names = "hosc", "losc";
684 #clock-cells = <1>;
685 #reset-cells = <1>;
686 };
688 pio: pinctrl@1c20800 {
689 compatible = "allwinner,sun7i-a20-pinctrl";
690 reg = <0x01c20800 0x400>;
691 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
693 clock-names = "apb", "hosc", "losc";
694 gpio-controller;
695 interrupt-controller;
696 #interrupt-cells = <3>;
697 #gpio-cells = <3>;
699 can0_pins_a: can0@0 {
700 pins = "PH20", "PH21";
701 function = "can";
702 };
704 clk_out_a_pins_a: clk_out_a@0 {
705 pins = "PI12";
706 function = "clk_out_a";
707 };
709 clk_out_b_pins_a: clk_out_b@0 {
710 pins = "PI13";
711 function = "clk_out_b";
712 };
714 emac_pins_a: emac0@0 {
715 pins = "PA0", "PA1", "PA2",
716 "PA3", "PA4", "PA5", "PA6",
717 "PA7", "PA8", "PA9", "PA10",
718 "PA11", "PA12", "PA13", "PA14",
719 "PA15", "PA16";
720 function = "emac";
721 };
723 gmac_pins_mii_a: gmac_mii@0 {
724 pins = "PA0", "PA1", "PA2",
725 "PA3", "PA4", "PA5", "PA6",
726 "PA7", "PA8", "PA9", "PA10",
727 "PA11", "PA12", "PA13", "PA14",
728 "PA15", "PA16";
729 function = "gmac";
730 };
732 gmac_pins_rgmii_a: gmac_rgmii@0 {
733 pins = "PA0", "PA1", "PA2",
734 "PA3", "PA4", "PA5", "PA6",
735 "PA7", "PA8", "PA10",
736 "PA11", "PA12", "PA13",
737 "PA15", "PA16";
738 function = "gmac";
739 /*
740 * data lines in RGMII mode use DDR mode
741 * and need a higher signal drive strength
742 */
743 drive-strength = <40>;
744 };
746 i2c0_pins_a: i2c0@0 {
747 pins = "PB0", "PB1";
748 function = "i2c0";
749 };
751 i2c1_pins_a: i2c1@0 {
752 pins = "PB18", "PB19";
753 function = "i2c1";
754 };
756 i2c2_pins_a: i2c2@0 {
757 pins = "PB20", "PB21";
758 function = "i2c2";
759 };
761 i2c3_pins_a: i2c3@0 {
762 pins = "PI0", "PI1";
763 function = "i2c3";
764 };
766 ir0_rx_pins_a: ir0@0 {
767 pins = "PB4";
768 function = "ir0";
769 };
771 ir0_tx_pins_a: ir0@1 {
772 pins = "PB3";
773 function = "ir0";
774 };
776 ir1_rx_pins_a: ir1@0 {
777 pins = "PB23";
778 function = "ir1";
779 };
781 ir1_tx_pins_a: ir1@1 {
782 pins = "PB22";
783 function = "ir1";
784 };
786 mmc0_pins_a: mmc0@0 {
787 pins = "PF0", "PF1", "PF2",
788 "PF3", "PF4", "PF5";
789 function = "mmc0";
790 drive-strength = <30>;
791 bias-pull-up;
792 };
794 mmc2_pins_a: mmc2@0 {
795 pins = "PC6", "PC7", "PC8",
796 "PC9", "PC10", "PC11";
797 function = "mmc2";
798 drive-strength = <30>;
799 bias-pull-up;
800 };
802 mmc3_pins_a: mmc3@0 {
803 pins = "PI4", "PI5", "PI6",
804 "PI7", "PI8", "PI9";
805 function = "mmc3";
806 drive-strength = <30>;
807 bias-pull-up;
808 };
810 ps20_pins_a: ps20@0 {
811 pins = "PI20", "PI21";
812 function = "ps2";
813 };
815 ps21_pins_a: ps21@0 {
816 pins = "PH12", "PH13";
817 function = "ps2";
818 };
820 pwm0_pins_a: pwm0@0 {
821 pins = "PB2";
822 function = "pwm";
823 };
825 pwm1_pins_a: pwm1@0 {
826 pins = "PI3";
827 function = "pwm";
828 };
830 spdif_tx_pins_a: spdif@0 {
831 pins = "PB13";
832 function = "spdif";
833 bias-pull-up;
834 };
836 spi0_pins_a: spi0@0 {
837 pins = "PI11", "PI12", "PI13";
838 function = "spi0";
839 };
841 spi0_cs0_pins_a: spi0_cs0@0 {
842 pins = "PI10";
843 function = "spi0";
844 };
846 spi0_cs1_pins_a: spi0_cs1@0 {
847 pins = "PI14";
848 function = "spi0";
849 };
851 spi1_pins_a: spi1@0 {
852 pins = "PI17", "PI18", "PI19";
853 function = "spi1";
854 };
856 spi1_cs0_pins_a: spi1_cs0@0 {
857 pins = "PI16";
858 function = "spi1";
859 };
861 spi2_pins_a: spi2@0 {
862 pins = "PC20", "PC21", "PC22";
863 function = "spi2";
864 };
866 spi2_pins_b: spi2@1 {
867 pins = "PB15", "PB16", "PB17";
868 function = "spi2";
869 };
871 spi2_cs0_pins_a: spi2_cs0@0 {
872 pins = "PC19";
873 function = "spi2";
874 };
876 spi2_cs0_pins_b: spi2_cs0@1 {
877 pins = "PB14";
878 function = "spi2";
879 };
881 uart0_pins_a: uart0@0 {
882 pins = "PB22", "PB23";
883 function = "uart0";
884 };
886 uart2_pins_a: uart2@0 {
887 pins = "PI16", "PI17", "PI18", "PI19";
888 function = "uart2";
889 };
891 uart3_pins_a: uart3@0 {
892 pins = "PG6", "PG7", "PG8", "PG9";
893 function = "uart3";
894 };
896 uart3_pins_b: uart3@1 {
897 pins = "PH0", "PH1";
898 function = "uart3";
899 };
901 uart4_pins_a: uart4@0 {
902 pins = "PG10", "PG11";
903 function = "uart4";
904 };
906 uart4_pins_b: uart4@1 {
907 pins = "PH4", "PH5";
908 function = "uart4";
909 };
911 uart5_pins_a: uart5@0 {
912 pins = "PI10", "PI11";
913 function = "uart5";
914 };
916 uart6_pins_a: uart6@0 {
917 pins = "PI12", "PI13";
918 function = "uart6";
919 };
921 uart7_pins_a: uart7@0 {
922 pins = "PI20", "PI21";
923 function = "uart7";
924 };
925 };
927 timer@1c20c00 {
928 compatible = "allwinner,sun4i-a10-timer";
929 reg = <0x01c20c00 0x90>;
930 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&osc24M>;
937 };
939 wdt: watchdog@1c20c90 {
940 compatible = "allwinner,sun4i-a10-wdt";
941 reg = <0x01c20c90 0x10>;
942 };
944 rtc: rtc@1c20d00 {
945 compatible = "allwinner,sun7i-a20-rtc";
946 reg = <0x01c20d00 0x20>;
947 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
948 };
950 pwm: pwm@1c20e00 {
951 compatible = "allwinner,sun7i-a20-pwm";
952 reg = <0x01c20e00 0xc>;
953 clocks = <&osc24M>;
954 #pwm-cells = <3>;
955 status = "disabled";
956 };
958 spdif: spdif@1c21000 {
959 #sound-dai-cells = <0>;
960 compatible = "allwinner,sun4i-a10-spdif";
961 reg = <0x01c21000 0x400>;
962 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
964 clock-names = "apb", "spdif";
965 dmas = <&dma SUN4I_DMA_NORMAL 2>,
966 <&dma SUN4I_DMA_NORMAL 2>;
967 dma-names = "rx", "tx";
968 status = "disabled";
969 };
971 ir0: ir@1c21800 {
972 compatible = "allwinner,sun4i-a10-ir";
973 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
974 clock-names = "apb", "ir";
975 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
976 reg = <0x01c21800 0x40>;
977 status = "disabled";
978 };
980 ir1: ir@1c21c00 {
981 compatible = "allwinner,sun4i-a10-ir";
982 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
983 clock-names = "apb", "ir";
984 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
985 reg = <0x01c21c00 0x40>;
986 status = "disabled";
987 };
989 i2s1: i2s@1c22000 {
990 #sound-dai-cells = <0>;
991 compatible = "allwinner,sun4i-a10-i2s";
992 reg = <0x01c22000 0x400>;
993 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
995 clock-names = "apb", "mod";
996 dmas = <&dma SUN4I_DMA_NORMAL 4>,
997 <&dma SUN4I_DMA_NORMAL 4>;
998 dma-names = "rx", "tx";
999 status = "disabled";
1000 };
1002 i2s0: i2s@1c22400 {
1003 #sound-dai-cells = <0>;
1004 compatible = "allwinner,sun4i-a10-i2s";
1005 reg = <0x01c22400 0x400>;
1006 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1008 clock-names = "apb", "mod";
1009 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1010 <&dma SUN4I_DMA_NORMAL 3>;
1011 dma-names = "rx", "tx";
1012 status = "disabled";
1013 };
1015 lradc: lradc@1c22800 {
1016 compatible = "allwinner,sun4i-a10-lradc-keys";
1017 reg = <0x01c22800 0x100>;
1018 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1019 status = "disabled";
1020 };
1022 codec: codec@1c22c00 {
1023 #sound-dai-cells = <0>;
1024 compatible = "allwinner,sun7i-a20-codec";
1025 reg = <0x01c22c00 0x40>;
1026 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1028 clock-names = "apb", "codec";
1029 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1030 <&dma SUN4I_DMA_NORMAL 19>;
1031 dma-names = "rx", "tx";
1032 status = "disabled";
1033 };
1035 sid: eeprom@1c23800 {
1036 compatible = "allwinner,sun7i-a20-sid";
1037 reg = <0x01c23800 0x200>;
1038 };
1040 i2s2: i2s@1c24400 {
1041 #sound-dai-cells = <0>;
1042 compatible = "allwinner,sun4i-a10-i2s";
1043 reg = <0x01c24400 0x400>;
1044 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1046 clock-names = "apb", "mod";
1047 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1048 <&dma SUN4I_DMA_NORMAL 6>;
1049 dma-names = "rx", "tx";
1050 status = "disabled";
1051 };
1053 rtp: rtp@1c25000 {
1054 compatible = "allwinner,sun5i-a13-ts";
1055 reg = <0x01c25000 0x100>;
1056 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1057 #thermal-sensor-cells = <0>;
1058 };
1060 uart0: serial@1c28000 {
1061 compatible = "snps,dw-apb-uart";
1062 reg = <0x01c28000 0x400>;
1063 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1064 reg-shift = <2>;
1065 reg-io-width = <4>;
1066 clocks = <&ccu CLK_APB1_UART0>;
1067 status = "disabled";
1068 };
1070 uart1: serial@1c28400 {
1071 compatible = "snps,dw-apb-uart";
1072 reg = <0x01c28400 0x400>;
1073 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1074 reg-shift = <2>;
1075 reg-io-width = <4>;
1076 clocks = <&ccu CLK_APB1_UART1>;
1077 status = "disabled";
1078 };
1080 uart2: serial@1c28800 {
1081 compatible = "snps,dw-apb-uart";
1082 reg = <0x01c28800 0x400>;
1083 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1084 reg-shift = <2>;
1085 reg-io-width = <4>;
1086 clocks = <&ccu CLK_APB1_UART2>;
1087 status = "disabled";
1088 };
1090 uart3: serial@1c28c00 {
1091 compatible = "snps,dw-apb-uart";
1092 reg = <0x01c28c00 0x400>;
1093 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1094 reg-shift = <2>;
1095 reg-io-width = <4>;
1096 clocks = <&ccu CLK_APB1_UART3>;
1097 status = "disabled";
1098 };
1100 uart4: serial@1c29000 {
1101 compatible = "snps,dw-apb-uart";
1102 reg = <0x01c29000 0x400>;
1103 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1104 reg-shift = <2>;
1105 reg-io-width = <4>;
1106 clocks = <&ccu CLK_APB1_UART4>;
1107 status = "disabled";
1108 };
1110 uart5: serial@1c29400 {
1111 compatible = "snps,dw-apb-uart";
1112 reg = <0x01c29400 0x400>;
1113 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1114 reg-shift = <2>;
1115 reg-io-width = <4>;
1116 clocks = <&ccu CLK_APB1_UART5>;
1117 status = "disabled";
1118 };
1120 uart6: serial@1c29800 {
1121 compatible = "snps,dw-apb-uart";
1122 reg = <0x01c29800 0x400>;
1123 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1124 reg-shift = <2>;
1125 reg-io-width = <4>;
1126 clocks = <&ccu CLK_APB1_UART6>;
1127 status = "disabled";
1128 };
1130 uart7: serial@1c29c00 {
1131 compatible = "snps,dw-apb-uart";
1132 reg = <0x01c29c00 0x400>;
1133 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1134 reg-shift = <2>;
1135 reg-io-width = <4>;
1136 clocks = <&ccu CLK_APB1_UART7>;
1137 status = "disabled";
1138 };
1140 ps20: ps2@1c2a000 {
1141 compatible = "allwinner,sun4i-a10-ps2";
1142 reg = <0x01c2a000 0x400>;
1143 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1144 clocks = <&ccu CLK_APB1_PS20>;
1145 status = "disabled";
1146 };
1148 ps21: ps2@1c2a400 {
1149 compatible = "allwinner,sun4i-a10-ps2";
1150 reg = <0x01c2a400 0x400>;
1151 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&ccu CLK_APB1_PS21>;
1153 status = "disabled";
1154 };
1156 i2c0: i2c@1c2ac00 {
1157 compatible = "allwinner,sun7i-a20-i2c",
1158 "allwinner,sun4i-a10-i2c";
1159 reg = <0x01c2ac00 0x400>;
1160 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&ccu CLK_APB1_I2C0>;
1162 status = "disabled";
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1165 };
1167 i2c1: i2c@1c2b000 {
1168 compatible = "allwinner,sun7i-a20-i2c",
1169 "allwinner,sun4i-a10-i2c";
1170 reg = <0x01c2b000 0x400>;
1171 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&ccu CLK_APB1_I2C1>;
1173 status = "disabled";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1176 };
1178 i2c2: i2c@1c2b400 {
1179 compatible = "allwinner,sun7i-a20-i2c",
1180 "allwinner,sun4i-a10-i2c";
1181 reg = <0x01c2b400 0x400>;
1182 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&ccu CLK_APB1_I2C2>;
1184 status = "disabled";
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1187 };
1189 i2c3: i2c@1c2b800 {
1190 compatible = "allwinner,sun7i-a20-i2c",
1191 "allwinner,sun4i-a10-i2c";
1192 reg = <0x01c2b800 0x400>;
1193 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&ccu CLK_APB1_I2C3>;
1195 status = "disabled";
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1198 };
1200 can0: can@1c2bc00 {
1201 compatible = "allwinner,sun7i-a20-can",
1202 "allwinner,sun4i-a10-can";
1203 reg = <0x01c2bc00 0x400>;
1204 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&ccu CLK_APB1_CAN>;
1206 status = "disabled";
1207 };
1209 i2c4: i2c@1c2c000 {
1210 compatible = "allwinner,sun7i-a20-i2c",
1211 "allwinner,sun4i-a10-i2c";
1212 reg = <0x01c2c000 0x400>;
1213 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&ccu CLK_APB1_I2C4>;
1215 status = "disabled";
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1218 };
1220 gmac: ethernet@1c50000 {
1221 compatible = "allwinner,sun7i-a20-gmac";
1222 reg = <0x01c50000 0x10000>;
1223 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1224 interrupt-names = "macirq";
1225 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1226 clock-names = "stmmaceth", "allwinner_gmac_tx";
1227 snps,pbl = <2>;
1228 snps,fixed-burst;
1229 snps,force_sf_dma_mode;
1230 status = "disabled";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1233 };
1235 hstimer@1c60000 {
1236 compatible = "allwinner,sun7i-a20-hstimer";
1237 reg = <0x01c60000 0x1000>;
1238 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1242 clocks = <&ccu CLK_AHB_HSTIMER>;
1243 };
1245 gic: interrupt-controller@1c81000 {
1246 compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1247 reg = <0x01c81000 0x1000>,
1248 <0x01c82000 0x2000>,
1249 <0x01c84000 0x2000>,
1250 <0x01c86000 0x2000>;
1251 interrupt-controller;
1252 #interrupt-cells = <3>;
1253 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1254 };
1256 fe0: display-frontend@1e00000 {
1257 compatible = "allwinner,sun7i-a20-display-frontend";
1258 reg = <0x01e00000 0x20000>;
1259 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1260 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1261 <&ccu CLK_DRAM_DE_FE0>;
1262 clock-names = "ahb", "mod",
1263 "ram";
1264 resets = <&ccu RST_DE_FE0>;
1266 ports {
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1270 fe0_out: port@1 {
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1273 reg = <1>;
1275 fe0_out_be0: endpoint@0 {
1276 reg = <0>;
1277 remote-endpoint = <&be0_in_fe0>;
1278 };
1280 fe0_out_be1: endpoint@1 {
1281 reg = <1>;
1282 remote-endpoint = <&be1_in_fe0>;
1283 };
1284 };
1285 };
1286 };
1288 fe1: display-frontend@1e20000 {
1289 compatible = "allwinner,sun7i-a20-display-frontend";
1290 reg = <0x01e20000 0x20000>;
1291 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1293 <&ccu CLK_DRAM_DE_FE1>;
1294 clock-names = "ahb", "mod",
1295 "ram";
1296 resets = <&ccu RST_DE_FE1>;
1298 ports {
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1302 fe1_out: port@1 {
1303 #address-cells = <1>;
1304 #size-cells = <0>;
1305 reg = <1>;
1307 fe1_out_be0: endpoint@0 {
1308 reg = <0>;
1309 remote-endpoint = <&be0_in_fe1>;
1310 };
1312 fe1_out_be1: endpoint@1 {
1313 reg = <1>;
1314 remote-endpoint = <&be1_in_fe1>;
1315 };
1316 };
1317 };
1318 };
1320 be1: display-backend@1e40000 {
1321 compatible = "allwinner,sun7i-a20-display-backend";
1322 reg = <0x01e40000 0x10000>;
1323 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1324 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1325 <&ccu CLK_DRAM_DE_BE1>;
1326 clock-names = "ahb", "mod",
1327 "ram";
1328 resets = <&ccu RST_DE_BE1>;
1330 ports {
1331 #address-cells = <1>;
1332 #size-cells = <0>;
1334 be1_in: port@0 {
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1337 reg = <0>;
1339 be1_in_fe0: endpoint@0 {
1340 reg = <0>;
1341 remote-endpoint = <&fe0_out_be1>;
1342 };
1344 be1_in_fe1: endpoint@1 {
1345 reg = <1>;
1346 remote-endpoint = <&fe1_out_be1>;
1347 };
1348 };
1350 be1_out: port@1 {
1351 #address-cells = <1>;
1352 #size-cells = <0>;
1353 reg = <1>;
1355 be1_out_tcon0: endpoint@0 {
1356 reg = <0>;
1357 remote-endpoint = <&tcon0_in_be1>;
1358 };
1360 be1_out_tcon1: endpoint@1 {
1361 reg = <1>;
1362 remote-endpoint = <&tcon1_in_be1>;
1363 };
1364 };
1365 };
1366 };
1368 be0: display-backend@1e60000 {
1369 compatible = "allwinner,sun7i-a20-display-backend";
1370 reg = <0x01e60000 0x10000>;
1371 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1372 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1373 <&ccu CLK_DRAM_DE_BE0>;
1374 clock-names = "ahb", "mod",
1375 "ram";
1376 resets = <&ccu RST_DE_BE0>;
1378 ports {
1379 #address-cells = <1>;
1380 #size-cells = <0>;
1382 be0_in: port@0 {
1383 #address-cells = <1>;
1384 #size-cells = <0>;
1385 reg = <0>;
1387 be0_in_fe0: endpoint@0 {
1388 reg = <0>;
1389 remote-endpoint = <&fe0_out_be0>;
1390 };
1392 be0_in_fe1: endpoint@1 {
1393 reg = <1>;
1394 remote-endpoint = <&fe1_out_be0>;
1395 };
1396 };
1398 be0_out: port@1 {
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1401 reg = <1>;
1403 be0_out_tcon0: endpoint@0 {
1404 reg = <0>;
1405 remote-endpoint = <&tcon0_in_be0>;
1406 };
1408 be0_out_tcon1: endpoint@1 {
1409 reg = <1>;
1410 remote-endpoint = <&tcon1_in_be0>;
1411 };
1412 };
1413 };
1414 };
1415 };
1416 };