arch/arm/boot/dts/sun8i-a83t.dtsi

   1 /*
   2  * Copyright 2015 Vishnu Patekar
   3  *
   4  * Vishnu Patekar <vishnupatekar0510@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
  48 #include <dt-bindings/clock/sun8i-de2.h>
  49 #include <dt-bindings/clock/sun8i-r-ccu.h>
  50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
  51 #include <dt-bindings/reset/sun8i-de2.h>
  52 #include <dt-bindings/reset/sun8i-r-ccu.h>
  53
  54 / {
  55         interrupt-parent = <&gic>;
  56         #address-cells = <1>;
  57         #size-cells = <1>;
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 cpu@0 {
  64                         compatible = "arm,cortex-a7";
  65                         device_type = "cpu";
  66                         reg = <0>;
  67                 };
  68
  69                 cpu@1 {
  70                         compatible = "arm,cortex-a7";
  71                         device_type = "cpu";
  72                         reg = <1>;
  73                 };
  74
  75                 cpu@2 {
  76                         compatible = "arm,cortex-a7";
  77                         device_type = "cpu";
  78                         reg = <2>;
  79                 };
  80
  81                 cpu@3 {
  82                         compatible = "arm,cortex-a7";
  83                         device_type = "cpu";
  84                         reg = <3>;
  85                 };
  86
  87                 cpu@100 {
  88                         compatible = "arm,cortex-a7";
  89                         device_type = "cpu";
  90                         reg = <0x100>;
  91                 };
  92
  93                 cpu@101 {
  94                         compatible = "arm,cortex-a7";
  95                         device_type = "cpu";
  96                         reg = <0x101>;
  97                 };
  98
  99                 cpu@102 {
 100                         compatible = "arm,cortex-a7";
 101                         device_type = "cpu";
 102                         reg = <0x102>;
 103                 };
 104
 105                 cpu@103 {
 106                         compatible = "arm,cortex-a7";
 107                         device_type = "cpu";
 108                         reg = <0x103>;
 109                 };
 110         };
 111
 112         timer {
 113                 compatible = "arm,armv7-timer";
 114                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 115                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 116                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 117                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 118         };
 119
 120         clocks {
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 ranges;
 124
 125                 /* TODO: PRCM block has a mux for this. */
 126                 osc24M: osc24M_clk {
 127                         #clock-cells = <0>;
 128                         compatible = "fixed-clock";
 129                         clock-frequency = <24000000>;
 130                         clock-accuracy = <50000>;
 131                         clock-output-names = "osc24M";
 132                 };
 133
 134                 /*
 135                  * This is called "internal OSC" in some places.
 136                  * It is an internal RC-based oscillator.
 137                  * TODO: Its controls are in the PRCM block.
 138                  */
 139                 osc16M: osc16M_clk {
 140                         #clock-cells = <0>;
 141                         compatible = "fixed-clock";
 142                         clock-frequency = <16000000>;
 143                         clock-output-names = "osc16M";
 144                 };
 145
 146                 osc16Md512: osc16Md512_clk {
 147                         #clock-cells = <0>;
 148                         compatible = "fixed-factor-clock";
 149                         clock-div = <512>;
 150                         clock-mult = <1>;
 151                         clocks = <&osc16M>;
 152                         clock-output-names = "osc16M-d512";
 153                 };
 154         };
 155
 156         de: display-engine {
 157                 compatible = "allwinner,sun8i-a83t-display-engine";
 158                 allwinner,pipelines = <&mixer0>;
 159                 status = "disabled";
 160         };
 161
 162         memory {
 163                 reg = <0x40000000 0x80000000>;
 164                 device_type = "memory";
 165         };
 166
 167         soc {
 168                 compatible = "simple-bus";
 169                 #address-cells = <1>;
 170                 #size-cells = <1>;
 171                 ranges;
 172
 173                 display_clocks: clock@1000000 {
 174                         compatible = "allwinner,sun8i-a83t-de2-clk";
 175                         reg = <0x01000000 0x100000>;
 176                         clocks = <&ccu CLK_PLL_DE>,
 177                                  <&ccu CLK_BUS_DE>;
 178                         clock-names = "mod",
 179                                       "bus";
 180                         resets = <&ccu RST_BUS_DE>;
 181                         #clock-cells = <1>;
 182                         #reset-cells = <1>;
 183                 };
 184
 185                 mixer0: mixer@1100000 {
 186                         compatible = "allwinner,sun8i-a83t-de2-mixer-0";
 187                         reg = <0x01100000 0x100000>;
 188                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 189                                  <&display_clocks CLK_MIXER0>;
 190                         clock-names = "bus",
 191                                       "mod";
 192                         resets = <&display_clocks RST_MIXER0>;
 193
 194                         ports {
 195                                 #address-cells = <1>;
 196                                 #size-cells = <0>;
 197
 198                                 mixer0_out: port@1 {
 199                                         #address-cells = <1>;
 200                                         #size-cells = <0>;
 201                                         reg = <1>;
 202
 203                                         mixer0_out_tcon0: endpoint@0 {
 204                                                 reg = <0>;
 205                                                 remote-endpoint = <&tcon0_in_mixer0>;
 206                                         };
 207                                 };
 208                         };
 209                 };
 210
 211                 syscon: syscon@1c00000 {
 212                         compatible = "allwinner,sun8i-a83t-system-controller",
 213                                 "syscon";
 214                         reg = <0x01c00000 0x1000>;
 215                 };
 216
 217                 dma: dma-controller@1c02000 {
 218                         compatible = "allwinner,sun8i-a83t-dma";
 219                         reg = <0x01c02000 0x1000>;
 220                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 221                         clocks = <&ccu CLK_BUS_DMA>;
 222                         resets = <&ccu RST_BUS_DMA>;
 223                         #dma-cells = <1>;
 224                 };
 225
 226                 tcon0: lcd-controller@1c0c000 {
 227                         compatible = "allwinner,sun8i-a83t-tcon-lcd";
 228                         reg = <0x01c0c000 0x1000>;
 229                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 230                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 231                         clock-names = "ahb", "tcon-ch0";
 232                         clock-output-names = "tcon-pixel-clock";
 233                         resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 234                         reset-names = "lcd", "lvds";
 235
 236                         ports {
 237                                 #address-cells = <1>;
 238                                 #size-cells = <0>;
 239
 240                                 tcon0_in: port@0 {
 241                                         #address-cells = <1>;
 242                                         #size-cells = <0>;
 243                                         reg = <0>;
 244
 245                                         tcon0_in_mixer0: endpoint@0 {
 246                                                 reg = <0>;
 247                                                 remote-endpoint = <&mixer0_out_tcon0>;
 248                                         };
 249                                 };
 250
 251                                 tcon0_out: port@1 {
 252                                         #address-cells = <1>;
 253                                         #size-cells = <0>;
 254                                         reg = <1>;
 255                                 };
 256                         };
 257                 };
 258
 259                 mmc0: mmc@1c0f000 {
 260                         compatible = "allwinner,sun8i-a83t-mmc",
 261                                      "allwinner,sun7i-a20-mmc";
 262                         reg = <0x01c0f000 0x1000>;
 263                         clocks = <&ccu CLK_BUS_MMC0>,
 264                                  <&ccu CLK_MMC0>,
 265                                  <&ccu CLK_MMC0_OUTPUT>,
 266                                  <&ccu CLK_MMC0_SAMPLE>;
 267                         clock-names = "ahb",
 268                                       "mmc",
 269                                       "output",
 270                                       "sample";
 271                         resets = <&ccu RST_BUS_MMC0>;
 272                         reset-names = "ahb";
 273                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 274                         status = "disabled";
 275                         #address-cells = <1>;
 276                         #size-cells = <0>;
 277                 };
 278
 279                 mmc1: mmc@1c10000 {
 280                         compatible = "allwinner,sun8i-a83t-mmc",
 281                                      "allwinner,sun7i-a20-mmc";
 282                         reg = <0x01c10000 0x1000>;
 283                         clocks = <&ccu CLK_BUS_MMC1>,
 284                                  <&ccu CLK_MMC1>,
 285                                  <&ccu CLK_MMC1_OUTPUT>,
 286                                  <&ccu CLK_MMC1_SAMPLE>;
 287                         clock-names = "ahb",
 288                                       "mmc",
 289                                       "output",
 290                                       "sample";
 291                         resets = <&ccu RST_BUS_MMC1>;
 292                         reset-names = "ahb";
 293                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 294                         pinctrl-names = "default";
 295                         pinctrl-0 = <&mmc1_pins>;
 296                         status = "disabled";
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299                 };
 300
 301                 mmc2: mmc@1c11000 {
 302                         compatible = "allwinner,sun8i-a83t-emmc";
 303                         reg = <0x01c11000 0x1000>;
 304                         clocks = <&ccu CLK_BUS_MMC2>,
 305                                  <&ccu CLK_MMC2>,
 306                                  <&ccu CLK_MMC2_OUTPUT>,
 307                                  <&ccu CLK_MMC2_SAMPLE>;
 308                         clock-names = "ahb",
 309                                       "mmc",
 310                                       "output",
 311                                       "sample";
 312                         resets = <&ccu RST_BUS_MMC2>;
 313                         reset-names = "ahb";
 314                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 315                         status = "disabled";
 316                         #address-cells = <1>;
 317                         #size-cells = <0>;
 318                 };
 319
 320                 usb_otg: usb@1c19000 {
 321                         compatible = "allwinner,sun8i-a83t-musb",
 322                                      "allwinner,sun8i-a33-musb";
 323                         reg = <0x01c19000 0x0400>;
 324                         clocks = <&ccu CLK_BUS_OTG>;
 325                         resets = <&ccu RST_BUS_OTG>;
 326                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 327                         interrupt-names = "mc";
 328                         phys = <&usbphy 0>;
 329                         phy-names = "usb";
 330                         extcon = <&usbphy 0>;
 331                         status = "disabled";
 332                 };
 333
 334                 usbphy: phy@1c19400 {
 335                         compatible = "allwinner,sun8i-a83t-usb-phy";
 336                         reg = <0x01c19400 0x10>,
 337                               <0x01c1a800 0x14>,
 338                               <0x01c1b800 0x14>;
 339                         reg-names = "phy_ctrl",
 340                                     "pmu1",
 341                                     "pmu2";
 342                         clocks = <&ccu CLK_USB_PHY0>,
 343                                  <&ccu CLK_USB_PHY1>,
 344                                  <&ccu CLK_USB_HSIC>,
 345                                  <&ccu CLK_USB_HSIC_12M>;
 346                         clock-names = "usb0_phy",
 347                                       "usb1_phy",
 348                                       "usb2_phy",
 349                                       "usb2_hsic_12M";
 350                         resets = <&ccu RST_USB_PHY0>,
 351                                  <&ccu RST_USB_PHY1>,
 352                                  <&ccu RST_USB_HSIC>;
 353                         reset-names = "usb0_reset",
 354                                       "usb1_reset",
 355                                       "usb2_reset";
 356                         status = "disabled";
 357                         #phy-cells = <1>;
 358                 };
 359
 360                 ehci0: usb@1c1a000 {
 361                         compatible = "allwinner,sun8i-a83t-ehci",
 362                                      "generic-ehci";
 363                         reg = <0x01c1a000 0x100>;
 364                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 365                         clocks = <&ccu CLK_BUS_EHCI0>;
 366                         resets = <&ccu RST_BUS_EHCI0>;
 367                         phys = <&usbphy 1>;
 368                         phy-names = "usb";
 369                         status = "disabled";
 370                 };
 371
 372                 ohci0: usb@1c1a400 {
 373                         compatible = "allwinner,sun8i-a83t-ohci",
 374                                      "generic-ohci";
 375                         reg = <0x01c1a400 0x100>;
 376                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 377                         clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
 378                         resets = <&ccu RST_BUS_OHCI0>;
 379                         phys = <&usbphy 1>;
 380                         phy-names = "usb";
 381                         status = "disabled";
 382                 };
 383
 384                 ehci1: usb@1c1b000 {
 385                         compatible = "allwinner,sun8i-a83t-ehci",
 386                                      "generic-ehci";
 387                         reg = <0x01c1b000 0x100>;
 388                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 389                         clocks = <&ccu CLK_BUS_EHCI1>;
 390                         resets = <&ccu RST_BUS_EHCI1>;
 391                         phys = <&usbphy 2>;
 392                         phy-names = "usb";
 393                         status = "disabled";
 394                 };
 395
 396                 ccu: clock@1c20000 {
 397                         compatible = "allwinner,sun8i-a83t-ccu";
 398                         reg = <0x01c20000 0x400>;
 399                         clocks = <&osc24M>, <&osc16Md512>;
 400                         clock-names = "hosc", "losc";
 401                         #clock-cells = <1>;
 402                         #reset-cells = <1>;
 403                 };
 404
 405                 pio: pinctrl@1c20800 {
 406                         compatible = "allwinner,sun8i-a83t-pinctrl";
 407                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 408                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 409                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 410                         reg = <0x01c20800 0x400>;
 411                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
 412                         clock-names = "apb", "hosc", "losc";
 413                         gpio-controller;
 414                         interrupt-controller;
 415                         #interrupt-cells = <3>;
 416                         #gpio-cells = <3>;
 417
 418                         emac_rgmii_pins: emac-rgmii-pins {
 419                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 420                                        "PD11", "PD12", "PD13", "PD14", "PD18",
 421                                        "PD19", "PD21", "PD22", "PD23";
 422                                 function = "gmac";
 423                                 /*
 424                                  * data lines in RGMII mode use DDR mode
 425                                  * and need a higher signal drive strength
 426                                  */
 427                                 drive-strength = <40>;
 428                         };
 429
 430                         i2c0_pins: i2c0-pins {
 431                                 pins = "PH0", "PH1";
 432                                 function = "i2c0";
 433                         };
 434
 435                         i2c1_pins: i2c1-pins {
 436                                 pins = "PH2", "PH3";
 437                                 function = "i2c1";
 438                         };
 439
 440                         i2c2_ph_pins: i2c2-ph-pins {
 441                                 pins = "PH4", "PH5";
 442                                 function = "i2c2";
 443                         };
 444
 445                         i2s1_pins: i2s1-pins {
 446                                 /* I2S1 does not have external MCLK pin */
 447                                 pins = "PG10", "PG11", "PG12", "PG13";
 448                                 function = "i2s1";
 449                         };
 450
 451                         lcd_lvds_pins: lcd-lvds-pins {
 452                                 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
 453                                        "PD23", "PD24", "PD25", "PD26", "PD27";
 454                                 function = "lvds0";
 455                         };
 456
 457                         mmc0_pins: mmc0-pins {
 458                                 pins = "PF0", "PF1", "PF2",
 459                                        "PF3", "PF4", "PF5";
 460                                 function = "mmc0";
 461                                 drive-strength = <30>;
 462                                 bias-pull-up;
 463                         };
 464
 465                         mmc1_pins: mmc1-pins {
 466                                 pins = "PG0", "PG1", "PG2",
 467                                        "PG3", "PG4", "PG5";
 468                                 function = "mmc1";
 469                                 drive-strength = <30>;
 470                                 bias-pull-up;
 471                         };
 472
 473                         mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
 474                                 pins = "PC5", "PC6", "PC8", "PC9",
 475                                        "PC10", "PC11", "PC12", "PC13",
 476                                        "PC14", "PC15", "PC16";
 477                                 function = "mmc2";
 478                                 drive-strength = <30>;
 479                                 bias-pull-up;
 480                         };
 481
 482                         pwm_pin: pwm-pin {
 483                                 pins = "PD28";
 484                                 function = "pwm";
 485                         };
 486
 487                         spdif_tx_pin: spdif-tx-pin {
 488                                 pins = "PE18";
 489                                 function = "spdif";
 490                         };
 491
 492                         uart0_pb_pins: uart0-pb-pins {
 493                                 pins = "PB9", "PB10";
 494                                 function = "uart0";
 495                         };
 496
 497                         uart0_pf_pins: uart0-pf-pins {
 498                                 pins = "PF2", "PF4";
 499                                 function = "uart0";
 500                         };
 501
 502                         uart1_pins: uart1-pins {
 503                                 pins = "PG6", "PG7";
 504                                 function = "uart1";
 505                         };
 506
 507                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 508                                 pins = "PG8", "PG9";
 509                                 function = "uart1";
 510                         };
 511                 };
 512
 513                 timer@1c20c00 {
 514                         compatible = "allwinner,sun4i-a10-timer";
 515                         reg = <0x01c20c00 0xa0>;
 516                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 517                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 518                         clocks = <&osc24M>;
 519                 };
 520
 521                 watchdog@1c20ca0 {
 522                         compatible = "allwinner,sun6i-a31-wdt";
 523                         reg = <0x01c20ca0 0x20>;
 524                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&osc24M>;
 526                 };
 527
 528                 spdif: spdif@1c21000 {
 529                         #sound-dai-cells = <0>;
 530                         compatible = "allwinner,sun8i-a83t-spdif",
 531                                      "allwinner,sun8i-h3-spdif";
 532                         reg = <0x01c21000 0x400>;
 533                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 534                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 535                         resets = <&ccu RST_BUS_SPDIF>;
 536                         clock-names = "apb", "spdif";
 537                         dmas = <&dma 2>;
 538                         dma-names = "tx";
 539                         pinctrl-names = "default";
 540                         pinctrl-0 = <&spdif_tx_pin>;
 541                         status = "disabled";
 542                 };
 543
 544                 i2s0: i2s@1c22000 {
 545                         #sound-dai-cells = <0>;
 546                         compatible = "allwinner,sun8i-a83t-i2s";
 547                         reg = <0x01c22000 0x400>;
 548                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 549                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 550                         clock-names = "apb", "mod";
 551                         dmas = <&dma 3>, <&dma 3>;
 552                         resets = <&ccu RST_BUS_I2S0>;
 553                         dma-names = "rx", "tx";
 554                         status = "disabled";
 555                 };
 556
 557                 i2s1: i2s@1c22400 {
 558                         #sound-dai-cells = <0>;
 559                         compatible = "allwinner,sun8i-a83t-i2s";
 560                         reg = <0x01c22400 0x400>;
 561                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 563                         clock-names = "apb", "mod";
 564                         dmas = <&dma 4>, <&dma 4>;
 565                         resets = <&ccu RST_BUS_I2S1>;
 566                         dma-names = "rx", "tx";
 567                         pinctrl-names = "default";
 568                         pinctrl-0 = <&i2s1_pins>;
 569                         status = "disabled";
 570                 };
 571
 572                 i2s2: i2s@1c22800 {
 573                         #sound-dai-cells = <0>;
 574                         compatible = "allwinner,sun8i-a83t-i2s";
 575                         reg = <0x01c22800 0x400>;
 576                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 577                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
 578                         clock-names = "apb", "mod";
 579                         dmas = <&dma 27>;
 580                         resets = <&ccu RST_BUS_I2S2>;
 581                         dma-names = "tx";
 582                         status = "disabled";
 583                 };
 584
 585                 pwm: pwm@1c21400 {
 586                         compatible = "allwinner,sun8i-a83t-pwm",
 587                                      "allwinner,sun8i-h3-pwm";
 588                         reg = <0x01c21400 0x400>;
 589                         clocks = <&osc24M>;
 590                         #pwm-cells = <3>;
 591                         status = "disabled";
 592                 };
 593
 594                 uart0: serial@1c28000 {
 595                         compatible = "snps,dw-apb-uart";
 596                         reg = <0x01c28000 0x400>;
 597                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 598                         reg-shift = <2>;
 599                         reg-io-width = <4>;
 600                         clocks = <&ccu CLK_BUS_UART0>;
 601                         resets = <&ccu RST_BUS_UART0>;
 602                         status = "disabled";
 603                 };
 604
 605                 uart1: serial@1c28400 {
 606                         compatible = "snps,dw-apb-uart";
 607                         reg = <0x01c28400 0x400>;
 608                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 609                         reg-shift = <2>;
 610                         reg-io-width = <4>;
 611                         clocks = <&ccu CLK_BUS_UART1>;
 612                         resets = <&ccu RST_BUS_UART1>;
 613                         status = "disabled";
 614                 };
 615
 616                 i2c0: i2c@1c2ac00 {
 617                         compatible = "allwinner,sun8i-a83t-i2c",
 618                                      "allwinner,sun6i-a31-i2c";
 619                         reg = <0x01c2ac00 0x400>;
 620                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 621                         clocks = <&ccu CLK_BUS_I2C0>;
 622                         resets = <&ccu RST_BUS_I2C0>;
 623                         pinctrl-names = "default";
 624                         pinctrl-0 = <&i2c0_pins>;
 625                         status = "disabled";
 626                         #address-cells = <1>;
 627                         #size-cells = <0>;
 628                 };
 629
 630                 i2c1: i2c@1c2b000 {
 631                         compatible = "allwinner,sun8i-a83t-i2c",
 632                                      "allwinner,sun6i-a31-i2c";
 633                         reg = <0x01c2b000 0x400>;
 634                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 635                         clocks = <&ccu CLK_BUS_I2C1>;
 636                         resets = <&ccu RST_BUS_I2C1>;
 637                         pinctrl-names = "default";
 638                         pinctrl-0 = <&i2c1_pins>;
 639                         status = "disabled";
 640                         #address-cells = <1>;
 641                         #size-cells = <0>;
 642                 };
 643
 644                 i2c2: i2c@1c2b400 {
 645                         compatible = "allwinner,sun8i-a83t-i2c",
 646                                      "allwinner,sun6i-a31-i2c";
 647                         reg = <0x01c2b400 0x400>;
 648                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 649                         clocks = <&ccu CLK_BUS_I2C2>;
 650                         resets = <&ccu RST_BUS_I2C2>;
 651                         status = "disabled";
 652                         #address-cells = <1>;
 653                         #size-cells = <0>;
 654                 };
 655
 656                 emac: ethernet@1c30000 {
 657                         compatible = "allwinner,sun8i-a83t-emac";
 658                         syscon = <&syscon>;
 659                         reg = <0x01c30000 0x104>;
 660                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 661                         interrupt-names = "macirq";
 662                         resets = <&ccu 13>;
 663                         reset-names = "stmmaceth";
 664                         clocks = <&ccu 27>;
 665                         clock-names = "stmmaceth";
 666                         #address-cells = <1>;
 667                         #size-cells = <0>;
 668                         status = "disabled";
 669
 670                         mdio: mdio {
 671                                 compatible = "snps,dwmac-mdio";
 672                                 #address-cells = <1>;
 673                                 #size-cells = <0>;
 674                         };
 675                 };
 676
 677                 gic: interrupt-controller@1c81000 {
 678                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 679                         reg = <0x01c81000 0x1000>,
 680                               <0x01c82000 0x2000>,
 681                               <0x01c84000 0x2000>,
 682                               <0x01c86000 0x2000>;
 683                         interrupt-controller;
 684                         #interrupt-cells = <3>;
 685                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 686                 };
 687
 688                 r_intc: interrupt-controller@1f00c00 {
 689                         compatible = "allwinner,sun8i-a83t-r-intc",
 690                                      "allwinner,sun6i-a31-r-intc";
 691                         interrupt-controller;
 692                         #interrupt-cells = <2>;
 693                         reg = <0x01f00c00 0x400>;
 694                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 695                 };
 696
 697                 r_ccu: clock@1f01400 {
 698                         compatible = "allwinner,sun8i-a83t-r-ccu";
 699                         reg = <0x01f01400 0x400>;
 700                         clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
 701                                  <&ccu 6>;
 702                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 703                         #clock-cells = <1>;
 704                         #reset-cells = <1>;
 705                 };
 706
 707                 r_pio: pinctrl@1f02c00 {
 708                         compatible = "allwinner,sun8i-a83t-r-pinctrl";
 709                         reg = <0x01f02c00 0x400>;
 710                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 711                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
 712                                  <&osc16Md512>;
 713                         clock-names = "apb", "hosc", "losc";
 714                         gpio-controller;
 715                         #gpio-cells = <3>;
 716                         interrupt-controller;
 717                         #interrupt-cells = <3>;
 718
 719                         r_rsb_pins: r-rsb-pins {
 720                                 pins = "PL0", "PL1";
 721                                 function = "s_rsb";
 722                                 drive-strength = <20>;
 723                                 bias-pull-up;
 724                         };
 725                 };
 726
 727                 r_rsb: rsb@1f03400 {
 728                         compatible = "allwinner,sun8i-a83t-rsb",
 729                                      "allwinner,sun8i-a23-rsb";
 730                         reg = <0x01f03400 0x400>;
 731                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 732                         clocks = <&r_ccu CLK_APB0_RSB>;
 733                         clock-frequency = <3000000>;
 734                         resets = <&r_ccu RST_APB0_RSB>;
 735                         pinctrl-names = "default";
 736                         pinctrl-0 = <&r_rsb_pins>;
 737                         status = "disabled";
 738                         #address-cells = <1>;
 739                         #size-cells = <0>;
 740                 };
 741         };
 742 };