arch/arm/boot/dts/tegra124.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra124-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra124-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/reset/tegra124-car.h>
   8 #include <dt-bindings/thermal/tegra124-soctherm.h>
   9
  10 #include "skeleton.dtsi"
  11
  12 / {
  13         compatible = "nvidia,tegra124";
  14         interrupt-parent = <&lic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         pcie@1003000 {
  19                 compatible = "nvidia,tegra124-pcie";
  20                 device_type = "pci";
  21                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  22                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  23                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  24                 reg-names = "pads", "afi", "cs";
  25                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  26                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  27                 interrupt-names = "intr", "msi";
  28
  29                 #interrupt-cells = <1>;
  30                 interrupt-map-mask = <0 0 0 0>;
  31                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  32
  33                 bus-range = <0x00 0xff>;
  34                 #address-cells = <3>;
  35                 #size-cells = <2>;
  36
  37                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  38                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  39                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  40                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  41                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  42
  43                 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
  44                          <&tegra_car TEGRA124_CLK_AFI>,
  45                          <&tegra_car TEGRA124_CLK_PLL_E>,
  46                          <&tegra_car TEGRA124_CLK_CML0>;
  47                 clock-names = "pex", "afi", "pll_e", "cml";
  48                 resets = <&tegra_car 70>,
  49                          <&tegra_car 72>,
  50                          <&tegra_car 74>;
  51                 reset-names = "pex", "afi", "pcie_x";
  52                 status = "disabled";
  53
  54                 pci@1,0 {
  55                         device_type = "pci";
  56                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  57                         reg = <0x000800 0 0 0 0>;
  58                         bus-range = <0x00 0xff>;
  59                         status = "disabled";
  60
  61                         #address-cells = <3>;
  62                         #size-cells = <2>;
  63                         ranges;
  64
  65                         nvidia,num-lanes = <2>;
  66                 };
  67
  68                 pci@2,0 {
  69                         device_type = "pci";
  70                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  71                         reg = <0x001000 0 0 0 0>;
  72                         bus-range = <0x00 0xff>;
  73                         status = "disabled";
  74
  75                         #address-cells = <3>;
  76                         #size-cells = <2>;
  77                         ranges;
  78
  79                         nvidia,num-lanes = <1>;
  80                 };
  81         };
  82
  83         host1x@50000000 {
  84                 compatible = "nvidia,tegra124-host1x", "simple-bus";
  85                 reg = <0x0 0x50000000 0x0 0x00034000>;
  86                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  87                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  88                 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
  89                 resets = <&tegra_car 28>;
  90                 reset-names = "host1x";
  91                 iommus = <&mc TEGRA_SWGROUP_HC>;
  92
  93                 #address-cells = <2>;
  94                 #size-cells = <2>;
  95
  96                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
  97
  98                 dc@54200000 {
  99                         compatible = "nvidia,tegra124-dc";
 100                         reg = <0x0 0x54200000 0x0 0x00040000>;
 101                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 102                         clocks = <&tegra_car TEGRA124_CLK_DISP1>,
 103                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 104                         clock-names = "dc", "parent";
 105                         resets = <&tegra_car 27>;
 106                         reset-names = "dc";
 107
 108                         iommus = <&mc TEGRA_SWGROUP_DC>;
 109
 110                         nvidia,head = <0>;
 111                 };
 112
 113                 dc@54240000 {
 114                         compatible = "nvidia,tegra124-dc";
 115                         reg = <0x0 0x54240000 0x0 0x00040000>;
 116                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 117                         clocks = <&tegra_car TEGRA124_CLK_DISP2>,
 118                                  <&tegra_car TEGRA124_CLK_PLL_P>;
 119                         clock-names = "dc", "parent";
 120                         resets = <&tegra_car 26>;
 121                         reset-names = "dc";
 122
 123                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 124
 125                         nvidia,head = <1>;
 126                 };
 127
 128                 hdmi: hdmi@54280000 {
 129                         compatible = "nvidia,tegra124-hdmi";
 130                         reg = <0x0 0x54280000 0x0 0x00040000>;
 131                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 132                         clocks = <&tegra_car TEGRA124_CLK_HDMI>,
 133                                  <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
 134                         clock-names = "hdmi", "parent";
 135                         resets = <&tegra_car 51>;
 136                         reset-names = "hdmi";
 137                         status = "disabled";
 138                 };
 139
 140                 sor@54540000 {
 141                         compatible = "nvidia,tegra124-sor";
 142                         reg = <0x0 0x54540000 0x0 0x00040000>;
 143                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 144                         clocks = <&tegra_car TEGRA124_CLK_SOR0>,
 145                                  <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
 146                                  <&tegra_car TEGRA124_CLK_PLL_DP>,
 147                                  <&tegra_car TEGRA124_CLK_CLK_M>;
 148                         clock-names = "sor", "parent", "dp", "safe";
 149                         resets = <&tegra_car 182>;
 150                         reset-names = "sor";
 151                         status = "disabled";
 152                 };
 153
 154                 dpaux: dpaux@545c0000 {
 155                         compatible = "nvidia,tegra124-dpaux";
 156                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 157                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
 159                                  <&tegra_car TEGRA124_CLK_PLL_DP>;
 160                         clock-names = "dpaux", "parent";
 161                         resets = <&tegra_car 181>;
 162                         reset-names = "dpaux";
 163                         status = "disabled";
 164                 };
 165         };
 166
 167         gic: interrupt-controller@50041000 {
 168                 compatible = "arm,cortex-a15-gic";
 169                 #interrupt-cells = <3>;
 170                 interrupt-controller;
 171                 reg = <0x0 0x50041000 0x0 0x1000>,
 172                       <0x0 0x50042000 0x0 0x1000>,
 173                       <0x0 0x50044000 0x0 0x2000>,
 174                       <0x0 0x50046000 0x0 0x2000>;
 175                 interrupts = <GIC_PPI 9
 176                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 177                 interrupt-parent = <&gic>;
 178         };
 179
 180         /*
 181          * Please keep the following 0, notation in place as a former mainline
 182          * U-Boot version was looking for that particular notation in order to
 183          * perform required fix-ups on that GPU node.
 184          */
 185         gpu@0,57000000 {
 186                 compatible = "nvidia,gk20a";
 187                 reg = <0x0 0x57000000 0x0 0x01000000>,
 188                       <0x0 0x58000000 0x0 0x01000000>;
 189                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 191                 interrupt-names = "stall", "nonstall";
 192                 clocks = <&tegra_car TEGRA124_CLK_GPU>,
 193                          <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
 194                 clock-names = "gpu", "pwr";
 195                 resets = <&tegra_car 184>;
 196                 reset-names = "gpu";
 197
 198                 iommus = <&mc TEGRA_SWGROUP_GPU>;
 199
 200                 status = "disabled";
 201         };
 202
 203         lic: interrupt-controller@60004000 {
 204                 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
 205                 reg = <0x0 0x60004000 0x0 0x100>,
 206                       <0x0 0x60004100 0x0 0x100>,
 207                       <0x0 0x60004200 0x0 0x100>,
 208                       <0x0 0x60004300 0x0 0x100>,
 209                       <0x0 0x60004400 0x0 0x100>;
 210                 interrupt-controller;
 211                 #interrupt-cells = <3>;
 212                 interrupt-parent = <&gic>;
 213         };
 214
 215         timer@60005000 {
 216                 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 217                 reg = <0x0 0x60005000 0x0 0x400>;
 218                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 222                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 223                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 224                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
 225         };
 226
 227         tegra_car: clock@60006000 {
 228                 compatible = "nvidia,tegra124-car";
 229                 reg = <0x0 0x60006000 0x0 0x1000>;
 230                 #clock-cells = <1>;
 231                 #reset-cells = <1>;
 232                 nvidia,external-memory-controller = <&emc>;
 233         };
 234
 235         flow-controller@60007000 {
 236                 compatible = "nvidia,tegra124-flowctrl";
 237                 reg = <0x0 0x60007000 0x0 0x1000>;
 238         };
 239
 240         actmon@6000c800 {
 241                 compatible = "nvidia,tegra124-actmon";
 242                 reg = <0x0 0x6000c800 0x0 0x400>;
 243                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 244                 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
 245                          <&tegra_car TEGRA124_CLK_EMC>;
 246                 clock-names = "actmon", "emc";
 247                 resets = <&tegra_car 119>;
 248                 reset-names = "actmon";
 249         };
 250
 251         gpio: gpio@6000d000 {
 252                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 253                 reg = <0x0 0x6000d000 0x0 0x1000>;
 254                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 262                 #gpio-cells = <2>;
 263                 gpio-controller;
 264                 #interrupt-cells = <2>;
 265                 interrupt-controller;
 266                 /*
 267                 gpio-ranges = <&pinmux 0 0 251>;
 268                 */
 269         };
 270
 271         apbdma: dma@60020000 {
 272                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
 273                 reg = <0x0 0x60020000 0x0 0x1400>;
 274                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
 307                 resets = <&tegra_car 34>;
 308                 reset-names = "dma";
 309                 #dma-cells = <1>;
 310         };
 311
 312         apbmisc@70000800 {
 313                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
 314                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 315                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
 316         };
 317
 318         pinmux: pinmux@70000868 {
 319                 compatible = "nvidia,tegra124-pinmux";
 320                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
 321                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
 322                       <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
 323         };
 324
 325         /*
 326          * There are two serial driver i.e. 8250 based simple serial
 327          * driver and APB DMA based serial driver for higher baudrate
 328          * and performace. To enable the 8250 based driver, the compatible
 329          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 330          * the APB DMA based serial driver, the compatible is
 331          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 332          */
 333         uarta: serial@70006000 {
 334                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 335                 reg = <0x0 0x70006000 0x0 0x40>;
 336                 reg-shift = <2>;
 337                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 338                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 339                 resets = <&tegra_car 6>;
 340                 reset-names = "serial";
 341                 dmas = <&apbdma 8>, <&apbdma 8>;
 342                 dma-names = "rx", "tx";
 343                 status = "disabled";
 344         };
 345
 346         uartb: serial@70006040 {
 347                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 348                 reg = <0x0 0x70006040 0x0 0x40>;
 349                 reg-shift = <2>;
 350                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 352                 resets = <&tegra_car 7>;
 353                 reset-names = "serial";
 354                 dmas = <&apbdma 9>, <&apbdma 9>;
 355                 dma-names = "rx", "tx";
 356                 status = "disabled";
 357         };
 358
 359         uartc: serial@70006200 {
 360                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 361                 reg = <0x0 0x70006200 0x0 0x40>;
 362                 reg-shift = <2>;
 363                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 364                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 365                 resets = <&tegra_car 55>;
 366                 reset-names = "serial";
 367                 dmas = <&apbdma 10>, <&apbdma 10>;
 368                 dma-names = "rx", "tx";
 369                 status = "disabled";
 370         };
 371
 372         uartd: serial@70006300 {
 373                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 374                 reg = <0x0 0x70006300 0x0 0x40>;
 375                 reg-shift = <2>;
 376                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 378                 resets = <&tegra_car 65>;
 379                 reset-names = "serial";
 380                 dmas = <&apbdma 19>, <&apbdma 19>;
 381                 dma-names = "rx", "tx";
 382                 status = "disabled";
 383         };
 384
 385         pwm: pwm@7000a000 {
 386                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 387                 reg = <0x0 0x7000a000 0x0 0x100>;
 388                 #pwm-cells = <2>;
 389                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 390                 resets = <&tegra_car 17>;
 391                 reset-names = "pwm";
 392                 status = "disabled";
 393         };
 394
 395         i2c@7000c000 {
 396                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 397                 reg = <0x0 0x7000c000 0x0 0x100>;
 398                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 399                 #address-cells = <1>;
 400                 #size-cells = <0>;
 401                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 402                 clock-names = "div-clk";
 403                 resets = <&tegra_car 12>;
 404                 reset-names = "i2c";
 405                 dmas = <&apbdma 21>, <&apbdma 21>;
 406                 dma-names = "rx", "tx";
 407                 status = "disabled";
 408         };
 409
 410         i2c@7000c400 {
 411                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 412                 reg = <0x0 0x7000c400 0x0 0x100>;
 413                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 417                 clock-names = "div-clk";
 418                 resets = <&tegra_car 54>;
 419                 reset-names = "i2c";
 420                 dmas = <&apbdma 22>, <&apbdma 22>;
 421                 dma-names = "rx", "tx";
 422                 status = "disabled";
 423         };
 424
 425         i2c@7000c500 {
 426                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 427                 reg = <0x0 0x7000c500 0x0 0x100>;
 428                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 432                 clock-names = "div-clk";
 433                 resets = <&tegra_car 67>;
 434                 reset-names = "i2c";
 435                 dmas = <&apbdma 23>, <&apbdma 23>;
 436                 dma-names = "rx", "tx";
 437                 status = "disabled";
 438         };
 439
 440         i2c@7000c700 {
 441                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 442                 reg = <0x0 0x7000c700 0x0 0x100>;
 443                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 447                 clock-names = "div-clk";
 448                 resets = <&tegra_car 103>;
 449                 reset-names = "i2c";
 450                 dmas = <&apbdma 26>, <&apbdma 26>;
 451                 dma-names = "rx", "tx";
 452                 status = "disabled";
 453         };
 454
 455         i2c@7000d000 {
 456                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 457                 reg = <0x0 0x7000d000 0x0 0x100>;
 458                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 462                 clock-names = "div-clk";
 463                 resets = <&tegra_car 47>;
 464                 reset-names = "i2c";
 465                 dmas = <&apbdma 24>, <&apbdma 24>;
 466                 dma-names = "rx", "tx";
 467                 status = "disabled";
 468         };
 469
 470         i2c@7000d100 {
 471                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 472                 reg = <0x0 0x7000d100 0x0 0x100>;
 473                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 477                 clock-names = "div-clk";
 478                 resets = <&tegra_car 166>;
 479                 reset-names = "i2c";
 480                 dmas = <&apbdma 30>, <&apbdma 30>;
 481                 dma-names = "rx", "tx";
 482                 status = "disabled";
 483         };
 484
 485         spi@7000d400 {
 486                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 487                 reg = <0x0 0x7000d400 0x0 0x200>;
 488                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 489                 #address-cells = <1>;
 490                 #size-cells = <0>;
 491                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 492                 clock-names = "spi";
 493                 resets = <&tegra_car 41>;
 494                 reset-names = "spi";
 495                 dmas = <&apbdma 15>, <&apbdma 15>;
 496                 dma-names = "rx", "tx";
 497                 status = "disabled";
 498         };
 499
 500         spi@7000d600 {
 501                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 502                 reg = <0x0 0x7000d600 0x0 0x200>;
 503                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 504                 #address-cells = <1>;
 505                 #size-cells = <0>;
 506                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 507                 clock-names = "spi";
 508                 resets = <&tegra_car 44>;
 509                 reset-names = "spi";
 510                 dmas = <&apbdma 16>, <&apbdma 16>;
 511                 dma-names = "rx", "tx";
 512                 status = "disabled";
 513         };
 514
 515         spi@7000d800 {
 516                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 517                 reg = <0x0 0x7000d800 0x0 0x200>;
 518                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 519                 #address-cells = <1>;
 520                 #size-cells = <0>;
 521                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 522                 clock-names = "spi";
 523                 resets = <&tegra_car 46>;
 524                 reset-names = "spi";
 525                 dmas = <&apbdma 17>, <&apbdma 17>;
 526                 dma-names = "rx", "tx";
 527                 status = "disabled";
 528         };
 529
 530         spi@7000da00 {
 531                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 532                 reg = <0x0 0x7000da00 0x0 0x200>;
 533                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 534                 #address-cells = <1>;
 535                 #size-cells = <0>;
 536                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 537                 clock-names = "spi";
 538                 resets = <&tegra_car 68>;
 539                 reset-names = "spi";
 540                 dmas = <&apbdma 18>, <&apbdma 18>;
 541                 dma-names = "rx", "tx";
 542                 status = "disabled";
 543         };
 544
 545         spi@7000dc00 {
 546                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 547                 reg = <0x0 0x7000dc00 0x0 0x200>;
 548                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 549                 #address-cells = <1>;
 550                 #size-cells = <0>;
 551                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 552                 clock-names = "spi";
 553                 resets = <&tegra_car 104>;
 554                 reset-names = "spi";
 555                 dmas = <&apbdma 27>, <&apbdma 27>;
 556                 dma-names = "rx", "tx";
 557                 status = "disabled";
 558         };
 559
 560         spi@7000de00 {
 561                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 562                 reg = <0x0 0x7000de00 0x0 0x200>;
 563                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 564                 #address-cells = <1>;
 565                 #size-cells = <0>;
 566                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 567                 clock-names = "spi";
 568                 resets = <&tegra_car 105>;
 569                 reset-names = "spi";
 570                 dmas = <&apbdma 28>, <&apbdma 28>;
 571                 dma-names = "rx", "tx";
 572                 status = "disabled";
 573         };
 574
 575         rtc@7000e000 {
 576                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 577                 reg = <0x0 0x7000e000 0x0 0x100>;
 578                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 579                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 580         };
 581
 582         pmc@7000e400 {
 583                 compatible = "nvidia,tegra124-pmc";
 584                 reg = <0x0 0x7000e400 0x0 0x400>;
 585                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 586                 clock-names = "pclk", "clk32k_in";
 587         };
 588
 589         fuse@7000f800 {
 590                 compatible = "nvidia,tegra124-efuse";
 591                 reg = <0x0 0x7000f800 0x0 0x400>;
 592                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
 593                 clock-names = "fuse";
 594                 resets = <&tegra_car 39>;
 595                 reset-names = "fuse";
 596         };
 597
 598         mc: memory-controller@70019000 {
 599                 compatible = "nvidia,tegra124-mc";
 600                 reg = <0x0 0x70019000 0x0 0x1000>;
 601                 clocks = <&tegra_car TEGRA124_CLK_MC>;
 602                 clock-names = "mc";
 603
 604                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 605
 606                 #iommu-cells = <1>;
 607         };
 608
 609         emc: emc@7001b000 {
 610                 compatible = "nvidia,tegra124-emc";
 611                 reg = <0x0 0x7001b000 0x0 0x1000>;
 612
 613                 nvidia,memory-controller = <&mc>;
 614         };
 615
 616         sata@70020000 {
 617                 compatible = "nvidia,tegra124-ahci";
 618                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 619                       <0x0 0x70020000 0x0 0x7000>; /* SATA */
 620                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 621                 clocks = <&tegra_car TEGRA124_CLK_SATA>,
 622                          <&tegra_car TEGRA124_CLK_SATA_OOB>,
 623                          <&tegra_car TEGRA124_CLK_CML1>,
 624                          <&tegra_car TEGRA124_CLK_PLL_E>;
 625                 clock-names = "sata", "sata-oob", "cml1", "pll_e";
 626                 resets = <&tegra_car 124>,
 627                          <&tegra_car 123>,
 628                          <&tegra_car 129>;
 629                 reset-names = "sata", "sata-oob", "sata-cold";
 630                 status = "disabled";
 631         };
 632
 633         hda@70030000 {
 634                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
 635                 reg = <0x0 0x70030000 0x0 0x10000>;
 636                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&tegra_car TEGRA124_CLK_HDA>,
 638                          <&tegra_car TEGRA124_CLK_HDA2HDMI>,
 639                          <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
 640                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 641                 resets = <&tegra_car 125>, /* hda */
 642                          <&tegra_car 128>, /* hda2hdmi */
 643                          <&tegra_car 111>; /* hda2codec_2x */
 644                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 645                 status = "disabled";
 646         };
 647
 648         usb@70090000 {
 649                 compatible = "nvidia,tegra124-xusb";
 650                 reg = <0x0 0x70090000 0x0 0x8000>,
 651                       <0x0 0x70098000 0x0 0x1000>,
 652                       <0x0 0x70099000 0x0 0x1000>;
 653                 reg-names = "hcd", "fpci", "ipfs";
 654
 655                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 656                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 657
 658                 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
 659                          <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
 660                          <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
 661                          <&tegra_car TEGRA124_CLK_XUSB_SS>,
 662                          <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
 663                          <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
 664                          <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
 665                          <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
 666                          <&tegra_car TEGRA124_CLK_PLL_U_480M>,
 667                          <&tegra_car TEGRA124_CLK_CLK_M>,
 668                          <&tegra_car TEGRA124_CLK_PLL_E>;
 669                 clock-names = "xusb_host", "xusb_host_src",
 670                               "xusb_falcon_src", "xusb_ss",
 671                               "xusb_ss_div2", "xusb_ss_src",
 672                               "xusb_hs_src", "xusb_fs_src",
 673                               "pll_u_480m", "clk_m", "pll_e";
 674                 resets = <&tegra_car 89>, <&tegra_car 156>,
 675                          <&tegra_car 143>;
 676                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
 677
 678                 nvidia,xusb-padctl = <&padctl>;
 679
 680                 status = "disabled";
 681         };
 682
 683         padctl: padctl@7009f000 {
 684                 compatible = "nvidia,tegra124-xusb-padctl";
 685                 reg = <0x0 0x7009f000 0x0 0x1000>;
 686                 resets = <&tegra_car 142>;
 687                 reset-names = "padctl";
 688
 689                 pads {
 690                         usb2 {
 691                                 status = "disabled";
 692
 693                                 lanes {
 694                                         usb2-0 {
 695                                                 status = "disabled";
 696                                                 #phy-cells = <0>;
 697                                         };
 698
 699                                         usb2-1 {
 700                                                 status = "disabled";
 701                                                 #phy-cells = <0>;
 702                                         };
 703
 704                                         usb2-2 {
 705                                                 status = "disabled";
 706                                                 #phy-cells = <0>;
 707                                         };
 708                                 };
 709                         };
 710
 711                         ulpi {
 712                                 status = "disabled";
 713
 714                                 lanes {
 715                                         ulpi-0 {
 716                                                 status = "disabled";
 717                                                 #phy-cells = <0>;
 718                                         };
 719                                 };
 720                         };
 721
 722                         hsic {
 723                                 status = "disabled";
 724
 725                                 lanes {
 726                                         hsic-0 {
 727                                                 status = "disabled";
 728                                                 #phy-cells = <0>;
 729                                         };
 730
 731                                         hsic-1 {
 732                                                 status = "disabled";
 733                                                 #phy-cells = <0>;
 734                                         };
 735                                 };
 736                         };
 737
 738                         pcie {
 739                                 status = "disabled";
 740
 741                                 lanes {
 742                                         pcie-0 {
 743                                                 status = "disabled";
 744                                                 #phy-cells = <0>;
 745                                         };
 746
 747                                         pcie-1 {
 748                                                 status = "disabled";
 749                                                 #phy-cells = <0>;
 750                                         };
 751
 752                                         pcie-2 {
 753                                                 status = "disabled";
 754                                                 #phy-cells = <0>;
 755                                         };
 756
 757                                         pcie-3 {
 758                                                 status = "disabled";
 759                                                 #phy-cells = <0>;
 760                                         };
 761
 762                                         pcie-4 {
 763                                                 status = "disabled";
 764                                                 #phy-cells = <0>;
 765                                         };
 766                                 };
 767                         };
 768
 769                         sata {
 770                                 status = "disabled";
 771
 772                                 lanes {
 773                                         sata-0 {
 774                                                 status = "disabled";
 775                                                 #phy-cells = <0>;
 776                                         };
 777                                 };
 778                         };
 779                 };
 780
 781                 ports {
 782                         usb2-0 {
 783                                 status = "disabled";
 784                         };
 785
 786                         usb2-1 {
 787                                 status = "disabled";
 788                         };
 789
 790                         usb2-2 {
 791                                 status = "disabled";
 792                         };
 793
 794                         ulpi-0 {
 795                                 status = "disabled";
 796                         };
 797
 798                         hsic-0 {
 799                                 status = "disabled";
 800                         };
 801
 802                         hsic-1 {
 803                                 status = "disabled";
 804                         };
 805
 806                         usb3-0 {
 807                                 status = "disabled";
 808                         };
 809
 810                         usb3-1 {
 811                                 status = "disabled";
 812                         };
 813                 };
 814         };
 815
 816         sdhci@700b0000 {
 817                 compatible = "nvidia,tegra124-sdhci";
 818                 reg = <0x0 0x700b0000 0x0 0x200>;
 819                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 820                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 821                 resets = <&tegra_car 14>;
 822                 reset-names = "sdhci";
 823                 status = "disabled";
 824         };
 825
 826         sdhci@700b0200 {
 827                 compatible = "nvidia,tegra124-sdhci";
 828                 reg = <0x0 0x700b0200 0x0 0x200>;
 829                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 830                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 831                 resets = <&tegra_car 9>;
 832                 reset-names = "sdhci";
 833                 status = "disabled";
 834         };
 835
 836         sdhci@700b0400 {
 837                 compatible = "nvidia,tegra124-sdhci";
 838                 reg = <0x0 0x700b0400 0x0 0x200>;
 839                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 840                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 841                 resets = <&tegra_car 69>;
 842                 reset-names = "sdhci";
 843                 status = "disabled";
 844         };
 845
 846         sdhci@700b0600 {
 847                 compatible = "nvidia,tegra124-sdhci";
 848                 reg = <0x0 0x700b0600 0x0 0x200>;
 849                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 850                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 851                 resets = <&tegra_car 15>;
 852                 reset-names = "sdhci";
 853                 status = "disabled";
 854         };
 855
 856         cec@70015000 {
 857                 compatible = "nvidia,tegra124-cec";
 858                 reg = <0x0 0x70015000 0x0 0x00001000>;
 859                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 860                 clocks = <&tegra_car TEGRA124_CLK_CEC>;
 861                 clock-names = "cec";
 862                 status = "disabled";
 863                 hdmi-phandle = <&hdmi>;
 864         };
 865
 866         soctherm: thermal-sensor@700e2000 {
 867                 compatible = "nvidia,tegra124-soctherm";
 868                 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
 869                         0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
 870                 reg-names = "soctherm-reg", "car-reg";
 871                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 872                 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
 873                         <&tegra_car TEGRA124_CLK_SOC_THERM>;
 874                 clock-names = "tsensor", "soctherm";
 875                 resets = <&tegra_car 78>;
 876                 reset-names = "soctherm";
 877                 #thermal-sensor-cells = <1>;
 878
 879                 throttle-cfgs {
 880                         throttle_heavy: heavy {
 881                                 nvidia,priority = <100>;
 882                                 nvidia,cpu-throt-percent = <85>;
 883
 884                                 #cooling-cells = <2>;
 885                         };
 886                 };
 887         };
 888
 889         dfll: clock@70110000 {
 890                 compatible = "nvidia,tegra124-dfll";
 891                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
 892                       <0 0x70110000 0 0x100>, /* I2C output control */
 893                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
 894                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
 895                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 896                 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
 897                          <&tegra_car TEGRA124_CLK_DFLL_REF>,
 898                          <&tegra_car TEGRA124_CLK_I2C5>;
 899                 clock-names = "soc", "ref", "i2c";
 900                 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
 901                 reset-names = "dvco";
 902                 #clock-cells = <0>;
 903                 clock-output-names = "dfllCPU_out";
 904                 nvidia,sample-rate = <12500>;
 905                 nvidia,droop-ctrl = <0x00000f00>;
 906                 nvidia,force-mode = <1>;
 907                 nvidia,cf = <10>;
 908                 nvidia,ci = <0>;
 909                 nvidia,cg = <2>;
 910                 status = "disabled";
 911         };
 912
 913         ahub@70300000 {
 914                 compatible = "nvidia,tegra124-ahub";
 915                 reg = <0x0 0x70300000 0x0 0x200>,
 916                       <0x0 0x70300800 0x0 0x800>,
 917                       <0x0 0x70300200 0x0 0x600>;
 918                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 919                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 920                          <&tegra_car TEGRA124_CLK_APBIF>;
 921                 clock-names = "d_audio", "apbif";
 922                 resets = <&tegra_car 106>, /* d_audio */
 923                          <&tegra_car 107>, /* apbif */
 924                          <&tegra_car 30>,  /* i2s0 */
 925                          <&tegra_car 11>,  /* i2s1 */
 926                          <&tegra_car 18>,  /* i2s2 */
 927                          <&tegra_car 101>, /* i2s3 */
 928                          <&tegra_car 102>, /* i2s4 */
 929                          <&tegra_car 108>, /* dam0 */
 930                          <&tegra_car 109>, /* dam1 */
 931                          <&tegra_car 110>, /* dam2 */
 932                          <&tegra_car 10>,  /* spdif */
 933                          <&tegra_car 153>, /* amx */
 934                          <&tegra_car 185>, /* amx1 */
 935                          <&tegra_car 154>, /* adx */
 936                          <&tegra_car 180>, /* adx1 */
 937                          <&tegra_car 186>, /* afc0 */
 938                          <&tegra_car 187>, /* afc1 */
 939                          <&tegra_car 188>, /* afc2 */
 940                          <&tegra_car 189>, /* afc3 */
 941                          <&tegra_car 190>, /* afc4 */
 942                          <&tegra_car 191>; /* afc5 */
 943                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 944                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 945                               "spdif", "amx", "amx1", "adx", "adx1",
 946                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 947                 dmas = <&apbdma 1>, <&apbdma 1>,
 948                        <&apbdma 2>, <&apbdma 2>,
 949                        <&apbdma 3>, <&apbdma 3>,
 950                        <&apbdma 4>, <&apbdma 4>,
 951                        <&apbdma 6>, <&apbdma 6>,
 952                        <&apbdma 7>, <&apbdma 7>,
 953                        <&apbdma 12>, <&apbdma 12>,
 954                        <&apbdma 13>, <&apbdma 13>,
 955                        <&apbdma 14>, <&apbdma 14>,
 956                        <&apbdma 29>, <&apbdma 29>;
 957                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 958                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 959                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 960                             "rx9", "tx9";
 961                 ranges;
 962                 #address-cells = <2>;
 963                 #size-cells = <2>;
 964
 965                 tegra_i2s0: i2s@70301000 {
 966                         compatible = "nvidia,tegra124-i2s";
 967                         reg = <0x0 0x70301000 0x0 0x100>;
 968                         nvidia,ahub-cif-ids = <4 4>;
 969                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 970                         resets = <&tegra_car 30>;
 971                         reset-names = "i2s";
 972                         status = "disabled";
 973                 };
 974
 975                 tegra_i2s1: i2s@70301100 {
 976                         compatible = "nvidia,tegra124-i2s";
 977                         reg = <0x0 0x70301100 0x0 0x100>;
 978                         nvidia,ahub-cif-ids = <5 5>;
 979                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 980                         resets = <&tegra_car 11>;
 981                         reset-names = "i2s";
 982                         status = "disabled";
 983                 };
 984
 985                 tegra_i2s2: i2s@70301200 {
 986                         compatible = "nvidia,tegra124-i2s";
 987                         reg = <0x0 0x70301200 0x0 0x100>;
 988                         nvidia,ahub-cif-ids = <6 6>;
 989                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 990                         resets = <&tegra_car 18>;
 991                         reset-names = "i2s";
 992                         status = "disabled";
 993                 };
 994
 995                 tegra_i2s3: i2s@70301300 {
 996                         compatible = "nvidia,tegra124-i2s";
 997                         reg = <0x0 0x70301300 0x0 0x100>;
 998                         nvidia,ahub-cif-ids = <7 7>;
 999                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1000                         resets = <&tegra_car 101>;
1001                         reset-names = "i2s";
1002                         status = "disabled";
1003                 };
1004
1005                 tegra_i2s4: i2s@70301400 {
1006                         compatible = "nvidia,tegra124-i2s";
1007                         reg = <0x0 0x70301400 0x0 0x100>;
1008                         nvidia,ahub-cif-ids = <8 8>;
1009                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1010                         resets = <&tegra_car 102>;
1011                         reset-names = "i2s";
1012                         status = "disabled";
1013                 };
1014         };
1015
1016         usb@7d000000 {
1017                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1018                 reg = <0x0 0x7d000000 0x0 0x4000>;
1019                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1020                 phy_type = "utmi";
1021                 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1022                 resets = <&tegra_car 22>;
1023                 reset-names = "usb";
1024                 nvidia,phy = <&phy1>;
1025                 status = "disabled";
1026         };
1027
1028         phy1: usb-phy@7d000000 {
1029                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1030                 reg = <0x0 0x7d000000 0x0 0x4000>,
1031                       <0x0 0x7d000000 0x0 0x4000>;
1032                 phy_type = "utmi";
1033                 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1034                          <&tegra_car TEGRA124_CLK_PLL_U>,
1035                          <&tegra_car TEGRA124_CLK_USBD>;
1036                 clock-names = "reg", "pll_u", "utmi-pads";
1037                 resets = <&tegra_car 22>, <&tegra_car 22>;
1038                 reset-names = "usb", "utmi-pads";
1039                 nvidia,hssync-start-delay = <0>;
1040                 nvidia,idle-wait-delay = <17>;
1041                 nvidia,elastic-limit = <16>;
1042                 nvidia,term-range-adj = <6>;
1043                 nvidia,xcvr-setup = <9>;
1044                 nvidia,xcvr-lsfslew = <0>;
1045                 nvidia,xcvr-lsrslew = <3>;
1046                 nvidia,hssquelch-level = <2>;
1047                 nvidia,hsdiscon-level = <5>;
1048                 nvidia,xcvr-hsslew = <12>;
1049                 nvidia,has-utmi-pad-registers;
1050                 status = "disabled";
1051         };
1052
1053         usb@7d004000 {
1054                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1055                 reg = <0x0 0x7d004000 0x0 0x4000>;
1056                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1057                 phy_type = "utmi";
1058                 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1059                 resets = <&tegra_car 58>;
1060                 reset-names = "usb";
1061                 nvidia,phy = <&phy2>;
1062                 status = "disabled";
1063         };
1064
1065         phy2: usb-phy@7d004000 {
1066                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1067                 reg = <0x0 0x7d004000 0x0 0x4000>,
1068                       <0x0 0x7d000000 0x0 0x4000>;
1069                 phy_type = "utmi";
1070                 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1071                          <&tegra_car TEGRA124_CLK_PLL_U>,
1072                          <&tegra_car TEGRA124_CLK_USBD>;
1073                 clock-names = "reg", "pll_u", "utmi-pads";
1074                 resets = <&tegra_car 58>, <&tegra_car 22>;
1075                 reset-names = "usb", "utmi-pads";
1076                 nvidia,hssync-start-delay = <0>;
1077                 nvidia,idle-wait-delay = <17>;
1078                 nvidia,elastic-limit = <16>;
1079                 nvidia,term-range-adj = <6>;
1080                 nvidia,xcvr-setup = <9>;
1081                 nvidia,xcvr-lsfslew = <0>;
1082                 nvidia,xcvr-lsrslew = <3>;
1083                 nvidia,hssquelch-level = <2>;
1084                 nvidia,hsdiscon-level = <5>;
1085                 nvidia,xcvr-hsslew = <12>;
1086                 status = "disabled";
1087         };
1088
1089         usb@7d008000 {
1090                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1091                 reg = <0x0 0x7d008000 0x0 0x4000>;
1092                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1093                 phy_type = "utmi";
1094                 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1095                 resets = <&tegra_car 59>;
1096                 reset-names = "usb";
1097                 nvidia,phy = <&phy3>;
1098                 status = "disabled";
1099         };
1100
1101         phy3: usb-phy@7d008000 {
1102                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1103                 reg = <0x0 0x7d008000 0x0 0x4000>,
1104                       <0x0 0x7d000000 0x0 0x4000>;
1105                 phy_type = "utmi";
1106                 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1107                          <&tegra_car TEGRA124_CLK_PLL_U>,
1108                          <&tegra_car TEGRA124_CLK_USBD>;
1109                 clock-names = "reg", "pll_u", "utmi-pads";
1110                 resets = <&tegra_car 59>, <&tegra_car 22>;
1111                 reset-names = "usb", "utmi-pads";
1112                 nvidia,hssync-start-delay = <0>;
1113                 nvidia,idle-wait-delay = <17>;
1114                 nvidia,elastic-limit = <16>;
1115                 nvidia,term-range-adj = <6>;
1116                 nvidia,xcvr-setup = <9>;
1117                 nvidia,xcvr-lsfslew = <0>;
1118                 nvidia,xcvr-lsrslew = <3>;
1119                 nvidia,hssquelch-level = <2>;
1120                 nvidia,hsdiscon-level = <5>;
1121                 nvidia,xcvr-hsslew = <12>;
1122                 status = "disabled";
1123         };
1124
1125         cpus {
1126                 #address-cells = <1>;
1127                 #size-cells = <0>;
1128
1129                 cpu@0 {
1130                         device_type = "cpu";
1131                         compatible = "arm,cortex-a15";
1132                         reg = <0>;
1133
1134                         clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1135                                  <&tegra_car TEGRA124_CLK_CCLK_LP>,
1136                                  <&tegra_car TEGRA124_CLK_PLL_X>,
1137                                  <&tegra_car TEGRA124_CLK_PLL_P>,
1138                                  <&dfll>;
1139                         clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1140                         /* FIXME: what's the actual transition time? */
1141                         clock-latency = <300000>;
1142                 };
1143
1144                 cpu@1 {
1145                         device_type = "cpu";
1146                         compatible = "arm,cortex-a15";
1147                         reg = <1>;
1148                 };
1149
1150                 cpu@2 {
1151                         device_type = "cpu";
1152                         compatible = "arm,cortex-a15";
1153                         reg = <2>;
1154                 };
1155
1156                 cpu@3 {
1157                         device_type = "cpu";
1158                         compatible = "arm,cortex-a15";
1159                         reg = <3>;
1160                 };
1161         };
1162
1163         pmu {
1164                 compatible = "arm,cortex-a15-pmu";
1165                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1166                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1167                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1168                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1169                 interrupt-affinity = <&{/cpus/cpu@0}>,
1170                                      <&{/cpus/cpu@1}>,
1171                                      <&{/cpus/cpu@2}>,
1172                                      <&{/cpus/cpu@3}>;
1173         };
1174
1175         thermal-zones {
1176                 cpu {
1177                         polling-delay-passive = <1000>;
1178                         polling-delay = <1000>;
1179
1180                         thermal-sensors =
1181                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1182
1183                         trips {
1184                                 cpu-shutdown-trip {
1185                                         temperature = <103000>;
1186                                         hysteresis = <0>;
1187                                         type = "critical";
1188                                 };
1189                                 cpu_throttle_trip: throttle-trip {
1190                                         temperature = <100000>;
1191                                         hysteresis = <1000>;
1192                                         type = "hot";
1193                                 };
1194                         };
1195
1196                         cooling-maps {
1197                                 map0 {
1198                                         trip = <&cpu_throttle_trip>;
1199                                         cooling-device = <&throttle_heavy 1 1>;
1200                                 };
1201                         };
1202                 };
1203
1204                 mem {
1205                         polling-delay-passive = <1000>;
1206                         polling-delay = <1000>;
1207
1208                         thermal-sensors =
1209                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1210
1211                         trips {
1212                                 mem-shutdown-trip {
1213                                         temperature = <103000>;
1214                                         hysteresis = <0>;
1215                                         type = "critical";
1216                                 };
1217                         };
1218
1219                         cooling-maps {
1220                                 /*
1221                                  * There are currently no cooling maps,
1222                                  * because there are no cooling devices.
1223                                  */
1224                         };
1225                 };
1226
1227                 gpu {
1228                         polling-delay-passive = <1000>;
1229                         polling-delay = <1000>;
1230
1231                         thermal-sensors =
1232                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1233
1234                         trips {
1235                                 gpu-shutdown-trip {
1236                                         temperature = <101000>;
1237                                         hysteresis = <0>;
1238                                         type = "critical";
1239                                 };
1240                                 gpu_throttle_trip: throttle-trip {
1241                                         temperature = <99000>;
1242                                         hysteresis = <1000>;
1243                                         type = "hot";
1244                                 };
1245                         };
1246
1247                         cooling-maps {
1248                                 map0 {
1249                                         trip = <&gpu_throttle_trip>;
1250                                         cooling-device = <&throttle_heavy 1 1>;
1251                                 };
1252                         };
1253                 };
1254
1255                 pllx {
1256                         polling-delay-passive = <1000>;
1257                         polling-delay = <1000>;
1258
1259                         thermal-sensors =
1260                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1261
1262                         trips {
1263                                 pllx-shutdown-trip {
1264                                         temperature = <103000>;
1265                                         hysteresis = <0>;
1266                                         type = "critical";
1267                                 };
1268                         };
1269
1270                         cooling-maps {
1271                                 /*
1272                                  * There are currently no cooling maps,
1273                                  * because there are no cooling devices.
1274                                  */
1275                         };
1276                 };
1277         };
1278
1279         timer {
1280                 compatible = "arm,armv7-timer";
1281                 interrupts = <GIC_PPI 13
1282                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1283                              <GIC_PPI 14
1284                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1285                              <GIC_PPI 11
1286                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1287                              <GIC_PPI 10
1288                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1289                 interrupt-parent = <&gic>;
1290         };
1291 };