| blob | 813ae34edd6a33a9113d4f4bc2d6e44ea0e4cf2f |
1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra20.dtsi"
4 / {
5 model = "Toradex Colibri T20 512MB";
6 compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
8 aliases {
9 rtc0 = "/i2c@7000d000/tps6586x@34";
10 rtc1 = "/rtc@7000e000";
11 };
13 memory {
14 reg = <0x00000000 0x20000000>;
15 };
17 host1x@50000000 {
18 hdmi@54280000 {
19 vdd-supply = <&hdmi_vdd_reg>;
20 pll-supply = <&hdmi_pll_reg>;
22 nvidia,ddc-i2c-bus = <&i2c_ddc>;
23 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
24 GPIO_ACTIVE_HIGH>;
25 };
26 };
28 pinmux@70000014 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&state_default>;
32 state_default: pinmux {
33 audio_refclk {
34 nvidia,pins = "cdev1";
35 nvidia,function = "plla_out";
36 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
37 nvidia,tristate = <TEGRA_PIN_DISABLE>;
38 };
39 crt {
40 nvidia,pins = "crtp";
41 nvidia,function = "crt";
42 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
43 nvidia,tristate = <TEGRA_PIN_ENABLE>;
44 };
45 dap3 {
46 nvidia,pins = "dap3";
47 nvidia,function = "dap3";
48 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
49 nvidia,tristate = <TEGRA_PIN_DISABLE>;
50 };
51 displaya {
52 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
53 "ld4", "ld5", "ld6", "ld7", "ld8",
54 "ld9", "ld10", "ld11", "ld12", "ld13",
55 "ld14", "ld15", "ld16", "ld17",
56 "lhs", "lpw0", "lpw2", "lsc0",
57 "lsc1", "lsck", "lsda", "lspi", "lvs";
58 nvidia,function = "displaya";
59 nvidia,tristate = <TEGRA_PIN_ENABLE>;
60 };
61 gpio_dte {
62 nvidia,pins = "dte";
63 nvidia,function = "rsvd1";
64 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
65 nvidia,tristate = <TEGRA_PIN_DISABLE>;
66 };
67 gpio_gmi {
68 nvidia,pins = "ata", "atc", "atd", "ate",
69 "dap1", "dap2", "dap4", "gpu", "irrx",
70 "irtx", "spia", "spib", "spic";
71 nvidia,function = "gmi";
72 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
73 nvidia,tristate = <TEGRA_PIN_DISABLE>;
74 };
75 gpio_pta {
76 nvidia,pins = "pta";
77 nvidia,function = "rsvd4";
78 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 };
81 gpio_uac {
82 nvidia,pins = "uac";
83 nvidia,function = "rsvd2";
84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
86 };
87 hdint {
88 nvidia,pins = "hdint";
89 nvidia,function = "hdmi";
90 nvidia,tristate = <TEGRA_PIN_ENABLE>;
91 };
92 i2c1 {
93 nvidia,pins = "rm";
94 nvidia,function = "i2c1";
95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <TEGRA_PIN_ENABLE>;
97 };
98 i2c3 {
99 nvidia,pins = "dtf";
100 nvidia,function = "i2c3";
101 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
102 nvidia,tristate = <TEGRA_PIN_ENABLE>;
103 };
104 i2cddc {
105 nvidia,pins = "ddc";
106 nvidia,function = "i2c2";
107 nvidia,pull = <TEGRA_PIN_PULL_UP>;
108 nvidia,tristate = <TEGRA_PIN_ENABLE>;
109 };
110 i2cp {
111 nvidia,pins = "i2cp";
112 nvidia,function = "i2cp";
113 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114 nvidia,tristate = <TEGRA_PIN_DISABLE>;
115 };
116 irda {
117 nvidia,pins = "uad";
118 nvidia,function = "irda";
119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120 nvidia,tristate = <TEGRA_PIN_ENABLE>;
121 };
122 nand {
123 nvidia,pins = "kbca", "kbcc", "kbcd",
124 "kbce", "kbcf";
125 nvidia,function = "nand";
126 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
127 nvidia,tristate = <TEGRA_PIN_DISABLE>;
128 };
129 owc {
130 nvidia,pins = "owc";
131 nvidia,function = "owr";
132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristate = <TEGRA_PIN_ENABLE>;
134 };
135 pmc {
136 nvidia,pins = "pmc";
137 nvidia,function = "pwr_on";
138 nvidia,tristate = <TEGRA_PIN_DISABLE>;
139 };
140 pwm {
141 nvidia,pins = "sdb", "sdc", "sdd";
142 nvidia,function = "pwm";
143 nvidia,tristate = <TEGRA_PIN_ENABLE>;
144 };
145 sdio4 {
146 nvidia,pins = "atb", "gma", "gme";
147 nvidia,function = "sdio4";
148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <TEGRA_PIN_ENABLE>;
150 };
151 spi1 {
152 nvidia,pins = "spid", "spie", "spif";
153 nvidia,function = "spi1";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_ENABLE>;
156 };
157 spi4 {
158 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
159 nvidia,function = "spi4";
160 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
161 nvidia,tristate = <TEGRA_PIN_ENABLE>;
162 };
163 uarta {
164 nvidia,pins = "sdio1";
165 nvidia,function = "uarta";
166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristate = <TEGRA_PIN_ENABLE>;
168 };
169 uartd {
170 nvidia,pins = "gmc";
171 nvidia,function = "uartd";
172 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173 nvidia,tristate = <TEGRA_PIN_ENABLE>;
174 };
175 ulpi {
176 nvidia,pins = "uaa", "uab", "uda";
177 nvidia,function = "ulpi";
178 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
179 nvidia,tristate = <TEGRA_PIN_DISABLE>;
180 };
181 ulpi_refclk {
182 nvidia,pins = "cdev2";
183 nvidia,function = "pllp_out4";
184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 };
187 usb_gpio {
188 nvidia,pins = "spig", "spih";
189 nvidia,function = "spi2_alt";
190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 nvidia,tristate = <TEGRA_PIN_DISABLE>;
192 };
193 vi {
194 nvidia,pins = "dta", "dtb", "dtc", "dtd";
195 nvidia,function = "vi";
196 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
197 nvidia,tristate = <TEGRA_PIN_ENABLE>;
198 };
199 vi_sc {
200 nvidia,pins = "csus";
201 nvidia,function = "vi_sensor_clk";
202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
203 nvidia,tristate = <TEGRA_PIN_ENABLE>;
204 };
205 };
206 };
208 ac97: ac97@70002000 {
209 status = "okay";
210 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
211 GPIO_ACTIVE_HIGH>;
212 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
213 GPIO_ACTIVE_HIGH>;
214 };
216 i2c@7000c000 {
217 clock-frequency = <400000>;
218 };
220 i2c_ddc: i2c@7000c400 {
221 clock-frequency = <100000>;
222 };
224 i2c@7000c500 {
225 clock-frequency = <400000>;
226 };
228 i2c@7000d000 {
229 status = "okay";
230 clock-frequency = <400000>;
232 pmic: tps6586x@34 {
233 compatible = "ti,tps6586x";
234 reg = <0x34>;
235 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
237 ti,system-power-controller;
239 #gpio-cells = <2>;
240 gpio-controller;
242 sys-supply = <&vdd_3v3_reg>;
243 vin-sm0-supply = <&sys_reg>;
244 vin-sm1-supply = <&sys_reg>;
245 vin-sm2-supply = <&sys_reg>;
246 vinldo01-supply = <&sm2_reg>;
247 vinldo23-supply = <&vdd_3v3_reg>;
248 vinldo4-supply = <&vdd_3v3_reg>;
249 vinldo678-supply = <&vdd_3v3_reg>;
250 vinldo9-supply = <&vdd_3v3_reg>;
252 regulators {
253 #address-cells = <1>;
254 #size-cells = <0>;
256 sys_reg: regulator@0 {
257 reg = <0>;
258 regulator-compatible = "sys";
259 regulator-name = "vdd_sys";
260 regulator-always-on;
261 };
263 regulator@1 {
264 reg = <1>;
265 regulator-compatible = "sm0";
266 regulator-name = "vdd_sm0,vdd_core";
267 regulator-min-microvolt = <1200000>;
268 regulator-max-microvolt = <1200000>;
269 regulator-always-on;
270 };
272 regulator@2 {
273 reg = <2>;
274 regulator-compatible = "sm1";
275 regulator-name = "vdd_sm1,vdd_cpu";
276 regulator-min-microvolt = <1000000>;
277 regulator-max-microvolt = <1000000>;
278 regulator-always-on;
279 };
281 sm2_reg: regulator@3 {
282 reg = <3>;
283 regulator-compatible = "sm2";
284 regulator-name = "vdd_sm2,vin_ldo*";
285 regulator-min-microvolt = <1800000>;
286 regulator-max-microvolt = <1800000>;
287 regulator-always-on;
288 };
290 /* LDO0 is not connected to anything */
292 regulator@5 {
293 reg = <5>;
294 regulator-compatible = "ldo1";
295 regulator-name = "vdd_ldo1,avdd_pll*";
296 regulator-min-microvolt = <1100000>;
297 regulator-max-microvolt = <1100000>;
298 regulator-always-on;
299 };
301 regulator@6 {
302 reg = <6>;
303 regulator-compatible = "ldo2";
304 regulator-name = "vdd_ldo2,vdd_rtc";
305 regulator-min-microvolt = <1200000>;
306 regulator-max-microvolt = <1200000>;
307 };
309 /* LDO3 is not connected to anything */
311 regulator@8 {
312 reg = <8>;
313 regulator-compatible = "ldo4";
314 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
315 regulator-min-microvolt = <1800000>;
316 regulator-max-microvolt = <1800000>;
317 regulator-always-on;
318 };
320 ldo5_reg: regulator@9 {
321 reg = <9>;
322 regulator-compatible = "ldo5";
323 regulator-name = "vdd_ldo5,vdd_fuse";
324 regulator-min-microvolt = <3300000>;
325 regulator-max-microvolt = <3300000>;
326 regulator-always-on;
327 };
329 regulator@10 {
330 reg = <10>;
331 regulator-compatible = "ldo6";
332 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
333 regulator-min-microvolt = <2850000>;
334 regulator-max-microvolt = <2850000>;
335 };
337 hdmi_vdd_reg: regulator@11 {
338 reg = <11>;
339 regulator-compatible = "ldo7";
340 regulator-name = "vdd_ldo7,avdd_hdmi";
341 regulator-min-microvolt = <3300000>;
342 regulator-max-microvolt = <3300000>;
343 };
345 hdmi_pll_reg: regulator@12 {
346 reg = <12>;
347 regulator-compatible = "ldo8";
348 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
349 regulator-min-microvolt = <1800000>;
350 regulator-max-microvolt = <1800000>;
351 };
353 regulator@13 {
354 reg = <13>;
355 regulator-compatible = "ldo9";
356 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
357 regulator-min-microvolt = <2850000>;
358 regulator-max-microvolt = <2850000>;
359 regulator-always-on;
360 };
362 regulator@14 {
363 reg = <14>;
364 regulator-compatible = "ldo_rtc";
365 regulator-name = "vdd_rtc_out,vdd_cell";
366 regulator-min-microvolt = <3300000>;
367 regulator-max-microvolt = <3300000>;
368 regulator-always-on;
369 };
370 };
371 };
373 temperature-sensor@4c {
374 compatible = "national,lm95245";
375 reg = <0x4c>;
376 };
377 };
379 pmc@7000e400 {
380 nvidia,suspend-mode = <1>;
381 nvidia,cpu-pwr-good-time = <5000>;
382 nvidia,cpu-pwr-off-time = <5000>;
383 nvidia,core-pwr-good-time = <3845 3845>;
384 nvidia,core-pwr-off-time = <3875>;
385 nvidia,sys-clock-req-active-high;
386 };
388 memory-controller@7000f400 {
389 emc-table@83250 {
390 reg = <83250>;
391 compatible = "nvidia,tegra20-emc-table";
392 clock-frequency = <83250>;
393 nvidia,emc-registers = <0x00000005 0x00000011
394 0x00000004 0x00000002 0x00000004 0x00000004
395 0x00000001 0x0000000a 0x00000002 0x00000002
396 0x00000001 0x00000001 0x00000003 0x00000004
397 0x00000003 0x00000009 0x0000000c 0x0000025f
398 0x00000000 0x00000003 0x00000003 0x00000002
399 0x00000002 0x00000001 0x00000008 0x000000c8
400 0x00000003 0x00000005 0x00000003 0x0000000c
401 0x00000002 0x00000000 0x00000000 0x00000002
402 0x00000000 0x00000000 0x00000083 0x00520006
403 0x00000010 0x00000008 0x00000000 0x00000000
404 0x00000000 0x00000000 0x00000000 0x00000000>;
405 };
406 emc-table@133200 {
407 reg = <133200>;
408 compatible = "nvidia,tegra20-emc-table";
409 clock-frequency = <133200>;
410 nvidia,emc-registers = <0x00000008 0x00000019
411 0x00000006 0x00000002 0x00000004 0x00000004
412 0x00000001 0x0000000a 0x00000002 0x00000002
413 0x00000002 0x00000001 0x00000003 0x00000004
414 0x00000003 0x00000009 0x0000000c 0x0000039f
415 0x00000000 0x00000003 0x00000003 0x00000002
416 0x00000002 0x00000001 0x00000008 0x000000c8
417 0x00000003 0x00000007 0x00000003 0x0000000c
418 0x00000002 0x00000000 0x00000000 0x00000002
419 0x00000000 0x00000000 0x00000083 0x00510006
420 0x00000010 0x00000008 0x00000000 0x00000000
421 0x00000000 0x00000000 0x00000000 0x00000000>;
422 };
423 emc-table@166500 {
424 reg = <166500>;
425 compatible = "nvidia,tegra20-emc-table";
426 clock-frequency = <166500>;
427 nvidia,emc-registers = <0x0000000a 0x00000021
428 0x00000008 0x00000003 0x00000004 0x00000004
429 0x00000002 0x0000000a 0x00000003 0x00000003
430 0x00000002 0x00000001 0x00000003 0x00000004
431 0x00000003 0x00000009 0x0000000c 0x000004df
432 0x00000000 0x00000003 0x00000003 0x00000003
433 0x00000003 0x00000001 0x00000009 0x000000c8
434 0x00000003 0x00000009 0x00000004 0x0000000c
435 0x00000002 0x00000000 0x00000000 0x00000002
436 0x00000000 0x00000000 0x00000083 0x004f0006
437 0x00000010 0x00000008 0x00000000 0x00000000
438 0x00000000 0x00000000 0x00000000 0x00000000>;
439 };
440 emc-table@333000 {
441 reg = <333000>;
442 compatible = "nvidia,tegra20-emc-table";
443 clock-frequency = <333000>;
444 nvidia,emc-registers = <0x00000014 0x00000041
445 0x0000000f 0x00000005 0x00000004 0x00000005
446 0x00000003 0x0000000a 0x00000005 0x00000005
447 0x00000004 0x00000001 0x00000003 0x00000004
448 0x00000003 0x00000009 0x0000000c 0x000009ff
449 0x00000000 0x00000003 0x00000003 0x00000005
450 0x00000005 0x00000001 0x0000000e 0x000000c8
451 0x00000003 0x00000011 0x00000006 0x0000000c
452 0x00000002 0x00000000 0x00000000 0x00000002
453 0x00000000 0x00000000 0x00000083 0x00380006
454 0x00000010 0x00000008 0x00000000 0x00000000
455 0x00000000 0x00000000 0x00000000 0x00000000>;
456 };
457 };
459 usb@c5004000 {
460 status = "okay";
461 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
462 GPIO_ACTIVE_LOW>;
463 };
465 usb-phy@c5004000 {
466 status = "okay";
467 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
468 GPIO_ACTIVE_LOW>;
469 };
471 sdhci@c8000600 {
472 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
473 };
475 clocks {
476 compatible = "simple-bus";
477 #address-cells = <1>;
478 #size-cells = <0>;
480 clk32k_in: clock@0 {
481 compatible = "fixed-clock";
482 reg = <0>;
483 #clock-cells = <0>;
484 clock-frequency = <32768>;
485 };
486 };
488 regulators {
489 compatible = "simple-bus";
490 #address-cells = <1>;
491 #size-cells = <0>;
493 vdd_3v3_reg: regulator@100 {
494 compatible = "regulator-fixed";
495 reg = <100>;
496 regulator-name = "vdd_3v3";
497 regulator-min-microvolt = <3300000>;
498 regulator-max-microvolt = <3300000>;
499 regulator-always-on;
500 };
502 regulator@101 {
503 compatible = "regulator-fixed";
504 reg = <101>;
505 regulator-name = "internal_usb";
506 regulator-min-microvolt = <5000000>;
507 regulator-max-microvolt = <5000000>;
508 enable-active-high;
509 regulator-boot-on;
510 regulator-always-on;
511 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
512 };
513 };
515 sound {
516 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
517 "nvidia,tegra-audio-wm9712";
518 nvidia,model = "Colibri T20 AC97 Audio";
520 nvidia,audio-routing =
521 "Headphone", "HPOUTL",
522 "Headphone", "HPOUTR",
523 "LineIn", "LINEINL",
524 "LineIn", "LINEINR",
525 "Mic", "MIC1";
527 nvidia,ac97-controller = <&ac97>;
529 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
530 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
531 <&tegra_car TEGRA20_CLK_CDEV1>;
532 clock-names = "pll_a", "pll_a_out0", "mclk";
533 };
534 };