| blob | 864a95872b8db5a3c6afbb27d157e075d1894abc |
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "skeleton.dtsi"
9 / {
10 compatible = "nvidia,tegra20";
11 interrupt-parent = <&lic>;
13 iram@40000000 {
14 compatible = "mmio-sram";
15 reg = <0x40000000 0x40000>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges = <0 0x40000000 0x40000>;
20 vde_pool: vde {
21 reg = <0x400 0x3fc00>;
22 pool;
23 };
24 };
26 host1x@50000000 {
27 compatible = "nvidia,tegra20-host1x", "simple-bus";
28 reg = <0x50000000 0x00024000>;
29 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
30 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
31 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
32 resets = <&tegra_car 28>;
33 reset-names = "host1x";
35 #address-cells = <1>;
36 #size-cells = <1>;
38 ranges = <0x54000000 0x54000000 0x04000000>;
40 mpe@54040000 {
41 compatible = "nvidia,tegra20-mpe";
42 reg = <0x54040000 0x00040000>;
43 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
44 clocks = <&tegra_car TEGRA20_CLK_MPE>;
45 resets = <&tegra_car 60>;
46 reset-names = "mpe";
47 };
49 vi@54080000 {
50 compatible = "nvidia,tegra20-vi";
51 reg = <0x54080000 0x00040000>;
52 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
53 clocks = <&tegra_car TEGRA20_CLK_VI>;
54 resets = <&tegra_car 20>;
55 reset-names = "vi";
56 };
58 epp@540c0000 {
59 compatible = "nvidia,tegra20-epp";
60 reg = <0x540c0000 0x00040000>;
61 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
62 clocks = <&tegra_car TEGRA20_CLK_EPP>;
63 resets = <&tegra_car 19>;
64 reset-names = "epp";
65 };
67 isp@54100000 {
68 compatible = "nvidia,tegra20-isp";
69 reg = <0x54100000 0x00040000>;
70 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
71 clocks = <&tegra_car TEGRA20_CLK_ISP>;
72 resets = <&tegra_car 23>;
73 reset-names = "isp";
74 };
76 gr2d@54140000 {
77 compatible = "nvidia,tegra20-gr2d";
78 reg = <0x54140000 0x00040000>;
79 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
81 resets = <&tegra_car 21>;
82 reset-names = "2d";
83 };
85 gr3d@54180000 {
86 compatible = "nvidia,tegra20-gr3d";
87 reg = <0x54180000 0x00040000>;
88 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
89 resets = <&tegra_car 24>;
90 reset-names = "3d";
91 };
93 dc@54200000 {
94 compatible = "nvidia,tegra20-dc";
95 reg = <0x54200000 0x00040000>;
96 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
98 <&tegra_car TEGRA20_CLK_PLL_P>;
99 clock-names = "dc", "parent";
100 resets = <&tegra_car 27>;
101 reset-names = "dc";
103 nvidia,head = <0>;
105 rgb {
106 status = "disabled";
107 };
108 };
110 dc@54240000 {
111 compatible = "nvidia,tegra20-dc";
112 reg = <0x54240000 0x00040000>;
113 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
115 <&tegra_car TEGRA20_CLK_PLL_P>;
116 clock-names = "dc", "parent";
117 resets = <&tegra_car 26>;
118 reset-names = "dc";
120 nvidia,head = <1>;
122 rgb {
123 status = "disabled";
124 };
125 };
127 hdmi@54280000 {
128 compatible = "nvidia,tegra20-hdmi";
129 reg = <0x54280000 0x00040000>;
130 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
132 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
133 clock-names = "hdmi", "parent";
134 resets = <&tegra_car 51>;
135 reset-names = "hdmi";
136 status = "disabled";
137 };
139 tvo@542c0000 {
140 compatible = "nvidia,tegra20-tvo";
141 reg = <0x542c0000 0x00040000>;
142 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&tegra_car TEGRA20_CLK_TVO>;
144 status = "disabled";
145 };
147 dsi@54300000 {
148 compatible = "nvidia,tegra20-dsi";
149 reg = <0x54300000 0x00040000>;
150 clocks = <&tegra_car TEGRA20_CLK_DSI>;
151 resets = <&tegra_car 48>;
152 reset-names = "dsi";
153 status = "disabled";
154 };
155 };
157 timer@50040600 {
158 compatible = "arm,cortex-a9-twd-timer";
159 interrupt-parent = <&intc>;
160 reg = <0x50040600 0x20>;
161 interrupts = <GIC_PPI 13
162 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
163 clocks = <&tegra_car TEGRA20_CLK_TWD>;
164 };
166 intc: interrupt-controller@50041000 {
167 compatible = "arm,cortex-a9-gic";
168 reg = <0x50041000 0x1000
169 0x50040100 0x0100>;
170 interrupt-controller;
171 #interrupt-cells = <3>;
172 interrupt-parent = <&intc>;
173 };
175 cache-controller@50043000 {
176 compatible = "arm,pl310-cache";
177 reg = <0x50043000 0x1000>;
178 arm,data-latency = <5 5 2>;
179 arm,tag-latency = <4 4 2>;
180 cache-unified;
181 cache-level = <2>;
182 };
184 lic: interrupt-controller@60004000 {
185 compatible = "nvidia,tegra20-ictlr";
186 reg = <0x60004000 0x100>,
187 <0x60004100 0x50>,
188 <0x60004200 0x50>,
189 <0x60004300 0x50>;
190 interrupt-controller;
191 #interrupt-cells = <3>;
192 interrupt-parent = <&intc>;
193 };
195 timer@60005000 {
196 compatible = "nvidia,tegra20-timer";
197 reg = <0x60005000 0x60>;
198 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
203 };
205 tegra_car: clock@60006000 {
206 compatible = "nvidia,tegra20-car";
207 reg = <0x60006000 0x1000>;
208 #clock-cells = <1>;
209 #reset-cells = <1>;
210 };
212 flow-controller@60007000 {
213 compatible = "nvidia,tegra20-flowctrl";
214 reg = <0x60007000 0x1000>;
215 };
217 apbdma: dma@6000a000 {
218 compatible = "nvidia,tegra20-apbdma";
219 reg = <0x6000a000 0x1200>;
220 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
237 resets = <&tegra_car 34>;
238 reset-names = "dma";
239 #dma-cells = <1>;
240 };
242 ahb@6000c000 {
243 compatible = "nvidia,tegra20-ahb";
244 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
245 };
247 gpio: gpio@6000d000 {
248 compatible = "nvidia,tegra20-gpio";
249 reg = <0x6000d000 0x1000>;
250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
257 #gpio-cells = <2>;
258 gpio-controller;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 /*
262 gpio-ranges = <&pinmux 0 0 224>;
263 */
264 };
266 vde@6001a000 {
267 compatible = "nvidia,tegra20-vde";
268 reg = <0x6001a000 0x1000 /* Syntax Engine */
269 0x6001b000 0x1000 /* Video Bitstream Engine */
270 0x6001c000 0x100 /* Macroblock Engine */
271 0x6001c200 0x100 /* Post-processing Engine */
272 0x6001c400 0x100 /* Motion Compensation Engine */
273 0x6001c600 0x100 /* Transform Engine */
274 0x6001c800 0x100 /* Pixel prediction block */
275 0x6001ca00 0x100 /* Video DMA */
276 0x6001d800 0x300>; /* Video frame controls */
277 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
278 "tfe", "ppb", "vdma", "frameid";
279 iram = <&vde_pool>; /* IRAM region */
280 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
281 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
282 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
283 interrupt-names = "sync-token", "bsev", "sxe";
284 clocks = <&tegra_car TEGRA20_CLK_VDE>;
285 resets = <&tegra_car 61>;
286 };
288 apbmisc@70000800 {
289 compatible = "nvidia,tegra20-apbmisc";
290 reg = <0x70000800 0x64 /* Chip revision */
291 0x70000008 0x04>; /* Strapping options */
292 };
294 pinmux: pinmux@70000014 {
295 compatible = "nvidia,tegra20-pinmux";
296 reg = <0x70000014 0x10 /* Tri-state registers */
297 0x70000080 0x20 /* Mux registers */
298 0x700000a0 0x14 /* Pull-up/down registers */
299 0x70000868 0xa8>; /* Pad control registers */
300 };
302 das@70000c00 {
303 compatible = "nvidia,tegra20-das";
304 reg = <0x70000c00 0x80>;
305 };
307 tegra_ac97: ac97@70002000 {
308 compatible = "nvidia,tegra20-ac97";
309 reg = <0x70002000 0x200>;
310 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&tegra_car TEGRA20_CLK_AC97>;
312 resets = <&tegra_car 3>;
313 reset-names = "ac97";
314 dmas = <&apbdma 12>, <&apbdma 12>;
315 dma-names = "rx", "tx";
316 status = "disabled";
317 };
319 tegra_i2s1: i2s@70002800 {
320 compatible = "nvidia,tegra20-i2s";
321 reg = <0x70002800 0x200>;
322 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
324 resets = <&tegra_car 11>;
325 reset-names = "i2s";
326 dmas = <&apbdma 2>, <&apbdma 2>;
327 dma-names = "rx", "tx";
328 status = "disabled";
329 };
331 tegra_i2s2: i2s@70002a00 {
332 compatible = "nvidia,tegra20-i2s";
333 reg = <0x70002a00 0x200>;
334 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
336 resets = <&tegra_car 18>;
337 reset-names = "i2s";
338 dmas = <&apbdma 1>, <&apbdma 1>;
339 dma-names = "rx", "tx";
340 status = "disabled";
341 };
343 /*
344 * There are two serial driver i.e. 8250 based simple serial
345 * driver and APB DMA based serial driver for higher baudrate
346 * and performace. To enable the 8250 based driver, the compatible
347 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
348 * driver, the compatible is "nvidia,tegra20-hsuart".
349 */
350 uarta: serial@70006000 {
351 compatible = "nvidia,tegra20-uart";
352 reg = <0x70006000 0x40>;
353 reg-shift = <2>;
354 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
356 resets = <&tegra_car 6>;
357 reset-names = "serial";
358 dmas = <&apbdma 8>, <&apbdma 8>;
359 dma-names = "rx", "tx";
360 status = "disabled";
361 };
363 uartb: serial@70006040 {
364 compatible = "nvidia,tegra20-uart";
365 reg = <0x70006040 0x40>;
366 reg-shift = <2>;
367 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
369 resets = <&tegra_car 7>;
370 reset-names = "serial";
371 dmas = <&apbdma 9>, <&apbdma 9>;
372 dma-names = "rx", "tx";
373 status = "disabled";
374 };
376 uartc: serial@70006200 {
377 compatible = "nvidia,tegra20-uart";
378 reg = <0x70006200 0x100>;
379 reg-shift = <2>;
380 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
382 resets = <&tegra_car 55>;
383 reset-names = "serial";
384 dmas = <&apbdma 10>, <&apbdma 10>;
385 dma-names = "rx", "tx";
386 status = "disabled";
387 };
389 uartd: serial@70006300 {
390 compatible = "nvidia,tegra20-uart";
391 reg = <0x70006300 0x100>;
392 reg-shift = <2>;
393 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
395 resets = <&tegra_car 65>;
396 reset-names = "serial";
397 dmas = <&apbdma 19>, <&apbdma 19>;
398 dma-names = "rx", "tx";
399 status = "disabled";
400 };
402 uarte: serial@70006400 {
403 compatible = "nvidia,tegra20-uart";
404 reg = <0x70006400 0x100>;
405 reg-shift = <2>;
406 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
408 resets = <&tegra_car 66>;
409 reset-names = "serial";
410 dmas = <&apbdma 20>, <&apbdma 20>;
411 dma-names = "rx", "tx";
412 status = "disabled";
413 };
415 gmi@70009000 {
416 compatible = "nvidia,tegra20-gmi";
417 reg = <0x70009000 0x1000>;
418 #address-cells = <2>;
419 #size-cells = <1>;
420 ranges = <0 0 0xd0000000 0xfffffff>;
421 clocks = <&tegra_car TEGRA20_CLK_NOR>;
422 clock-names = "gmi";
423 resets = <&tegra_car 42>;
424 reset-names = "gmi";
425 status = "disabled";
426 };
428 pwm: pwm@7000a000 {
429 compatible = "nvidia,tegra20-pwm";
430 reg = <0x7000a000 0x100>;
431 #pwm-cells = <2>;
432 clocks = <&tegra_car TEGRA20_CLK_PWM>;
433 resets = <&tegra_car 17>;
434 reset-names = "pwm";
435 status = "disabled";
436 };
438 rtc@7000e000 {
439 compatible = "nvidia,tegra20-rtc";
440 reg = <0x7000e000 0x100>;
441 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&tegra_car TEGRA20_CLK_RTC>;
443 };
445 i2c@7000c000 {
446 compatible = "nvidia,tegra20-i2c";
447 reg = <0x7000c000 0x100>;
448 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
452 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
453 clock-names = "div-clk", "fast-clk";
454 resets = <&tegra_car 12>;
455 reset-names = "i2c";
456 dmas = <&apbdma 21>, <&apbdma 21>;
457 dma-names = "rx", "tx";
458 status = "disabled";
459 };
461 spi@7000c380 {
462 compatible = "nvidia,tegra20-sflash";
463 reg = <0x7000c380 0x80>;
464 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
465 #address-cells = <1>;
466 #size-cells = <0>;
467 clocks = <&tegra_car TEGRA20_CLK_SPI>;
468 resets = <&tegra_car 43>;
469 reset-names = "spi";
470 dmas = <&apbdma 11>, <&apbdma 11>;
471 dma-names = "rx", "tx";
472 status = "disabled";
473 };
475 i2c@7000c400 {
476 compatible = "nvidia,tegra20-i2c";
477 reg = <0x7000c400 0x100>;
478 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
482 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
483 clock-names = "div-clk", "fast-clk";
484 resets = <&tegra_car 54>;
485 reset-names = "i2c";
486 dmas = <&apbdma 22>, <&apbdma 22>;
487 dma-names = "rx", "tx";
488 status = "disabled";
489 };
491 i2c@7000c500 {
492 compatible = "nvidia,tegra20-i2c";
493 reg = <0x7000c500 0x100>;
494 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
495 #address-cells = <1>;
496 #size-cells = <0>;
497 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
498 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
499 clock-names = "div-clk", "fast-clk";
500 resets = <&tegra_car 67>;
501 reset-names = "i2c";
502 dmas = <&apbdma 23>, <&apbdma 23>;
503 dma-names = "rx", "tx";
504 status = "disabled";
505 };
507 i2c@7000d000 {
508 compatible = "nvidia,tegra20-i2c-dvc";
509 reg = <0x7000d000 0x200>;
510 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
511 #address-cells = <1>;
512 #size-cells = <0>;
513 clocks = <&tegra_car TEGRA20_CLK_DVC>,
514 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
515 clock-names = "div-clk", "fast-clk";
516 resets = <&tegra_car 47>;
517 reset-names = "i2c";
518 dmas = <&apbdma 24>, <&apbdma 24>;
519 dma-names = "rx", "tx";
520 status = "disabled";
521 };
523 spi@7000d400 {
524 compatible = "nvidia,tegra20-slink";
525 reg = <0x7000d400 0x200>;
526 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
528 #size-cells = <0>;
529 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
530 resets = <&tegra_car 41>;
531 reset-names = "spi";
532 dmas = <&apbdma 15>, <&apbdma 15>;
533 dma-names = "rx", "tx";
534 status = "disabled";
535 };
537 spi@7000d600 {
538 compatible = "nvidia,tegra20-slink";
539 reg = <0x7000d600 0x200>;
540 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
544 resets = <&tegra_car 44>;
545 reset-names = "spi";
546 dmas = <&apbdma 16>, <&apbdma 16>;
547 dma-names = "rx", "tx";
548 status = "disabled";
549 };
551 spi@7000d800 {
552 compatible = "nvidia,tegra20-slink";
553 reg = <0x7000d800 0x200>;
554 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
555 #address-cells = <1>;
556 #size-cells = <0>;
557 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
558 resets = <&tegra_car 46>;
559 reset-names = "spi";
560 dmas = <&apbdma 17>, <&apbdma 17>;
561 dma-names = "rx", "tx";
562 status = "disabled";
563 };
565 spi@7000da00 {
566 compatible = "nvidia,tegra20-slink";
567 reg = <0x7000da00 0x200>;
568 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
569 #address-cells = <1>;
570 #size-cells = <0>;
571 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
572 resets = <&tegra_car 68>;
573 reset-names = "spi";
574 dmas = <&apbdma 18>, <&apbdma 18>;
575 dma-names = "rx", "tx";
576 status = "disabled";
577 };
579 kbc@7000e200 {
580 compatible = "nvidia,tegra20-kbc";
581 reg = <0x7000e200 0x100>;
582 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&tegra_car TEGRA20_CLK_KBC>;
584 resets = <&tegra_car 36>;
585 reset-names = "kbc";
586 status = "disabled";
587 };
589 pmc@7000e400 {
590 compatible = "nvidia,tegra20-pmc";
591 reg = <0x7000e400 0x400>;
592 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
593 clock-names = "pclk", "clk32k_in";
594 };
596 memory-controller@7000f000 {
597 compatible = "nvidia,tegra20-mc";
598 reg = <0x7000f000 0x024
599 0x7000f03c 0x3c4>;
600 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
601 };
603 iommu@7000f024 {
604 compatible = "nvidia,tegra20-gart";
605 reg = <0x7000f024 0x00000018 /* controller registers */
606 0x58000000 0x02000000>; /* GART aperture */
607 };
609 memory-controller@7000f400 {
610 compatible = "nvidia,tegra20-emc";
611 reg = <0x7000f400 0x200>;
612 #address-cells = <1>;
613 #size-cells = <0>;
614 };
616 fuse@7000f800 {
617 compatible = "nvidia,tegra20-efuse";
618 reg = <0x7000f800 0x400>;
619 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
620 clock-names = "fuse";
621 resets = <&tegra_car 39>;
622 reset-names = "fuse";
623 };
625 pcie@80003000 {
626 compatible = "nvidia,tegra20-pcie";
627 device_type = "pci";
628 reg = <0x80003000 0x00000800 /* PADS registers */
629 0x80003800 0x00000200 /* AFI registers */
630 0x90000000 0x10000000>; /* configuration space */
631 reg-names = "pads", "afi", "cs";
632 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
633 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
634 interrupt-names = "intr", "msi";
636 #interrupt-cells = <1>;
637 interrupt-map-mask = <0 0 0 0>;
638 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
640 bus-range = <0x00 0xff>;
641 #address-cells = <3>;
642 #size-cells = <2>;
644 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
645 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
646 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
647 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
648 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
650 clocks = <&tegra_car TEGRA20_CLK_PEX>,
651 <&tegra_car TEGRA20_CLK_AFI>,
652 <&tegra_car TEGRA20_CLK_PLL_E>;
653 clock-names = "pex", "afi", "pll_e";
654 resets = <&tegra_car 70>,
655 <&tegra_car 72>,
656 <&tegra_car 74>;
657 reset-names = "pex", "afi", "pcie_x";
658 status = "disabled";
660 pci@1,0 {
661 device_type = "pci";
662 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
663 reg = <0x000800 0 0 0 0>;
664 bus-range = <0x00 0xff>;
665 status = "disabled";
667 #address-cells = <3>;
668 #size-cells = <2>;
669 ranges;
671 nvidia,num-lanes = <2>;
672 };
674 pci@2,0 {
675 device_type = "pci";
676 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
677 reg = <0x001000 0 0 0 0>;
678 bus-range = <0x00 0xff>;
679 status = "disabled";
681 #address-cells = <3>;
682 #size-cells = <2>;
683 ranges;
685 nvidia,num-lanes = <2>;
686 };
687 };
689 usb@c5000000 {
690 compatible = "nvidia,tegra20-ehci", "usb-ehci";
691 reg = <0xc5000000 0x4000>;
692 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
693 phy_type = "utmi";
694 nvidia,has-legacy-mode;
695 clocks = <&tegra_car TEGRA20_CLK_USBD>;
696 resets = <&tegra_car 22>;
697 reset-names = "usb";
698 nvidia,needs-double-reset;
699 nvidia,phy = <&phy1>;
700 status = "disabled";
701 };
703 phy1: usb-phy@c5000000 {
704 compatible = "nvidia,tegra20-usb-phy";
705 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
706 phy_type = "utmi";
707 clocks = <&tegra_car TEGRA20_CLK_USBD>,
708 <&tegra_car TEGRA20_CLK_PLL_U>,
709 <&tegra_car TEGRA20_CLK_CLK_M>,
710 <&tegra_car TEGRA20_CLK_USBD>;
711 clock-names = "reg", "pll_u", "timer", "utmi-pads";
712 resets = <&tegra_car 22>, <&tegra_car 22>;
713 reset-names = "usb", "utmi-pads";
714 nvidia,has-legacy-mode;
715 nvidia,hssync-start-delay = <9>;
716 nvidia,idle-wait-delay = <17>;
717 nvidia,elastic-limit = <16>;
718 nvidia,term-range-adj = <6>;
719 nvidia,xcvr-setup = <9>;
720 nvidia,xcvr-lsfslew = <1>;
721 nvidia,xcvr-lsrslew = <1>;
722 nvidia,has-utmi-pad-registers;
723 status = "disabled";
724 };
726 usb@c5004000 {
727 compatible = "nvidia,tegra20-ehci", "usb-ehci";
728 reg = <0xc5004000 0x4000>;
729 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
730 phy_type = "ulpi";
731 clocks = <&tegra_car TEGRA20_CLK_USB2>;
732 resets = <&tegra_car 58>;
733 reset-names = "usb";
734 nvidia,phy = <&phy2>;
735 status = "disabled";
736 };
738 phy2: usb-phy@c5004000 {
739 compatible = "nvidia,tegra20-usb-phy";
740 reg = <0xc5004000 0x4000>;
741 phy_type = "ulpi";
742 clocks = <&tegra_car TEGRA20_CLK_USB2>,
743 <&tegra_car TEGRA20_CLK_PLL_U>,
744 <&tegra_car TEGRA20_CLK_CDEV2>;
745 clock-names = "reg", "pll_u", "ulpi-link";
746 resets = <&tegra_car 58>, <&tegra_car 22>;
747 reset-names = "usb", "utmi-pads";
748 status = "disabled";
749 };
751 usb@c5008000 {
752 compatible = "nvidia,tegra20-ehci", "usb-ehci";
753 reg = <0xc5008000 0x4000>;
754 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
755 phy_type = "utmi";
756 clocks = <&tegra_car TEGRA20_CLK_USB3>;
757 resets = <&tegra_car 59>;
758 reset-names = "usb";
759 nvidia,phy = <&phy3>;
760 status = "disabled";
761 };
763 phy3: usb-phy@c5008000 {
764 compatible = "nvidia,tegra20-usb-phy";
765 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
766 phy_type = "utmi";
767 clocks = <&tegra_car TEGRA20_CLK_USB3>,
768 <&tegra_car TEGRA20_CLK_PLL_U>,
769 <&tegra_car TEGRA20_CLK_CLK_M>,
770 <&tegra_car TEGRA20_CLK_USBD>;
771 clock-names = "reg", "pll_u", "timer", "utmi-pads";
772 resets = <&tegra_car 59>, <&tegra_car 22>;
773 reset-names = "usb", "utmi-pads";
774 nvidia,hssync-start-delay = <9>;
775 nvidia,idle-wait-delay = <17>;
776 nvidia,elastic-limit = <16>;
777 nvidia,term-range-adj = <6>;
778 nvidia,xcvr-setup = <9>;
779 nvidia,xcvr-lsfslew = <2>;
780 nvidia,xcvr-lsrslew = <2>;
781 status = "disabled";
782 };
784 sdhci@c8000000 {
785 compatible = "nvidia,tegra20-sdhci";
786 reg = <0xc8000000 0x200>;
787 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
789 resets = <&tegra_car 14>;
790 reset-names = "sdhci";
791 status = "disabled";
792 };
794 sdhci@c8000200 {
795 compatible = "nvidia,tegra20-sdhci";
796 reg = <0xc8000200 0x200>;
797 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
799 resets = <&tegra_car 9>;
800 reset-names = "sdhci";
801 status = "disabled";
802 };
804 sdhci@c8000400 {
805 compatible = "nvidia,tegra20-sdhci";
806 reg = <0xc8000400 0x200>;
807 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
809 resets = <&tegra_car 69>;
810 reset-names = "sdhci";
811 status = "disabled";
812 };
814 sdhci@c8000600 {
815 compatible = "nvidia,tegra20-sdhci";
816 reg = <0xc8000600 0x200>;
817 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
819 resets = <&tegra_car 15>;
820 reset-names = "sdhci";
821 status = "disabled";
822 };
824 cpus {
825 #address-cells = <1>;
826 #size-cells = <0>;
828 cpu@0 {
829 device_type = "cpu";
830 compatible = "arm,cortex-a9";
831 reg = <0>;
832 };
834 cpu@1 {
835 device_type = "cpu";
836 compatible = "arm,cortex-a9";
837 reg = <1>;
838 };
839 };
841 pmu {
842 compatible = "arm,cortex-a9-pmu";
843 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
844 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
845 };
846 };