arch/arm/boot/dts/uniphier-ld4.dtsi

   1 /*
   2  * Device Tree Source for UniPhier LD4 SoC
   3  *
   4  * Copyright (C) 2015-2016 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  *
   7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   8  */
   9
  10 #include <dt-bindings/gpio/uniphier-gpio.h>
  11
  12 / {
  13         compatible = "socionext,uniphier-ld4";
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         reg = <0>;
  25                         enable-method = "psci";
  26                         next-level-cache = <&l2>;
  27                 };
  28         };
  29
  30         psci {
  31                 compatible = "arm,psci-0.2";
  32                 method = "smc";
  33         };
  34
  35         clocks {
  36                 refclk: ref {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <24576000>;
  40                 };
  41
  42                 arm_timer_clk: arm-timer {
  43                         #clock-cells = <0>;
  44                         compatible = "fixed-clock";
  45                         clock-frequency = <50000000>;
  46                 };
  47         };
  48
  49         soc {
  50                 compatible = "simple-bus";
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 ranges;
  54                 interrupt-parent = <&intc>;
  55
  56                 l2: l2-cache@500c0000 {
  57                         compatible = "socionext,uniphier-system-cache";
  58                         reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
  59                               <0x506c0000 0x400>;
  60                         interrupts = <0 174 4>, <0 175 4>;
  61                         cache-unified;
  62                         cache-size = <(512 * 1024)>;
  63                         cache-sets = <256>;
  64                         cache-line-size = <128>;
  65                         cache-level = <2>;
  66                 };
  67
  68                 serial0: serial@54006800 {
  69                         compatible = "socionext,uniphier-uart";
  70                         status = "disabled";
  71                         reg = <0x54006800 0x40>;
  72                         interrupts = <0 33 4>;
  73                         pinctrl-names = "default";
  74                         pinctrl-0 = <&pinctrl_uart0>;
  75                         clocks = <&peri_clk 0>;
  76                         resets = <&peri_rst 0>;
  77                 };
  78
  79                 serial1: serial@54006900 {
  80                         compatible = "socionext,uniphier-uart";
  81                         status = "disabled";
  82                         reg = <0x54006900 0x40>;
  83                         interrupts = <0 35 4>;
  84                         pinctrl-names = "default";
  85                         pinctrl-0 = <&pinctrl_uart1>;
  86                         clocks = <&peri_clk 1>;
  87                         resets = <&peri_rst 1>;
  88                 };
  89
  90                 serial2: serial@54006a00 {
  91                         compatible = "socionext,uniphier-uart";
  92                         status = "disabled";
  93                         reg = <0x54006a00 0x40>;
  94                         interrupts = <0 37 4>;
  95                         pinctrl-names = "default";
  96                         pinctrl-0 = <&pinctrl_uart2>;
  97                         clocks = <&peri_clk 2>;
  98                         resets = <&peri_rst 2>;
  99                 };
 100
 101                 serial3: serial@54006b00 {
 102                         compatible = "socionext,uniphier-uart";
 103                         status = "disabled";
 104                         reg = <0x54006b00 0x40>;
 105                         interrupts = <0 29 4>;
 106                         pinctrl-names = "default";
 107                         pinctrl-0 = <&pinctrl_uart3>;
 108                         clocks = <&peri_clk 3>;
 109                         resets = <&peri_rst 3>;
 110                 };
 111
 112                 gpio: gpio@55000000 {
 113                         compatible = "socionext,uniphier-gpio";
 114                         reg = <0x55000000 0x200>;
 115                         interrupt-parent = <&aidet>;
 116                         interrupt-controller;
 117                         #interrupt-cells = <2>;
 118                         gpio-controller;
 119                         #gpio-cells = <2>;
 120                         gpio-ranges = <&pinctrl 0 0 0>;
 121                         gpio-ranges-group-names = "gpio_range";
 122                         ngpios = <136>;
 123                         socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
 124                 };
 125
 126                 i2c0: i2c@58400000 {
 127                         compatible = "socionext,uniphier-i2c";
 128                         status = "disabled";
 129                         reg = <0x58400000 0x40>;
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         interrupts = <0 41 1>;
 133                         pinctrl-names = "default";
 134                         pinctrl-0 = <&pinctrl_i2c0>;
 135                         clocks = <&peri_clk 4>;
 136                         resets = <&peri_rst 4>;
 137                         clock-frequency = <100000>;
 138                 };
 139
 140                 i2c1: i2c@58480000 {
 141                         compatible = "socionext,uniphier-i2c";
 142                         status = "disabled";
 143                         reg = <0x58480000 0x40>;
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         interrupts = <0 42 1>;
 147                         pinctrl-names = "default";
 148                         pinctrl-0 = <&pinctrl_i2c1>;
 149                         clocks = <&peri_clk 5>;
 150                         resets = <&peri_rst 5>;
 151                         clock-frequency = <100000>;
 152                 };
 153
 154                 /* chip-internal connection for DMD */
 155                 i2c2: i2c@58500000 {
 156                         compatible = "socionext,uniphier-i2c";
 157                         reg = <0x58500000 0x40>;
 158                         #address-cells = <1>;
 159                         #size-cells = <0>;
 160                         interrupts = <0 43 1>;
 161                         pinctrl-names = "default";
 162                         pinctrl-0 = <&pinctrl_i2c2>;
 163                         clocks = <&peri_clk 6>;
 164                         resets = <&peri_rst 6>;
 165                         clock-frequency = <400000>;
 166                 };
 167
 168                 i2c3: i2c@58580000 {
 169                         compatible = "socionext,uniphier-i2c";
 170                         status = "disabled";
 171                         reg = <0x58580000 0x40>;
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         interrupts = <0 44 1>;
 175                         pinctrl-names = "default";
 176                         pinctrl-0 = <&pinctrl_i2c3>;
 177                         clocks = <&peri_clk 7>;
 178                         resets = <&peri_rst 7>;
 179                         clock-frequency = <100000>;
 180                 };
 181
 182                 system_bus: system-bus@58c00000 {
 183                         compatible = "socionext,uniphier-system-bus";
 184                         status = "disabled";
 185                         reg = <0x58c00000 0x400>;
 186                         #address-cells = <2>;
 187                         #size-cells = <1>;
 188                         pinctrl-names = "default";
 189                         pinctrl-0 = <&pinctrl_system_bus>;
 190                 };
 191
 192                 smpctrl@59801000 {
 193                         compatible = "socionext,uniphier-smpctrl";
 194                         reg = <0x59801000 0x400>;
 195                 };
 196
 197                 mioctrl@59810000 {
 198                         compatible = "socionext,uniphier-ld4-mioctrl",
 199                                      "simple-mfd", "syscon";
 200                         reg = <0x59810000 0x800>;
 201
 202                         mio_clk: clock {
 203                                 compatible = "socionext,uniphier-ld4-mio-clock";
 204                                 #clock-cells = <1>;
 205                         };
 206
 207                         mio_rst: reset {
 208                                 compatible = "socionext,uniphier-ld4-mio-reset";
 209                                 #reset-cells = <1>;
 210                         };
 211                 };
 212
 213                 perictrl@59820000 {
 214                         compatible = "socionext,uniphier-ld4-perictrl",
 215                                      "simple-mfd", "syscon";
 216                         reg = <0x59820000 0x200>;
 217
 218                         peri_clk: clock {
 219                                 compatible = "socionext,uniphier-ld4-peri-clock";
 220                                 #clock-cells = <1>;
 221                         };
 222
 223                         peri_rst: reset {
 224                                 compatible = "socionext,uniphier-ld4-peri-reset";
 225                                 #reset-cells = <1>;
 226                         };
 227                 };
 228
 229                 usb0: usb@5a800100 {
 230                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 231                         status = "disabled";
 232                         reg = <0x5a800100 0x100>;
 233                         interrupts = <0 80 4>;
 234                         pinctrl-names = "default";
 235                         pinctrl-0 = <&pinctrl_usb0>;
 236                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 237                                  <&mio_clk 12>;
 238                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 239                                  <&mio_rst 12>;
 240                         has-transaction-translator;
 241                 };
 242
 243                 usb1: usb@5a810100 {
 244                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 245                         status = "disabled";
 246                         reg = <0x5a810100 0x100>;
 247                         interrupts = <0 81 4>;
 248                         pinctrl-names = "default";
 249                         pinctrl-0 = <&pinctrl_usb1>;
 250                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 251                                  <&mio_clk 13>;
 252                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 253                                  <&mio_rst 13>;
 254                         has-transaction-translator;
 255                 };
 256
 257                 usb2: usb@5a820100 {
 258                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 259                         status = "disabled";
 260                         reg = <0x5a820100 0x100>;
 261                         interrupts = <0 82 4>;
 262                         pinctrl-names = "default";
 263                         pinctrl-0 = <&pinctrl_usb2>;
 264                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 265                                  <&mio_clk 14>;
 266                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 267                                  <&mio_rst 14>;
 268                         has-transaction-translator;
 269                 };
 270
 271                 soc-glue@5f800000 {
 272                         compatible = "socionext,uniphier-ld4-soc-glue",
 273                                      "simple-mfd", "syscon";
 274                         reg = <0x5f800000 0x2000>;
 275
 276                         pinctrl: pinctrl {
 277                                 compatible = "socionext,uniphier-ld4-pinctrl";
 278                         };
 279                 };
 280
 281                 soc-glue@5f900000 {
 282                         compatible = "socionext,uniphier-ld4-soc-glue-debug",
 283                                      "simple-mfd";
 284                         #address-cells = <1>;
 285                         #size-cells = <1>;
 286                         ranges = <0 0x5f900000 0x2000>;
 287
 288                         efuse@100 {
 289                                 compatible = "socionext,uniphier-efuse";
 290                                 reg = <0x100 0x28>;
 291                         };
 292
 293                         efuse@130 {
 294                                 compatible = "socionext,uniphier-efuse";
 295                                 reg = <0x130 0x8>;
 296                         };
 297                 };
 298
 299                 timer@60000200 {
 300                         compatible = "arm,cortex-a9-global-timer";
 301                         reg = <0x60000200 0x20>;
 302                         interrupts = <1 11 0x104>;
 303                         clocks = <&arm_timer_clk>;
 304                 };
 305
 306                 timer@60000600 {
 307                         compatible = "arm,cortex-a9-twd-timer";
 308                         reg = <0x60000600 0x20>;
 309                         interrupts = <1 13 0x104>;
 310                         clocks = <&arm_timer_clk>;
 311                 };
 312
 313                 intc: interrupt-controller@60001000 {
 314                         compatible = "arm,cortex-a9-gic";
 315                         reg = <0x60001000 0x1000>,
 316                               <0x60000100 0x100>;
 317                         #interrupt-cells = <3>;
 318                         interrupt-controller;
 319                 };
 320
 321                 aidet: aidet@61830000 {
 322                         compatible = "socionext,uniphier-ld4-aidet";
 323                         reg = <0x61830000 0x200>;
 324                         interrupt-controller;
 325                         #interrupt-cells = <2>;
 326                 };
 327
 328                 sysctrl@61840000 {
 329                         compatible = "socionext,uniphier-ld4-sysctrl",
 330                                      "simple-mfd", "syscon";
 331                         reg = <0x61840000 0x10000>;
 332
 333                         sys_clk: clock {
 334                                 compatible = "socionext,uniphier-ld4-clock";
 335                                 #clock-cells = <1>;
 336                         };
 337
 338                         sys_rst: reset {
 339                                 compatible = "socionext,uniphier-ld4-reset";
 340                                 #reset-cells = <1>;
 341                         };
 342                 };
 343
 344                 nand: nand@68000000 {
 345                         compatible = "socionext,uniphier-denali-nand-v5a";
 346                         status = "disabled";
 347                         reg-names = "nand_data", "denali_reg";
 348                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 349                         interrupts = <0 65 4>;
 350                         pinctrl-names = "default";
 351                         pinctrl-0 = <&pinctrl_nand2cs>;
 352                         clocks = <&sys_clk 2>;
 353                         resets = <&sys_rst 2>;
 354                 };
 355         };
 356 };
 357
 358 #include "uniphier-pinctrl.dtsi"