| blob | 6cb3c2a52bafe5f0db8a0018b35e88998ed90f01 |
1 /*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 *
7 * Copyright (c) 2016 Endless Computers, Inc.
8 * Author: Carlo Caione <carlo@endlessm.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This library is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This library is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
49 #include <dt-bindings/gpio/gpio.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/interrupt-controller/arm-gic.h>
53 / {
54 interrupt-parent = <&gic>;
55 #address-cells = <2>;
56 #size-cells = <2>;
58 reserved-memory {
59 #address-cells = <2>;
60 #size-cells = <2>;
61 ranges;
63 /* 16 MiB reserved for Hardware ROM Firmware */
64 hwrom_reserved: hwrom@0 {
65 reg = <0x0 0x0 0x0 0x1000000>;
66 no-map;
67 };
69 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
70 secmon_reserved: secmon@10000000 {
71 reg = <0x0 0x10000000 0x0 0x200000>;
72 no-map;
73 };
75 linux,cma {
76 compatible = "shared-dma-pool";
77 reusable;
78 size = <0x0 0xbc00000>;
79 alignment = <0x0 0x400000>;
80 linux,cma-default;
81 };
82 };
84 cpus {
85 #address-cells = <0x2>;
86 #size-cells = <0x0>;
88 cpu0: cpu@0 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a53", "arm,armv8";
91 reg = <0x0 0x0>;
92 enable-method = "psci";
93 next-level-cache = <&l2>;
94 clocks = <&scpi_dvfs 0>;
95 };
97 cpu1: cpu@1 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a53", "arm,armv8";
100 reg = <0x0 0x1>;
101 enable-method = "psci";
102 next-level-cache = <&l2>;
103 clocks = <&scpi_dvfs 0>;
104 };
106 cpu2: cpu@2 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a53", "arm,armv8";
109 reg = <0x0 0x2>;
110 enable-method = "psci";
111 next-level-cache = <&l2>;
112 clocks = <&scpi_dvfs 0>;
113 };
115 cpu3: cpu@3 {
116 device_type = "cpu";
117 compatible = "arm,cortex-a53", "arm,armv8";
118 reg = <0x0 0x3>;
119 enable-method = "psci";
120 next-level-cache = <&l2>;
121 clocks = <&scpi_dvfs 0>;
122 };
124 l2: l2-cache0 {
125 compatible = "cache";
126 };
127 };
129 arm-pmu {
130 compatible = "arm,cortex-a53-pmu";
131 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
136 };
138 psci {
139 compatible = "arm,psci-0.2";
140 method = "smc";
141 };
143 timer {
144 compatible = "arm,armv8-timer";
145 interrupts = <GIC_PPI 13
146 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
147 <GIC_PPI 14
148 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
149 <GIC_PPI 11
150 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
151 <GIC_PPI 10
152 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
153 };
155 xtal: xtal-clk {
156 compatible = "fixed-clock";
157 clock-frequency = <24000000>;
158 clock-output-names = "xtal";
159 #clock-cells = <0>;
160 };
162 firmware {
163 sm: secure-monitor {
164 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
165 };
166 };
168 efuse: efuse {
169 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
170 #address-cells = <1>;
171 #size-cells = <1>;
173 sn: sn@14 {
174 reg = <0x14 0x10>;
175 };
177 eth_mac: eth_mac@34 {
178 reg = <0x34 0x10>;
179 };
181 bid: bid@46 {
182 reg = <0x46 0x30>;
183 };
184 };
186 scpi {
187 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
188 mboxes = <&mailbox 1 &mailbox 2>;
189 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
191 scpi_clocks: clocks {
192 compatible = "arm,scpi-clocks";
194 scpi_dvfs: scpi_clocks@0 {
195 compatible = "arm,scpi-dvfs-clocks";
196 #clock-cells = <1>;
197 clock-indices = <0>;
198 clock-output-names = "vcpu";
199 };
200 };
202 scpi_sensors: sensors {
203 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
204 #thermal-sensor-cells = <1>;
205 };
206 };
208 soc {
209 compatible = "simple-bus";
210 #address-cells = <2>;
211 #size-cells = <2>;
212 ranges;
214 cbus: bus@c1100000 {
215 compatible = "simple-bus";
216 reg = <0x0 0xc1100000 0x0 0x100000>;
217 #address-cells = <2>;
218 #size-cells = <2>;
219 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
221 gpio_intc: interrupt-controller@9880 {
222 compatible = "amlogic,meson-gpio-intc";
223 reg = <0x0 0x9880 0x0 0x10>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
226 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
227 status = "disabled";
228 };
230 reset: reset-controller@4404 {
231 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
232 reg = <0x0 0x04404 0x0 0x9c>;
233 #reset-cells = <1>;
234 };
236 uart_A: serial@84c0 {
237 compatible = "amlogic,meson-gx-uart";
238 reg = <0x0 0x84c0 0x0 0x14>;
239 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
240 status = "disabled";
241 };
243 uart_B: serial@84dc {
244 compatible = "amlogic,meson-gx-uart";
245 reg = <0x0 0x84dc 0x0 0x14>;
246 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
247 status = "disabled";
248 };
250 i2c_A: i2c@8500 {
251 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
252 reg = <0x0 0x08500 0x0 0x20>;
253 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 status = "disabled";
257 };
259 pwm_ab: pwm@8550 {
260 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
261 reg = <0x0 0x08550 0x0 0x10>;
262 #pwm-cells = <3>;
263 status = "disabled";
264 };
266 pwm_cd: pwm@8650 {
267 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
268 reg = <0x0 0x08650 0x0 0x10>;
269 #pwm-cells = <3>;
270 status = "disabled";
271 };
273 saradc: adc@8680 {
274 compatible = "amlogic,meson-saradc";
275 reg = <0x0 0x8680 0x0 0x34>;
276 #io-channel-cells = <1>;
277 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
278 status = "disabled";
279 };
281 pwm_ef: pwm@86c0 {
282 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
283 reg = <0x0 0x086c0 0x0 0x10>;
284 #pwm-cells = <3>;
285 status = "disabled";
286 };
288 uart_C: serial@8700 {
289 compatible = "amlogic,meson-gx-uart";
290 reg = <0x0 0x8700 0x0 0x14>;
291 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
292 status = "disabled";
293 };
295 i2c_B: i2c@87c0 {
296 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
297 reg = <0x0 0x087c0 0x0 0x20>;
298 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 status = "disabled";
302 };
304 i2c_C: i2c@87e0 {
305 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
306 reg = <0x0 0x087e0 0x0 0x20>;
307 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
308 #address-cells = <1>;
309 #size-cells = <0>;
310 status = "disabled";
311 };
313 spicc: spi@8d80 {
314 compatible = "amlogic,meson-gx-spicc";
315 reg = <0x0 0x08d80 0x0 0x80>;
316 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
317 #address-cells = <1>;
318 #size-cells = <0>;
319 status = "disabled";
320 };
322 spifc: spi@8c80 {
323 compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
324 reg = <0x0 0x08c80 0x0 0x80>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 status = "disabled";
328 };
330 watchdog@98d0 {
331 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
332 reg = <0x0 0x098d0 0x0 0x10>;
333 clocks = <&xtal>;
334 };
335 };
337 gic: interrupt-controller@c4301000 {
338 compatible = "arm,gic-400";
339 reg = <0x0 0xc4301000 0 0x1000>,
340 <0x0 0xc4302000 0 0x2000>,
341 <0x0 0xc4304000 0 0x2000>,
342 <0x0 0xc4306000 0 0x2000>;
343 interrupt-controller;
344 interrupts = <GIC_PPI 9
345 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
346 #interrupt-cells = <3>;
347 #address-cells = <0>;
348 };
350 sram: sram@c8000000 {
351 compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
352 reg = <0x0 0xc8000000 0x0 0x14000>;
354 #address-cells = <1>;
355 #size-cells = <1>;
356 ranges = <0 0x0 0xc8000000 0x14000>;
358 cpu_scp_lpri: scp-shmem@0 {
359 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
360 reg = <0x13000 0x400>;
361 };
363 cpu_scp_hpri: scp-shmem@200 {
364 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
365 reg = <0x13400 0x400>;
366 };
367 };
369 aobus: bus@c8100000 {
370 compatible = "simple-bus";
371 reg = <0x0 0xc8100000 0x0 0x100000>;
372 #address-cells = <2>;
373 #size-cells = <2>;
374 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
376 sysctrl_AO: sys-ctrl@0 {
377 compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
378 reg = <0x0 0x0 0x0 0x100>;
380 pwrc_vpu: power-controller-vpu {
381 compatible = "amlogic,meson-gx-pwrc-vpu";
382 #power-domain-cells = <0>;
383 amlogic,hhi-sysctrl = <&sysctrl>;
384 };
386 clkc_AO: clock-controller {
387 compatible = "amlogic,meson-gx-aoclkc";
388 #clock-cells = <1>;
389 #reset-cells = <1>;
390 };
391 };
393 cec_AO: cec@100 {
394 compatible = "amlogic,meson-gx-ao-cec";
395 reg = <0x0 0x00100 0x0 0x14>;
396 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
397 };
399 sec_AO: ao-secure@140 {
400 compatible = "amlogic,meson-gx-ao-secure", "syscon";
401 reg = <0x0 0x140 0x0 0x140>;
402 amlogic,has-chip-id;
403 };
405 uart_AO: serial@4c0 {
406 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
407 reg = <0x0 0x004c0 0x0 0x14>;
408 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
409 status = "disabled";
410 };
412 uart_AO_B: serial@4e0 {
413 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
414 reg = <0x0 0x004e0 0x0 0x14>;
415 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
416 status = "disabled";
417 };
419 i2c_AO: i2c@500 {
420 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
421 reg = <0x0 0x500 0x0 0x20>;
422 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
423 #address-cells = <1>;
424 #size-cells = <0>;
425 status = "disabled";
426 };
428 pwm_AO_ab: pwm@550 {
429 compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
430 reg = <0x0 0x00550 0x0 0x10>;
431 #pwm-cells = <3>;
432 status = "disabled";
433 };
435 ir: ir@580 {
436 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
437 reg = <0x0 0x00580 0x0 0x40>;
438 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
439 status = "disabled";
440 };
441 };
443 periphs: periphs@c8834000 {
444 compatible = "simple-bus";
445 reg = <0x0 0xc8834000 0x0 0x2000>;
446 #address-cells = <2>;
447 #size-cells = <2>;
448 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
450 hwrng: rng {
451 compatible = "amlogic,meson-rng";
452 reg = <0x0 0x0 0x0 0x4>;
453 };
454 };
456 hiubus: bus@c883c000 {
457 compatible = "simple-bus";
458 reg = <0x0 0xc883c000 0x0 0x2000>;
459 #address-cells = <2>;
460 #size-cells = <2>;
461 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
463 sysctrl: system-controller@0 {
464 compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
465 reg = <0 0 0 0x400>;
466 };
468 mailbox: mailbox@404 {
469 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
470 reg = <0 0x404 0 0x4c>;
471 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
472 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
473 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
474 #mbox-cells = <1>;
475 };
476 };
478 ethmac: ethernet@c9410000 {
479 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
480 reg = <0x0 0xc9410000 0x0 0x10000
481 0x0 0xc8834540 0x0 0x4>;
482 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
483 interrupt-names = "macirq";
484 status = "disabled";
485 };
487 apb: apb@d0000000 {
488 compatible = "simple-bus";
489 reg = <0x0 0xd0000000 0x0 0x200000>;
490 #address-cells = <2>;
491 #size-cells = <2>;
492 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
494 sd_emmc_a: mmc@70000 {
495 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
496 reg = <0x0 0x70000 0x0 0x2000>;
497 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
498 status = "disabled";
499 };
501 sd_emmc_b: mmc@72000 {
502 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
503 reg = <0x0 0x72000 0x0 0x2000>;
504 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
505 status = "disabled";
506 };
508 sd_emmc_c: mmc@74000 {
509 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
510 reg = <0x0 0x74000 0x0 0x2000>;
511 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
512 status = "disabled";
513 };
514 };
516 vpu: vpu@d0100000 {
517 compatible = "amlogic,meson-gx-vpu";
518 reg = <0x0 0xd0100000 0x0 0x100000>,
519 <0x0 0xc883c000 0x0 0x1000>,
520 <0x0 0xc8838000 0x0 0x1000>;
521 reg-names = "vpu", "hhi", "dmc";
522 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
523 #address-cells = <1>;
524 #size-cells = <0>;
526 /* CVBS VDAC output port */
527 cvbs_vdac_port: port@0 {
528 reg = <0>;
529 };
531 /* HDMI-TX output port */
532 hdmi_tx_port: port@1 {
533 reg = <1>;
535 hdmi_tx_out: endpoint {
536 remote-endpoint = <&hdmi_tx_in>;
537 };
538 };
539 };
541 hdmi_tx: hdmi-tx@c883a000 {
542 compatible = "amlogic,meson-gx-dw-hdmi";
543 reg = <0x0 0xc883a000 0x0 0x1c>;
544 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 status = "disabled";
549 /* VPU VENC Input */
550 hdmi_tx_venc_port: port@0 {
551 reg = <0>;
553 hdmi_tx_in: endpoint {
554 remote-endpoint = <&hdmi_tx_out>;
555 };
556 };
558 /* TMDS Output */
559 hdmi_tx_tmds_port: port@1 {
560 reg = <1>;
561 };
562 };
563 };
564 };