| blob | 3ac87e53b3da0fdc0c41bd967ac731f5d98d6efb |
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
7 *
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
10 *
11 * Most of this originates from head_64.S and thus has the same
12 * copyright history.
13 *
14 */
16 #include <asm/hw_irq.h>
17 #include <asm/exception-64s.h>
18 #include <asm/ptrace.h>
19 #include <asm/cpuidle.h>
20 #include <asm/head-64.h>
22 /*
23 * There are a few constraints to be concerned with.
24 * - Real mode exceptions code/data must be located at their physical location.
25 * - Virtual mode exceptions must be mapped at their 0xc000... location.
26 * - Fixed location code must not call directly beyond the __end_interrupts
27 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
28 * must be used.
29 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
30 * virtual 0xc00...
31 * - Conditional branch targets must be within +/-32K of caller.
32 *
33 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
34 * therefore don't have to run in physically located code or rfid to
35 * virtual mode kernel code. However on relocatable kernels they do have
36 * to branch to KERNELBASE offset because the rest of the kernel (outside
37 * the exception vectors) may be located elsewhere.
38 *
39 * Virtual exceptions correspond with physical, except their entry points
40 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
41 * offset applied. Virtual exceptions are enabled with the Alternate
42 * Interrupt Location (AIL) bit set in the LPCR. However this does not
43 * guarantee they will be delivered virtually. Some conditions (see the ISA)
44 * cause exceptions to be delivered in real mode.
45 *
46 * It's impossible to receive interrupts below 0x300 via AIL.
47 *
48 * KVM: None of the virtual exceptions are from the guest. Anything that
49 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
50 *
51 *
52 * We layout physical memory as follows:
53 * 0x0000 - 0x00ff : Secondary processor spin code
54 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
55 * 0x1900 - 0x3fff : Real mode trampolines
56 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
57 * 0x5900 - 0x6fff : Relon mode trampolines
58 * 0x7000 - 0x7fff : FWNMI data area
59 * 0x8000 - .... : Common interrupt handlers, remaining early
60 * setup code, rest of kernel.
61 *
62 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
63 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
64 * vectors there.
65 */
66 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
67 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
68 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
69 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
70 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
71 /*
72 * Data area reserved for FWNMI option.
73 * This address (0x7000) is fixed by the RPA.
74 * pseries and powernv need to keep the whole page from
75 * 0x7000 to 0x8000 free for use by the firmware
76 */
77 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
78 OPEN_TEXT_SECTION(0x8000)
79 #else
80 OPEN_TEXT_SECTION(0x7000)
81 #endif
83 USE_FIXED_SECTION(real_vectors)
85 /*
86 * This is the start of the interrupt handlers for pSeries
87 * This code runs with relocation off.
88 * Code from here to __end_interrupts gets copied down to real
89 * address 0x100 when we are running a relocatable kernel.
90 * Therefore any relative branches in this section must only
91 * branch to labels in this section.
92 */
93 .globl __start_interrupts
94 __start_interrupts:
96 /* No virt vectors corresponding with 0x0..0x100 */
97 EXC_VIRT_NONE(0x4000, 0x100)
100 #ifdef CONFIG_PPC_P7_NAP
101 /*
102 * If running native on arch 2.06 or later, check if we are waking up
103 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
104 * bits 46:47. A non-0 value indicates that we are coming from a power
105 * saving state. The idle wakeup handler initially runs in real mode,
106 * but we branch to the 0xc000... address so we can turn on relocation
107 * with mtmsr.
108 */
109 #define IDLETEST(n) \
110 BEGIN_FTR_SECTION ; \
111 mfspr r10,SPRN_SRR1 ; \
112 rlwinm. r10,r10,47-31,30,31 ; \
113 beq- 1f ; \
114 cmpwi cr3,r10,2 ; \
115 BRANCH_TO_C000(r10, system_reset_idle_common) ; \
116 1: \
117 KVMTEST_PR(n) ; \
118 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
119 #else
120 #define IDLETEST NOTEST
121 #endif
123 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
124 SET_SCRATCH0(r13)
125 /*
126 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
127 * being used, so a nested NMI exception would corrupt it.
128 */
129 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
130 IDLETEST, 0x100)
132 EXC_REAL_END(system_reset, 0x100, 0x100)
133 EXC_VIRT_NONE(0x4100, 0x100)
134 TRAMP_KVM(PACA_EXNMI, 0x100)
136 #ifdef CONFIG_PPC_P7_NAP
137 EXC_COMMON_BEGIN(system_reset_idle_common)
138 mfspr r12,SPRN_SRR1
139 b pnv_powersave_wakeup
140 #endif
142 EXC_COMMON_BEGIN(system_reset_common)
143 /*
144 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
145 * to recover, but nested NMI will notice in_nmi and not recover
146 * because of the use of the NMI stack. in_nmi reentrancy is tested in
147 * system_reset_exception.
148 */
149 lhz r10,PACA_IN_NMI(r13)
150 addi r10,r10,1
151 sth r10,PACA_IN_NMI(r13)
152 li r10,MSR_RI
153 mtmsrd r10,1
155 mr r10,r1
156 ld r1,PACA_NMI_EMERG_SP(r13)
157 subi r1,r1,INT_FRAME_SIZE
158 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100,
159 system_reset, system_reset_exception,
160 ADD_NVGPRS;ADD_RECONCILE)
162 /*
163 * The stack is no longer in use, decrement in_nmi.
164 */
165 lhz r10,PACA_IN_NMI(r13)
166 subi r10,r10,1
167 sth r10,PACA_IN_NMI(r13)
169 b ret_from_except
171 #ifdef CONFIG_PPC_PSERIES
172 /*
173 * Vectors for the FWNMI option. Share common code.
174 */
175 TRAMP_REAL_BEGIN(system_reset_fwnmi)
176 SET_SCRATCH0(r13) /* save r13 */
177 /* See comment at system_reset exception */
178 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common,
179 EXC_STD, NOTEST, 0x100)
180 #endif /* CONFIG_PPC_PSERIES */
183 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
184 /* This is moved out of line as it can be patched by FW, but
185 * some code path might still want to branch into the original
186 * vector
187 */
188 SET_SCRATCH0(r13) /* save r13 */
189 EXCEPTION_PROLOG_0(PACA_EXMC)
190 BEGIN_FTR_SECTION
191 b machine_check_powernv_early
192 FTR_SECTION_ELSE
193 b machine_check_pSeries_0
194 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
195 EXC_REAL_END(machine_check, 0x200, 0x100)
196 EXC_VIRT_NONE(0x4200, 0x100)
197 TRAMP_REAL_BEGIN(machine_check_powernv_early)
198 BEGIN_FTR_SECTION
199 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
200 /*
201 * Register contents:
202 * R13 = PACA
203 * R9 = CR
204 * Original R9 to R13 is saved on PACA_EXMC
205 *
206 * Switch to mc_emergency stack and handle re-entrancy (we limit
207 * the nested MCE upto level 4 to avoid stack overflow).
208 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
209 *
210 * We use paca->in_mce to check whether this is the first entry or
211 * nested machine check. We increment paca->in_mce to track nested
212 * machine checks.
213 *
214 * If this is the first entry then set stack pointer to
215 * paca->mc_emergency_sp, otherwise r1 is already pointing to
216 * stack frame on mc_emergency stack.
217 *
218 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
219 * checkstop if we get another machine check exception before we do
220 * rfid with MSR_ME=1.
221 *
222 * This interrupt can wake directly from idle. If that is the case,
223 * the machine check is handled then the idle wakeup code is called
224 * to restore state. In that case, the POWER9 DD1 idle PACA workaround
225 * is not applied in the early machine check code, which will cause
226 * bugs.
227 */
228 mr r11,r1 /* Save r1 */
229 lhz r10,PACA_IN_MCE(r13)
230 cmpwi r10,0 /* Are we in nested machine check */
231 bne 0f /* Yes, we are. */
232 /* First machine check entry */
233 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
234 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
235 addi r10,r10,1 /* increment paca->in_mce */
236 sth r10,PACA_IN_MCE(r13)
237 /* Limit nested MCE to level 4 to avoid stack overflow */
238 cmpwi r10,MAX_MCE_DEPTH
239 bgt 2f /* Check if we hit limit of 4 */
240 std r11,GPR1(r1) /* Save r1 on the stack. */
241 std r11,0(r1) /* make stack chain pointer */
242 mfspr r11,SPRN_SRR0 /* Save SRR0 */
243 std r11,_NIP(r1)
244 mfspr r11,SPRN_SRR1 /* Save SRR1 */
245 std r11,_MSR(r1)
246 mfspr r11,SPRN_DAR /* Save DAR */
247 std r11,_DAR(r1)
248 mfspr r11,SPRN_DSISR /* Save DSISR */
249 std r11,_DSISR(r1)
250 std r9,_CCR(r1) /* Save CR in stackframe */
251 /* Save r9 through r13 from EXMC save area to stack frame. */
252 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
253 mfmsr r11 /* get MSR value */
254 ori r11,r11,MSR_ME /* turn on ME bit */
255 ori r11,r11,MSR_RI /* turn on RI bit */
256 LOAD_HANDLER(r12, machine_check_handle_early)
257 1: mtspr SPRN_SRR0,r12
258 mtspr SPRN_SRR1,r11
259 RFI_TO_KERNEL
260 b . /* prevent speculative execution */
261 2:
262 /* Stack overflow. Stay on emergency stack and panic.
263 * Keep the ME bit off while panic-ing, so that if we hit
264 * another machine check we checkstop.
265 */
266 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
267 ld r11,PACAKMSR(r13)
268 LOAD_HANDLER(r12, unrecover_mce)
269 li r10,MSR_ME
270 andc r11,r11,r10 /* Turn off MSR_ME */
271 b 1b
272 b . /* prevent speculative execution */
273 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
275 TRAMP_REAL_BEGIN(machine_check_pSeries)
276 .globl machine_check_fwnmi
277 machine_check_fwnmi:
278 SET_SCRATCH0(r13) /* save r13 */
279 EXCEPTION_PROLOG_0(PACA_EXMC)
280 machine_check_pSeries_0:
281 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
282 /*
283 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
284 * nested machine check corrupts it. machine_check_common enables
285 * MSR_RI.
286 */
287 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD)
289 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
291 EXC_COMMON_BEGIN(machine_check_common)
292 /*
293 * Machine check is different because we use a different
294 * save area: PACA_EXMC instead of PACA_EXGEN.
295 */
296 mfspr r10,SPRN_DAR
297 std r10,PACA_EXMC+EX_DAR(r13)
298 mfspr r10,SPRN_DSISR
299 stw r10,PACA_EXMC+EX_DSISR(r13)
300 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
301 FINISH_NAP
302 RECONCILE_IRQ_STATE(r10, r11)
303 ld r3,PACA_EXMC+EX_DAR(r13)
304 lwz r4,PACA_EXMC+EX_DSISR(r13)
305 /* Enable MSR_RI when finished with PACA_EXMC */
306 li r10,MSR_RI
307 mtmsrd r10,1
308 std r3,_DAR(r1)
309 std r4,_DSISR(r1)
310 bl save_nvgprs
311 addi r3,r1,STACK_FRAME_OVERHEAD
312 bl machine_check_exception
313 b ret_from_except
315 #define MACHINE_CHECK_HANDLER_WINDUP \
316 /* Clear MSR_RI before setting SRR0 and SRR1. */\
317 li r0,MSR_RI; \
318 mfmsr r9; /* get MSR value */ \
319 andc r9,r9,r0; \
320 mtmsrd r9,1; /* Clear MSR_RI */ \
321 /* Move original SRR0 and SRR1 into the respective regs */ \
322 ld r9,_MSR(r1); \
323 mtspr SPRN_SRR1,r9; \
324 ld r3,_NIP(r1); \
325 mtspr SPRN_SRR0,r3; \
326 ld r9,_CTR(r1); \
327 mtctr r9; \
328 ld r9,_XER(r1); \
329 mtxer r9; \
330 ld r9,_LINK(r1); \
331 mtlr r9; \
332 REST_GPR(0, r1); \
333 REST_8GPRS(2, r1); \
334 REST_GPR(10, r1); \
335 ld r11,_CCR(r1); \
336 mtcr r11; \
337 /* Decrement paca->in_mce. */ \
338 lhz r12,PACA_IN_MCE(r13); \
339 subi r12,r12,1; \
340 sth r12,PACA_IN_MCE(r13); \
341 REST_GPR(11, r1); \
342 REST_2GPRS(12, r1); \
343 /* restore original r1. */ \
344 ld r1,GPR1(r1)
346 #ifdef CONFIG_PPC_P7_NAP
347 /*
348 * This is an idle wakeup. Low level machine check has already been
349 * done. Queue the event then call the idle code to do the wake up.
350 */
351 EXC_COMMON_BEGIN(machine_check_idle_common)
352 bl machine_check_queue_event
354 /*
355 * We have not used any non-volatile GPRs here, and as a rule
356 * most exception code including machine check does not.
357 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
358 * wakeup will restore volatile registers.
359 *
360 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
361 *
362 * Then decrement MCE nesting after finishing with the stack.
363 */
364 ld r3,_MSR(r1)
366 lhz r11,PACA_IN_MCE(r13)
367 subi r11,r11,1
368 sth r11,PACA_IN_MCE(r13)
370 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */
371 /* Recoverability could be improved by reducing the use of SRR1. */
372 li r11,0
373 mtmsrd r11,1
375 b pnv_powersave_wakeup_mce
376 #endif
377 /*
378 * Handle machine check early in real mode. We come here with
379 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
380 */
381 EXC_COMMON_BEGIN(machine_check_handle_early)
382 std r0,GPR0(r1) /* Save r0 */
383 EXCEPTION_PROLOG_COMMON_3(0x200)
384 bl save_nvgprs
385 addi r3,r1,STACK_FRAME_OVERHEAD
386 bl machine_check_early
387 std r3,RESULT(r1) /* Save result */
388 ld r12,_MSR(r1)
390 #ifdef CONFIG_PPC_P7_NAP
391 /*
392 * Check if thread was in power saving mode. We come here when any
393 * of the following is true:
394 * a. thread wasn't in power saving mode
395 * b. thread was in power saving mode with no state loss,
396 * supervisor state loss or hypervisor state loss.
397 *
398 * Go back to nap/sleep/winkle mode again if (b) is true.
399 */
400 BEGIN_FTR_SECTION
401 rlwinm. r11,r12,47-31,30,31
402 bne machine_check_idle_common
403 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
404 #endif
406 /*
407 * Check if we are coming from hypervisor userspace. If yes then we
408 * continue in host kernel in V mode to deliver the MC event.
409 */
410 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
411 beq 5f
412 andi. r11,r12,MSR_PR /* See if coming from user. */
413 bne 9f /* continue in V mode if we are. */
415 5:
416 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
417 /*
418 * We are coming from kernel context. Check if we are coming from
419 * guest. if yes, then we can continue. We will fall through
420 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
421 */
422 lbz r11,HSTATE_IN_GUEST(r13)
423 cmpwi r11,0 /* Check if coming from guest */
424 bne 9f /* continue if we are. */
425 #endif
426 /*
427 * At this point we are not sure about what context we come from.
428 * Queue up the MCE event and return from the interrupt.
429 * But before that, check if this is an un-recoverable exception.
430 * If yes, then stay on emergency stack and panic.
431 */
432 andi. r11,r12,MSR_RI
433 bne 2f
434 1: mfspr r11,SPRN_SRR0
435 LOAD_HANDLER(r10,unrecover_mce)
436 mtspr SPRN_SRR0,r10
437 ld r10,PACAKMSR(r13)
438 /*
439 * We are going down. But there are chances that we might get hit by
440 * another MCE during panic path and we may run into unstable state
441 * with no way out. Hence, turn ME bit off while going down, so that
442 * when another MCE is hit during panic path, system will checkstop
443 * and hypervisor will get restarted cleanly by SP.
444 */
445 li r3,MSR_ME
446 andc r10,r10,r3 /* Turn off MSR_ME */
447 mtspr SPRN_SRR1,r10
448 RFI_TO_KERNEL
449 b .
450 2:
451 /*
452 * Check if we have successfully handled/recovered from error, if not
453 * then stay on emergency stack and panic.
454 */
455 ld r3,RESULT(r1) /* Load result */
456 cmpdi r3,0 /* see if we handled MCE successfully */
458 beq 1b /* if !handled then panic */
459 /*
460 * Return from MC interrupt.
461 * Queue up the MCE event so that we can log it later, while
462 * returning from kernel or opal call.
463 */
464 bl machine_check_queue_event
465 MACHINE_CHECK_HANDLER_WINDUP
466 RFI_TO_USER_OR_KERNEL
467 9:
468 /* Deliver the machine check to host kernel in V mode. */
469 MACHINE_CHECK_HANDLER_WINDUP
470 b machine_check_pSeries
472 EXC_COMMON_BEGIN(unrecover_mce)
473 /* Invoke machine_check_exception to print MCE event and panic. */
474 addi r3,r1,STACK_FRAME_OVERHEAD
475 bl machine_check_exception
476 /*
477 * We will not reach here. Even if we did, there is no way out. Call
478 * unrecoverable_exception and die.
479 */
480 1: addi r3,r1,STACK_FRAME_OVERHEAD
481 bl unrecoverable_exception
482 b 1b
485 EXC_REAL(data_access, 0x300, 0x80)
486 EXC_VIRT(data_access, 0x4300, 0x80, 0x300)
487 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
489 EXC_COMMON_BEGIN(data_access_common)
490 /*
491 * Here r13 points to the paca, r9 contains the saved CR,
492 * SRR0 and SRR1 are saved in r11 and r12,
493 * r9 - r13 are saved in paca->exgen.
494 */
495 mfspr r10,SPRN_DAR
496 std r10,PACA_EXGEN+EX_DAR(r13)
497 mfspr r10,SPRN_DSISR
498 stw r10,PACA_EXGEN+EX_DSISR(r13)
499 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
500 RECONCILE_IRQ_STATE(r10, r11)
501 ld r12,_MSR(r1)
502 ld r3,PACA_EXGEN+EX_DAR(r13)
503 lwz r4,PACA_EXGEN+EX_DSISR(r13)
504 li r5,0x300
505 std r3,_DAR(r1)
506 std r4,_DSISR(r1)
507 BEGIN_MMU_FTR_SECTION
508 b do_hash_page /* Try to handle as hpte fault */
509 MMU_FTR_SECTION_ELSE
510 b handle_page_fault
511 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
514 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
515 SET_SCRATCH0(r13)
516 EXCEPTION_PROLOG_0(PACA_EXSLB)
517 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
518 mr r12,r3 /* save r3 */
519 mfspr r3,SPRN_DAR
520 mfspr r11,SPRN_SRR1
521 crset 4*cr6+eq
522 BRANCH_TO_COMMON(r10, slb_miss_common)
523 EXC_REAL_END(data_access_slb, 0x380, 0x80)
525 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
526 SET_SCRATCH0(r13)
527 EXCEPTION_PROLOG_0(PACA_EXSLB)
528 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
529 mr r12,r3 /* save r3 */
530 mfspr r3,SPRN_DAR
531 mfspr r11,SPRN_SRR1
532 crset 4*cr6+eq
533 BRANCH_TO_COMMON(r10, slb_miss_common)
534 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
535 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
538 EXC_REAL(instruction_access, 0x400, 0x80)
539 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
540 TRAMP_KVM(PACA_EXGEN, 0x400)
542 EXC_COMMON_BEGIN(instruction_access_common)
543 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
544 RECONCILE_IRQ_STATE(r10, r11)
545 ld r12,_MSR(r1)
546 ld r3,_NIP(r1)
547 andis. r4,r12,DSISR_SRR1_MATCH_64S@h
548 li r5,0x400
549 std r3,_DAR(r1)
550 std r4,_DSISR(r1)
551 BEGIN_MMU_FTR_SECTION
552 b do_hash_page /* Try to handle as hpte fault */
553 MMU_FTR_SECTION_ELSE
554 b handle_page_fault
555 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
558 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
559 SET_SCRATCH0(r13)
560 EXCEPTION_PROLOG_0(PACA_EXSLB)
561 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
562 mr r12,r3 /* save r3 */
563 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
564 mfspr r11,SPRN_SRR1
565 crclr 4*cr6+eq
566 BRANCH_TO_COMMON(r10, slb_miss_common)
567 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
569 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
570 SET_SCRATCH0(r13)
571 EXCEPTION_PROLOG_0(PACA_EXSLB)
572 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
573 mr r12,r3 /* save r3 */
574 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
575 mfspr r11,SPRN_SRR1
576 crclr 4*cr6+eq
577 BRANCH_TO_COMMON(r10, slb_miss_common)
578 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
579 TRAMP_KVM(PACA_EXSLB, 0x480)
582 /*
583 * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as
584 * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled.
585 */
586 EXC_COMMON_BEGIN(slb_miss_common)
587 /*
588 * r13 points to the PACA, r9 contains the saved CR,
589 * r12 contains the saved r3,
590 * r11 contain the saved SRR1, SRR0 is still ready for return
591 * r3 has the faulting address
592 * r9 - r13 are saved in paca->exslb.
593 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
594 * We assume we aren't going to take any exceptions during this
595 * procedure.
596 */
597 mflr r10
598 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
599 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
601 andi. r9,r11,MSR_PR // Check for exception from userspace
602 cmpdi cr4,r9,MSR_PR // And save the result in CR4 for later
604 /*
605 * Test MSR_RI before calling slb_allocate_realmode, because the
606 * MSR in r11 gets clobbered. However we still want to allocate
607 * SLB in case MSR_RI=0, to minimise the risk of getting stuck in
608 * recursive SLB faults. So use cr5 for this, which is preserved.
609 */
610 andi. r11,r11,MSR_RI /* check for unrecoverable exception */
611 cmpdi cr5,r11,MSR_RI
613 crset 4*cr0+eq
614 #ifdef CONFIG_PPC_BOOK3S_64
615 BEGIN_MMU_FTR_SECTION
616 bl slb_allocate
617 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
618 #endif
620 ld r10,PACA_EXSLB+EX_LR(r13)
621 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
622 mtlr r10
624 beq- 8f /* if bad address, make full stack frame */
626 bne- cr5,2f /* if unrecoverable exception, oops */
628 /* All done -- return from exception. */
630 bne cr4,1f /* returning to kernel */
632 .machine push
633 .machine "power4"
634 mtcrf 0x80,r9
635 mtcrf 0x08,r9 /* MSR[PR] indication is in cr4 */
636 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */
637 mtcrf 0x02,r9 /* I/D indication is in cr6 */
638 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
639 .machine pop
641 RESTORE_CTR(r9, PACA_EXSLB)
642 RESTORE_PPR_PACA(PACA_EXSLB, r9)
643 mr r3,r12
644 ld r9,PACA_EXSLB+EX_R9(r13)
645 ld r10,PACA_EXSLB+EX_R10(r13)
646 ld r11,PACA_EXSLB+EX_R11(r13)
647 ld r12,PACA_EXSLB+EX_R12(r13)
648 ld r13,PACA_EXSLB+EX_R13(r13)
649 RFI_TO_USER
650 b . /* prevent speculative execution */
651 1:
652 .machine push
653 .machine "power4"
654 mtcrf 0x80,r9
655 mtcrf 0x08,r9 /* MSR[PR] indication is in cr4 */
656 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */
657 mtcrf 0x02,r9 /* I/D indication is in cr6 */
658 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
659 .machine pop
661 RESTORE_CTR(r9, PACA_EXSLB)
662 RESTORE_PPR_PACA(PACA_EXSLB, r9)
663 mr r3,r12
664 ld r9,PACA_EXSLB+EX_R9(r13)
665 ld r10,PACA_EXSLB+EX_R10(r13)
666 ld r11,PACA_EXSLB+EX_R11(r13)
667 ld r12,PACA_EXSLB+EX_R12(r13)
668 ld r13,PACA_EXSLB+EX_R13(r13)
669 RFI_TO_KERNEL
670 b . /* prevent speculative execution */
673 2: std r3,PACA_EXSLB+EX_DAR(r13)
674 mr r3,r12
675 mfspr r11,SPRN_SRR0
676 mfspr r12,SPRN_SRR1
677 LOAD_HANDLER(r10,unrecov_slb)
678 mtspr SPRN_SRR0,r10
679 ld r10,PACAKMSR(r13)
680 mtspr SPRN_SRR1,r10
681 RFI_TO_KERNEL
682 b .
684 8: std r3,PACA_EXSLB+EX_DAR(r13)
685 mr r3,r12
686 mfspr r11,SPRN_SRR0
687 mfspr r12,SPRN_SRR1
688 LOAD_HANDLER(r10,bad_addr_slb)
689 mtspr SPRN_SRR0,r10
690 ld r10,PACAKMSR(r13)
691 mtspr SPRN_SRR1,r10
692 RFI_TO_KERNEL
693 b .
695 EXC_COMMON_BEGIN(unrecov_slb)
696 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
697 RECONCILE_IRQ_STATE(r10, r11)
698 bl save_nvgprs
699 1: addi r3,r1,STACK_FRAME_OVERHEAD
700 bl unrecoverable_exception
701 b 1b
703 EXC_COMMON_BEGIN(bad_addr_slb)
704 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
705 RECONCILE_IRQ_STATE(r10, r11)
706 ld r3, PACA_EXSLB+EX_DAR(r13)
707 std r3, _DAR(r1)
708 beq cr6, 2f
709 li r10, 0x480 /* fix trap number for I-SLB miss */
710 std r10, _TRAP(r1)
711 2: bl save_nvgprs
712 addi r3, r1, STACK_FRAME_OVERHEAD
713 bl slb_miss_bad_addr
714 b ret_from_except
716 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
717 .globl hardware_interrupt_hv;
718 hardware_interrupt_hv:
719 BEGIN_FTR_SECTION
720 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
721 EXC_HV, SOFTEN_TEST_HV,
722 IRQS_DISABLED)
723 FTR_SECTION_ELSE
724 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
725 EXC_STD, SOFTEN_TEST_PR,
726 IRQS_DISABLED)
727 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
728 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
730 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
731 .globl hardware_interrupt_relon_hv;
732 hardware_interrupt_relon_hv:
733 BEGIN_FTR_SECTION
734 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
735 EXC_HV, SOFTEN_TEST_HV,
736 IRQS_DISABLED)
737 FTR_SECTION_ELSE
738 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
739 EXC_STD, SOFTEN_TEST_PR,
740 IRQS_DISABLED)
741 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
742 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
744 TRAMP_KVM(PACA_EXGEN, 0x500)
745 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
746 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
749 EXC_REAL(alignment, 0x600, 0x100)
750 EXC_VIRT(alignment, 0x4600, 0x100, 0x600)
751 TRAMP_KVM(PACA_EXGEN, 0x600)
752 EXC_COMMON_BEGIN(alignment_common)
753 mfspr r10,SPRN_DAR
754 std r10,PACA_EXGEN+EX_DAR(r13)
755 mfspr r10,SPRN_DSISR
756 stw r10,PACA_EXGEN+EX_DSISR(r13)
757 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
758 ld r3,PACA_EXGEN+EX_DAR(r13)
759 lwz r4,PACA_EXGEN+EX_DSISR(r13)
760 std r3,_DAR(r1)
761 std r4,_DSISR(r1)
762 bl save_nvgprs
763 RECONCILE_IRQ_STATE(r10, r11)
764 addi r3,r1,STACK_FRAME_OVERHEAD
765 bl alignment_exception
766 b ret_from_except
769 EXC_REAL(program_check, 0x700, 0x100)
770 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
771 TRAMP_KVM(PACA_EXGEN, 0x700)
772 EXC_COMMON_BEGIN(program_check_common)
773 /*
774 * It's possible to receive a TM Bad Thing type program check with
775 * userspace register values (in particular r1), but with SRR1 reporting
776 * that we came from the kernel. Normally that would confuse the bad
777 * stack logic, and we would report a bad kernel stack pointer. Instead
778 * we switch to the emergency stack if we're taking a TM Bad Thing from
779 * the kernel.
780 */
781 li r10,MSR_PR /* Build a mask of MSR_PR .. */
782 oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */
783 and r10,r10,r12 /* Mask SRR1 with that. */
784 srdi r10,r10,8 /* Shift it so we can compare */
785 cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */
786 bne 1f /* If != go to normal path. */
788 /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */
789 andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */
790 /* 3 in EXCEPTION_PROLOG_COMMON */
791 mr r10,r1 /* Save r1 */
792 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
793 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
794 b 3f /* Jump into the macro !! */
795 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
796 bl save_nvgprs
797 RECONCILE_IRQ_STATE(r10, r11)
798 addi r3,r1,STACK_FRAME_OVERHEAD
799 bl program_check_exception
800 b ret_from_except
803 EXC_REAL(fp_unavailable, 0x800, 0x100)
804 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
805 TRAMP_KVM(PACA_EXGEN, 0x800)
806 EXC_COMMON_BEGIN(fp_unavailable_common)
807 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
808 bne 1f /* if from user, just load it up */
809 bl save_nvgprs
810 RECONCILE_IRQ_STATE(r10, r11)
811 addi r3,r1,STACK_FRAME_OVERHEAD
812 bl kernel_fp_unavailable_exception
813 BUG_OPCODE
814 1:
815 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
816 BEGIN_FTR_SECTION
817 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
818 * transaction), go do TM stuff
819 */
820 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
821 bne- 2f
822 END_FTR_SECTION_IFSET(CPU_FTR_TM)
823 #endif
824 bl load_up_fpu
825 b fast_exception_return
826 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
827 2: /* User process was in a transaction */
828 bl save_nvgprs
829 RECONCILE_IRQ_STATE(r10, r11)
830 addi r3,r1,STACK_FRAME_OVERHEAD
831 bl fp_unavailable_tm
832 b ret_from_except
833 #endif
836 EXC_REAL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED)
837 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED)
838 TRAMP_KVM(PACA_EXGEN, 0x900)
839 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
842 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
843 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
844 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
845 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
848 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED)
849 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED)
850 TRAMP_KVM(PACA_EXGEN, 0xa00)
851 #ifdef CONFIG_PPC_DOORBELL
852 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
853 #else
854 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
855 #endif
858 EXC_REAL(trap_0b, 0xb00, 0x100)
859 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
860 TRAMP_KVM(PACA_EXGEN, 0xb00)
861 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
863 /*
864 * system call / hypercall (0xc00, 0x4c00)
865 *
866 * The system call exception is invoked with "sc 0" and does not alter HV bit.
867 * There is support for kernel code to invoke system calls but there are no
868 * in-tree users.
869 *
870 * The hypercall is invoked with "sc 1" and sets HV=1.
871 *
872 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
873 * 0x4c00 virtual mode.
874 *
875 * Call convention:
876 *
877 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
878 *
879 * For hypercalls, the register convention is as follows:
880 * r0 volatile
881 * r1-2 nonvolatile
882 * r3 volatile parameter and return value for status
883 * r4-r10 volatile input and output value
884 * r11 volatile hypercall number and output value
885 * r12 volatile input and output value
886 * r13-r31 nonvolatile
887 * LR nonvolatile
888 * CTR volatile
889 * XER volatile
890 * CR0-1 CR5-7 volatile
891 * CR2-4 nonvolatile
892 * Other registers nonvolatile
893 *
894 * The intersection of volatile registers that don't contain possible
895 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
896 * without saving, though xer is not a good idea to use, as hardware may
897 * interpret some bits so it may be costly to change them.
898 */
899 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
900 /*
901 * There is a little bit of juggling to get syscall and hcall
902 * working well. Save r13 in ctr to avoid using SPRG scratch
903 * register.
904 *
905 * Userspace syscalls have already saved the PPR, hcalls must save
906 * it before setting HMT_MEDIUM.
907 */
908 #define SYSCALL_KVMTEST \
909 mtctr r13; \
910 GET_PACA(r13); \
911 std r10,PACA_EXGEN+EX_R10(r13); \
912 KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \
913 HMT_MEDIUM; \
914 mfctr r9;
916 #else
917 #define SYSCALL_KVMTEST \
918 HMT_MEDIUM; \
919 mr r9,r13; \
920 GET_PACA(r13);
921 #endif
923 #define LOAD_SYSCALL_HANDLER(reg) \
924 __LOAD_HANDLER(reg, system_call_common)
926 /*
927 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9,
928 * and HMT_MEDIUM.
929 */
930 #define SYSCALL_REAL \
931 mfspr r11,SPRN_SRR0 ; \
932 mfspr r12,SPRN_SRR1 ; \
933 LOAD_SYSCALL_HANDLER(r10) ; \
934 mtspr SPRN_SRR0,r10 ; \
935 ld r10,PACAKMSR(r13) ; \
936 mtspr SPRN_SRR1,r10 ; \
937 RFI_TO_KERNEL ; \
938 b . ; /* prevent speculative execution */
940 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
941 #define SYSCALL_FASTENDIAN_TEST \
942 BEGIN_FTR_SECTION \
943 cmpdi r0,0x1ebe ; \
944 beq- 1f ; \
945 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
947 #define SYSCALL_FASTENDIAN \
948 /* Fast LE/BE switch system call */ \
949 1: mfspr r12,SPRN_SRR1 ; \
950 xori r12,r12,MSR_LE ; \
951 mtspr SPRN_SRR1,r12 ; \
952 mr r13,r9 ; \
953 RFI_TO_USER ; /* return to userspace */ \
954 b . ; /* prevent speculative execution */
955 #else
956 #define SYSCALL_FASTENDIAN_TEST
957 #define SYSCALL_FASTENDIAN
958 #endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */
960 #if defined(CONFIG_RELOCATABLE)
961 /*
962 * We can't branch directly so we do it via the CTR which
963 * is volatile across system calls.
964 */
965 #define SYSCALL_VIRT \
966 LOAD_SYSCALL_HANDLER(r10) ; \
967 mtctr r10 ; \
968 mfspr r11,SPRN_SRR0 ; \
969 mfspr r12,SPRN_SRR1 ; \
970 li r10,MSR_RI ; \
971 mtmsrd r10,1 ; \
972 bctr ;
973 #else
974 /* We can branch directly */
975 #define SYSCALL_VIRT \
976 mfspr r11,SPRN_SRR0 ; \
977 mfspr r12,SPRN_SRR1 ; \
978 li r10,MSR_RI ; \
979 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
980 b system_call_common ;
981 #endif
983 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
984 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
985 SYSCALL_FASTENDIAN_TEST
986 SYSCALL_REAL
987 SYSCALL_FASTENDIAN
988 EXC_REAL_END(system_call, 0xc00, 0x100)
990 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
991 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
992 SYSCALL_FASTENDIAN_TEST
993 SYSCALL_VIRT
994 SYSCALL_FASTENDIAN
995 EXC_VIRT_END(system_call, 0x4c00, 0x100)
997 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
998 /*
999 * This is a hcall, so register convention is as above, with these
1000 * differences:
1001 * r13 = PACA
1002 * ctr = orig r13
1003 * orig r10 saved in PACA
1004 */
1005 TRAMP_KVM_BEGIN(do_kvm_0xc00)
1006 /*
1007 * Save the PPR (on systems that support it) before changing to
1008 * HMT_MEDIUM. That allows the KVM code to save that value into the
1009 * guest state (it is the guest's PPR value).
1010 */
1011 OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR)
1012 HMT_MEDIUM
1013 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR)
1014 mfctr r10
1015 SET_SCRATCH0(r10)
1016 std r9,PACA_EXGEN+EX_R9(r13)
1017 mfcr r9
1018 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00)
1019 #endif
1022 EXC_REAL(single_step, 0xd00, 0x100)
1023 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
1024 TRAMP_KVM(PACA_EXGEN, 0xd00)
1025 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
1027 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
1028 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
1029 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
1030 EXC_COMMON_BEGIN(h_data_storage_common)
1031 mfspr r10,SPRN_HDAR
1032 std r10,PACA_EXGEN+EX_DAR(r13)
1033 mfspr r10,SPRN_HDSISR
1034 stw r10,PACA_EXGEN+EX_DSISR(r13)
1035 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
1036 bl save_nvgprs
1037 RECONCILE_IRQ_STATE(r10, r11)
1038 addi r3,r1,STACK_FRAME_OVERHEAD
1039 bl unknown_exception
1040 b ret_from_except
1043 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
1044 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
1045 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1046 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1049 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
1050 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
1051 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1052 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1055 /*
1056 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1057 * first, and then eventaully from there to the trampoline to get into virtual
1058 * mode.
1059 */
1060 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
1061 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED)
1062 EXC_VIRT_NONE(0x4e60, 0x20)
1063 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1064 TRAMP_REAL_BEGIN(hmi_exception_early)
1065 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1066 mr r10,r1 /* Save r1 */
1067 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
1068 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1069 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1070 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
1071 EXCEPTION_PROLOG_COMMON_1()
1072 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1073 EXCEPTION_PROLOG_COMMON_3(0xe60)
1074 addi r3,r1,STACK_FRAME_OVERHEAD
1075 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */
1076 cmpdi cr0,r3,0
1078 /* Windup the stack. */
1079 /* Move original HSRR0 and HSRR1 into the respective regs */
1080 ld r9,_MSR(r1)
1081 mtspr SPRN_HSRR1,r9
1082 ld r3,_NIP(r1)
1083 mtspr SPRN_HSRR0,r3
1084 ld r9,_CTR(r1)
1085 mtctr r9
1086 ld r9,_XER(r1)
1087 mtxer r9
1088 ld r9,_LINK(r1)
1089 mtlr r9
1090 REST_GPR(0, r1)
1091 REST_8GPRS(2, r1)
1092 REST_GPR(10, r1)
1093 ld r11,_CCR(r1)
1094 REST_2GPRS(12, r1)
1095 bne 1f
1096 mtcr r11
1097 REST_GPR(11, r1)
1098 ld r1,GPR1(r1)
1099 HRFI_TO_USER_OR_KERNEL
1101 1: mtcr r11
1102 REST_GPR(11, r1)
1103 ld r1,GPR1(r1)
1105 /*
1106 * Go to virtual mode and pull the HMI event information from
1107 * firmware.
1108 */
1109 .globl hmi_exception_after_realmode
1110 hmi_exception_after_realmode:
1111 SET_SCRATCH0(r13)
1112 EXCEPTION_PROLOG_0(PACA_EXGEN)
1113 b tramp_real_hmi_exception
1115 EXC_COMMON_BEGIN(hmi_exception_common)
1116 EXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception,
1117 ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON)
1119 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED)
1120 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED)
1121 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1122 #ifdef CONFIG_PPC_DOORBELL
1123 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1124 #else
1125 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1126 #endif
1129 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED)
1130 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED)
1131 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1132 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1135 EXC_REAL_NONE(0xec0, 0x20)
1136 EXC_VIRT_NONE(0x4ec0, 0x20)
1137 EXC_REAL_NONE(0xee0, 0x20)
1138 EXC_VIRT_NONE(0x4ee0, 0x20)
1141 EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED)
1142 EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED)
1143 TRAMP_KVM(PACA_EXGEN, 0xf00)
1144 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1147 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1148 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1149 TRAMP_KVM(PACA_EXGEN, 0xf20)
1150 EXC_COMMON_BEGIN(altivec_unavailable_common)
1151 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1152 #ifdef CONFIG_ALTIVEC
1153 BEGIN_FTR_SECTION
1154 beq 1f
1155 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1156 BEGIN_FTR_SECTION_NESTED(69)
1157 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1158 * transaction), go do TM stuff
1159 */
1160 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1161 bne- 2f
1162 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1163 #endif
1164 bl load_up_altivec
1165 b fast_exception_return
1166 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1167 2: /* User process was in a transaction */
1168 bl save_nvgprs
1169 RECONCILE_IRQ_STATE(r10, r11)
1170 addi r3,r1,STACK_FRAME_OVERHEAD
1171 bl altivec_unavailable_tm
1172 b ret_from_except
1173 #endif
1174 1:
1175 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1176 #endif
1177 bl save_nvgprs
1178 RECONCILE_IRQ_STATE(r10, r11)
1179 addi r3,r1,STACK_FRAME_OVERHEAD
1180 bl altivec_unavailable_exception
1181 b ret_from_except
1184 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1185 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1186 TRAMP_KVM(PACA_EXGEN, 0xf40)
1187 EXC_COMMON_BEGIN(vsx_unavailable_common)
1188 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1189 #ifdef CONFIG_VSX
1190 BEGIN_FTR_SECTION
1191 beq 1f
1192 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1193 BEGIN_FTR_SECTION_NESTED(69)
1194 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1195 * transaction), go do TM stuff
1196 */
1197 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1198 bne- 2f
1199 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1200 #endif
1201 b load_up_vsx
1202 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1203 2: /* User process was in a transaction */
1204 bl save_nvgprs
1205 RECONCILE_IRQ_STATE(r10, r11)
1206 addi r3,r1,STACK_FRAME_OVERHEAD
1207 bl vsx_unavailable_tm
1208 b ret_from_except
1209 #endif
1210 1:
1211 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1212 #endif
1213 bl save_nvgprs
1214 RECONCILE_IRQ_STATE(r10, r11)
1215 addi r3,r1,STACK_FRAME_OVERHEAD
1216 bl vsx_unavailable_exception
1217 b ret_from_except
1220 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1221 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1222 TRAMP_KVM(PACA_EXGEN, 0xf60)
1223 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1226 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1227 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1228 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1229 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1232 EXC_REAL_NONE(0xfa0, 0x20)
1233 EXC_VIRT_NONE(0x4fa0, 0x20)
1234 EXC_REAL_NONE(0xfc0, 0x20)
1235 EXC_VIRT_NONE(0x4fc0, 0x20)
1236 EXC_REAL_NONE(0xfe0, 0x20)
1237 EXC_VIRT_NONE(0x4fe0, 0x20)
1239 EXC_REAL_NONE(0x1000, 0x100)
1240 EXC_VIRT_NONE(0x5000, 0x100)
1241 EXC_REAL_NONE(0x1100, 0x100)
1242 EXC_VIRT_NONE(0x5100, 0x100)
1244 #ifdef CONFIG_CBE_RAS
1245 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1246 EXC_VIRT_NONE(0x5200, 0x100)
1247 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1248 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1249 #else /* CONFIG_CBE_RAS */
1250 EXC_REAL_NONE(0x1200, 0x100)
1251 EXC_VIRT_NONE(0x5200, 0x100)
1252 #endif
1255 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1256 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1257 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1258 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1260 EXC_REAL_NONE(0x1400, 0x100)
1261 EXC_VIRT_NONE(0x5400, 0x100)
1263 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1264 mtspr SPRN_SPRG_HSCRATCH0,r13
1265 EXCEPTION_PROLOG_0(PACA_EXGEN)
1266 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1268 #ifdef CONFIG_PPC_DENORMALISATION
1269 mfspr r10,SPRN_HSRR1
1270 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1271 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1272 addi r11,r11,-4 /* HSRR0 is next instruction */
1273 bne+ denorm_assist
1274 #endif
1276 KVMTEST_PR(0x1500)
1277 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1278 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1280 #ifdef CONFIG_PPC_DENORMALISATION
1281 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1282 b exc_real_0x1500_denorm_exception_hv
1283 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1284 #else
1285 EXC_VIRT_NONE(0x5500, 0x100)
1286 #endif
1288 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
1290 #ifdef CONFIG_PPC_DENORMALISATION
1291 TRAMP_REAL_BEGIN(denorm_assist)
1292 BEGIN_FTR_SECTION
1293 /*
1294 * To denormalise we need to move a copy of the register to itself.
1295 * For POWER6 do that here for all FP regs.
1296 */
1297 mfmsr r10
1298 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1299 xori r10,r10,(MSR_FE0|MSR_FE1)
1300 mtmsrd r10
1301 sync
1303 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1304 #define FMR4(n) FMR2(n) ; FMR2(n+2)
1305 #define FMR8(n) FMR4(n) ; FMR4(n+4)
1306 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1307 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1308 FMR32(0)
1310 FTR_SECTION_ELSE
1311 /*
1312 * To denormalise we need to move a copy of the register to itself.
1313 * For POWER7 do that here for the first 32 VSX registers only.
1314 */
1315 mfmsr r10
1316 oris r10,r10,MSR_VSX@h
1317 mtmsrd r10
1318 sync
1320 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1321 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1322 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1323 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1324 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1325 XVCPSGNDP32(0)
1327 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1329 BEGIN_FTR_SECTION
1330 b denorm_done
1331 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1332 /*
1333 * To denormalise we need to move a copy of the register to itself.
1334 * For POWER8 we need to do that for all 64 VSX registers
1335 */
1336 XVCPSGNDP32(32)
1337 denorm_done:
1338 mtspr SPRN_HSRR0,r11
1339 mtcrf 0x80,r9
1340 ld r9,PACA_EXGEN+EX_R9(r13)
1341 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1342 BEGIN_FTR_SECTION
1343 ld r10,PACA_EXGEN+EX_CFAR(r13)
1344 mtspr SPRN_CFAR,r10
1345 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1346 ld r10,PACA_EXGEN+EX_R10(r13)
1347 ld r11,PACA_EXGEN+EX_R11(r13)
1348 ld r12,PACA_EXGEN+EX_R12(r13)
1349 ld r13,PACA_EXGEN+EX_R13(r13)
1350 HRFI_TO_UNKNOWN
1351 b .
1352 #endif
1354 EXC_COMMON(denorm_common, 0x1500, unknown_exception)
1357 #ifdef CONFIG_CBE_RAS
1358 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1359 EXC_VIRT_NONE(0x5600, 0x100)
1360 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1361 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1362 #else /* CONFIG_CBE_RAS */
1363 EXC_REAL_NONE(0x1600, 0x100)
1364 EXC_VIRT_NONE(0x5600, 0x100)
1365 #endif
1368 EXC_REAL(altivec_assist, 0x1700, 0x100)
1369 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1370 TRAMP_KVM(PACA_EXGEN, 0x1700)
1371 #ifdef CONFIG_ALTIVEC
1372 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1373 #else
1374 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1375 #endif
1378 #ifdef CONFIG_CBE_RAS
1379 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1380 EXC_VIRT_NONE(0x5800, 0x100)
1381 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1382 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1383 #else /* CONFIG_CBE_RAS */
1384 EXC_REAL_NONE(0x1800, 0x100)
1385 EXC_VIRT_NONE(0x5800, 0x100)
1386 #endif
1388 #ifdef CONFIG_PPC_WATCHDOG
1390 #define MASKED_DEC_HANDLER_LABEL 3f
1392 #define MASKED_DEC_HANDLER(_H) \
1393 3: /* soft-nmi */ \
1394 std r12,PACA_EXGEN+EX_R12(r13); \
1395 GET_SCRATCH0(r10); \
1396 std r10,PACA_EXGEN+EX_R13(r13); \
1397 EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H)
1399 /*
1400 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
1401 * stack is one that is usable by maskable interrupts so long as MSR_EE
1402 * remains off. It is used for recovery when something has corrupted the
1403 * normal kernel stack, for example. The "soft NMI" must not use the process
1404 * stack because we want irq disabled sections to avoid touching the stack
1405 * at all (other than PMU interrupts), so use the emergency stack for this,
1406 * and run it entirely with interrupts hard disabled.
1407 */
1408 EXC_COMMON_BEGIN(soft_nmi_common)
1409 mr r10,r1
1410 ld r1,PACAEMERGSP(r13)
1411 subi r1,r1,INT_FRAME_SIZE
1412 EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900,
1413 system_reset, soft_nmi_interrupt,
1414 ADD_NVGPRS;ADD_RECONCILE)
1415 b ret_from_except
1417 #else /* CONFIG_PPC_WATCHDOG */
1418 #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
1419 #define MASKED_DEC_HANDLER(_H)
1420 #endif /* CONFIG_PPC_WATCHDOG */
1422 /*
1423 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1424 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1425 * - If it was a doorbell we return immediately since doorbells are edge
1426 * triggered and won't automatically refire.
1427 * - If it was a HMI we return immediately since we handled it in realmode
1428 * and it won't refire.
1429 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
1430 * This is called with r10 containing the value to OR to the paca field.
1431 */
1432 #define MASKED_INTERRUPT(_H) \
1433 masked_##_H##interrupt: \
1434 std r11,PACA_EXGEN+EX_R11(r13); \
1435 lbz r11,PACAIRQHAPPENED(r13); \
1436 or r11,r11,r10; \
1437 stb r11,PACAIRQHAPPENED(r13); \
1438 cmpwi r10,PACA_IRQ_DEC; \
1439 bne 1f; \
1440 lis r10,0x7fff; \
1441 ori r10,r10,0xffff; \
1442 mtspr SPRN_DEC,r10; \
1443 b MASKED_DEC_HANDLER_LABEL; \
1444 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK; \
1445 beq 2f; \
1446 mfspr r10,SPRN_##_H##SRR1; \
1447 xori r10,r10,MSR_EE; /* clear MSR_EE */ \
1448 mtspr SPRN_##_H##SRR1,r10; \
1449 2: mtcrf 0x80,r9; \
1450 ld r9,PACA_EXGEN+EX_R9(r13); \
1451 ld r10,PACA_EXGEN+EX_R10(r13); \
1452 ld r11,PACA_EXGEN+EX_R11(r13); \
1453 /* returns to kernel where r13 must be set up, so don't restore it */ \
1454 ##_H##RFI_TO_KERNEL; \
1455 b .; \
1456 MASKED_DEC_HANDLER(_H)
1458 TRAMP_REAL_BEGIN(rfi_flush_fallback)
1459 SET_SCRATCH0(r13);
1460 GET_PACA(r13);
1461 std r9,PACA_EXRFI+EX_R9(r13)
1462 std r10,PACA_EXRFI+EX_R10(r13)
1463 std r11,PACA_EXRFI+EX_R11(r13)
1464 mfctr r9
1465 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1466 ld r11,PACA_L1D_FLUSH_SIZE(r13)
1467 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1468 mtctr r11
1469 DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1471 /* order ld/st prior to dcbt stop all streams with flushing */
1472 sync
1474 /*
1475 * The load adresses are at staggered offsets within cachelines,
1476 * which suits some pipelines better (on others it should not
1477 * hurt).
1478 */
1479 1:
1480 ld r11,(0x80 + 8)*0(r10)
1481 ld r11,(0x80 + 8)*1(r10)
1482 ld r11,(0x80 + 8)*2(r10)
1483 ld r11,(0x80 + 8)*3(r10)
1484 ld r11,(0x80 + 8)*4(r10)
1485 ld r11,(0x80 + 8)*5(r10)
1486 ld r11,(0x80 + 8)*6(r10)
1487 ld r11,(0x80 + 8)*7(r10)
1488 addi r10,r10,0x80*8
1489 bdnz 1b
1491 mtctr r9
1492 ld r9,PACA_EXRFI+EX_R9(r13)
1493 ld r10,PACA_EXRFI+EX_R10(r13)
1494 ld r11,PACA_EXRFI+EX_R11(r13)
1495 GET_SCRATCH0(r13);
1496 rfid
1498 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
1499 SET_SCRATCH0(r13);
1500 GET_PACA(r13);
1501 std r9,PACA_EXRFI+EX_R9(r13)
1502 std r10,PACA_EXRFI+EX_R10(r13)
1503 std r11,PACA_EXRFI+EX_R11(r13)
1504 mfctr r9
1505 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
1506 ld r11,PACA_L1D_FLUSH_SIZE(r13)
1507 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
1508 mtctr r11
1509 DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
1511 /* order ld/st prior to dcbt stop all streams with flushing */
1512 sync
1514 /*
1515 * The load adresses are at staggered offsets within cachelines,
1516 * which suits some pipelines better (on others it should not
1517 * hurt).
1518 */
1519 1:
1520 ld r11,(0x80 + 8)*0(r10)
1521 ld r11,(0x80 + 8)*1(r10)
1522 ld r11,(0x80 + 8)*2(r10)
1523 ld r11,(0x80 + 8)*3(r10)
1524 ld r11,(0x80 + 8)*4(r10)
1525 ld r11,(0x80 + 8)*5(r10)
1526 ld r11,(0x80 + 8)*6(r10)
1527 ld r11,(0x80 + 8)*7(r10)
1528 addi r10,r10,0x80*8
1529 bdnz 1b
1531 mtctr r9
1532 ld r9,PACA_EXRFI+EX_R9(r13)
1533 ld r10,PACA_EXRFI+EX_R10(r13)
1534 ld r11,PACA_EXRFI+EX_R11(r13)
1535 GET_SCRATCH0(r13);
1536 hrfid
1538 /*
1539 * Real mode exceptions actually use this too, but alternate
1540 * instruction code patches (which end up in the common .text area)
1541 * cannot reach these if they are put there.
1542 */
1543 USE_FIXED_SECTION(virt_trampolines)
1544 MASKED_INTERRUPT()
1545 MASKED_INTERRUPT(H)
1547 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1548 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1549 /*
1550 * Here all GPRs are unchanged from when the interrupt happened
1551 * except for r13, which is saved in SPRG_SCRATCH0.
1552 */
1553 mfspr r13, SPRN_SRR0
1554 addi r13, r13, 4
1555 mtspr SPRN_SRR0, r13
1556 GET_SCRATCH0(r13)
1557 RFI_TO_KERNEL
1558 b .
1560 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1561 /*
1562 * Here all GPRs are unchanged from when the interrupt happened
1563 * except for r13, which is saved in SPRG_SCRATCH0.
1564 */
1565 mfspr r13, SPRN_HSRR0
1566 addi r13, r13, 4
1567 mtspr SPRN_HSRR0, r13
1568 GET_SCRATCH0(r13)
1569 HRFI_TO_KERNEL
1570 b .
1571 #endif
1573 /*
1574 * Ensure that any handlers that get invoked from the exception prologs
1575 * above are below the first 64KB (0x10000) of the kernel image because
1576 * the prologs assemble the addresses of these handlers using the
1577 * LOAD_HANDLER macro, which uses an ori instruction.
1578 */
1580 /*** Common interrupt handlers ***/
1583 /*
1584 * Relocation-on interrupts: A subset of the interrupts can be delivered
1585 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1586 * it. Addresses are the same as the original interrupt addresses, but
1587 * offset by 0xc000000000004000.
1588 * It's impossible to receive interrupts below 0x300 via this mechanism.
1589 * KVM: None of these traps are from the guest ; anything that escalated
1590 * to HV=1 from HV=0 is delivered via real mode handlers.
1591 */
1593 /*
1594 * This uses the standard macro, since the original 0x300 vector
1595 * only has extra guff for STAB-based processors -- which never
1596 * come here.
1597 */
1599 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1600 b __ppc64_runlatch_on
1602 USE_FIXED_SECTION(virt_trampolines)
1603 /*
1604 * The __end_interrupts marker must be past the out-of-line (OOL)
1605 * handlers, so that they are copied to real address 0x100 when running
1606 * a relocatable kernel. This ensures they can be reached from the short
1607 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1608 * directly, without using LOAD_HANDLER().
1609 */
1610 .align 7
1611 .globl __end_interrupts
1612 __end_interrupts:
1613 DEFINE_FIXED_SYMBOL(__end_interrupts)
1615 #ifdef CONFIG_PPC_970_NAP
1616 EXC_COMMON_BEGIN(power4_fixup_nap)
1617 andc r9,r9,r10
1618 std r9,TI_LOCAL_FLAGS(r11)
1619 ld r10,_LINK(r1) /* make idle task do the */
1620 std r10,_NIP(r1) /* equivalent of a blr */
1621 blr
1622 #endif
1624 CLOSE_FIXED_SECTION(real_vectors);
1625 CLOSE_FIXED_SECTION(real_trampolines);
1626 CLOSE_FIXED_SECTION(virt_vectors);
1627 CLOSE_FIXED_SECTION(virt_trampolines);
1629 USE_TEXT_SECTION()
1631 /*
1632 * Hash table stuff
1633 */
1634 .balign IFETCH_ALIGN_BYTES
1635 do_hash_page:
1636 #ifdef CONFIG_PPC_BOOK3S_64
1637 lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h
1638 ori r0,r0,DSISR_BAD_FAULT_64S@l
1639 and. r0,r4,r0 /* weird error? */
1640 bne- handle_page_fault /* if not, try to insert a HPTE */
1641 CURRENT_THREAD_INFO(r11, r1)
1642 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1643 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1644 bne 77f /* then don't call hash_page now */
1646 /*
1647 * r3 contains the faulting address
1648 * r4 msr
1649 * r5 contains the trap number
1650 * r6 contains dsisr
1651 *
1652 * at return r3 = 0 for success, 1 for page fault, negative for error
1653 */
1654 mr r4,r12
1655 ld r6,_DSISR(r1)
1656 bl __hash_page /* build HPTE if possible */
1657 cmpdi r3,0 /* see if __hash_page succeeded */
1659 /* Success */
1660 beq fast_exc_return_irq /* Return from exception on success */
1662 /* Error */
1663 blt- 13f
1665 /* Reload DSISR into r4 for the DABR check below */
1666 ld r4,_DSISR(r1)
1667 #endif /* CONFIG_PPC_BOOK3S_64 */
1669 /* Here we have a page fault that hash_page can't handle. */
1670 handle_page_fault:
1671 11: andis. r0,r4,DSISR_DABRMATCH@h
1672 bne- handle_dabr_fault
1673 ld r4,_DAR(r1)
1674 ld r5,_DSISR(r1)
1675 addi r3,r1,STACK_FRAME_OVERHEAD
1676 bl do_page_fault
1677 cmpdi r3,0
1678 beq+ 12f
1679 bl save_nvgprs
1680 mr r5,r3
1681 addi r3,r1,STACK_FRAME_OVERHEAD
1682 lwz r4,_DAR(r1)
1683 bl bad_page_fault
1684 b ret_from_except
1686 /* We have a data breakpoint exception - handle it */
1687 handle_dabr_fault:
1688 bl save_nvgprs
1689 ld r4,_DAR(r1)
1690 ld r5,_DSISR(r1)
1691 addi r3,r1,STACK_FRAME_OVERHEAD
1692 bl do_break
1693 12: b ret_from_except_lite
1696 #ifdef CONFIG_PPC_BOOK3S_64
1697 /* We have a page fault that hash_page could handle but HV refused
1698 * the PTE insertion
1699 */
1700 13: bl save_nvgprs
1701 mr r5,r3
1702 addi r3,r1,STACK_FRAME_OVERHEAD
1703 ld r4,_DAR(r1)
1704 bl low_hash_fault
1705 b ret_from_except
1706 #endif
1708 /*
1709 * We come here as a result of a DSI at a point where we don't want
1710 * to call hash_page, such as when we are accessing memory (possibly
1711 * user memory) inside a PMU interrupt that occurred while interrupts
1712 * were soft-disabled. We want to invoke the exception handler for
1713 * the access, or panic if there isn't a handler.
1714 */
1715 77: bl save_nvgprs
1716 mr r4,r3
1717 addi r3,r1,STACK_FRAME_OVERHEAD
1718 li r5,SIGSEGV
1719 bl bad_page_fault
1720 b ret_from_except
1722 /*
1723 * Here we have detected that the kernel stack pointer is bad.
1724 * R9 contains the saved CR, r13 points to the paca,
1725 * r10 contains the (bad) kernel stack pointer,
1726 * r11 and r12 contain the saved SRR0 and SRR1.
1727 * We switch to using an emergency stack, save the registers there,
1728 * and call kernel_bad_stack(), which panics.
1729 */
1730 bad_stack:
1731 ld r1,PACAEMERGSP(r13)
1732 subi r1,r1,64+INT_FRAME_SIZE
1733 std r9,_CCR(r1)
1734 std r10,GPR1(r1)
1735 std r11,_NIP(r1)
1736 std r12,_MSR(r1)
1737 mfspr r11,SPRN_DAR
1738 mfspr r12,SPRN_DSISR
1739 std r11,_DAR(r1)
1740 std r12,_DSISR(r1)
1741 mflr r10
1742 mfctr r11
1743 mfxer r12
1744 std r10,_LINK(r1)
1745 std r11,_CTR(r1)
1746 std r12,_XER(r1)
1747 SAVE_GPR(0,r1)
1748 SAVE_GPR(2,r1)
1749 ld r10,EX_R3(r3)
1750 std r10,GPR3(r1)
1751 SAVE_GPR(4,r1)
1752 SAVE_4GPRS(5,r1)
1753 ld r9,EX_R9(r3)
1754 ld r10,EX_R10(r3)
1755 SAVE_2GPRS(9,r1)
1756 ld r9,EX_R11(r3)
1757 ld r10,EX_R12(r3)
1758 ld r11,EX_R13(r3)
1759 std r9,GPR11(r1)
1760 std r10,GPR12(r1)
1761 std r11,GPR13(r1)
1762 BEGIN_FTR_SECTION
1763 ld r10,EX_CFAR(r3)
1764 std r10,ORIG_GPR3(r1)
1765 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1766 SAVE_8GPRS(14,r1)
1767 SAVE_10GPRS(22,r1)
1768 lhz r12,PACA_TRAP_SAVE(r13)
1769 std r12,_TRAP(r1)
1770 addi r11,r1,INT_FRAME_SIZE
1771 std r11,0(r1)
1772 li r12,0
1773 std r12,0(r11)
1774 ld r2,PACATOC(r13)
1775 ld r11,exception_marker@toc(r2)
1776 std r12,RESULT(r1)
1777 std r11,STACK_FRAME_OVERHEAD-16(r1)
1778 1: addi r3,r1,STACK_FRAME_OVERHEAD
1779 bl kernel_bad_stack
1780 b 1b
1781 _ASM_NOKPROBE_SYMBOL(bad_stack);
1783 /*
1784 * When doorbell is triggered from system reset wakeup, the message is
1785 * not cleared, so it would fire again when EE is enabled.
1786 *
1787 * When coming from local_irq_enable, there may be the same problem if
1788 * we were hard disabled.
1789 *
1790 * Execute msgclr to clear pending exceptions before handling it.
1791 */
1792 h_doorbell_common_msgclr:
1793 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1794 PPC_MSGCLR(3)
1795 b h_doorbell_common
1797 doorbell_super_common_msgclr:
1798 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1799 PPC_MSGCLRP(3)
1800 b doorbell_super_common
1802 /*
1803 * Called from arch_local_irq_enable when an interrupt needs
1804 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1805 * which kind of interrupt. MSR:EE is already off. We generate a
1806 * stackframe like if a real interrupt had happened.
1807 *
1808 * Note: While MSR:EE is off, we need to make sure that _MSR
1809 * in the generated frame has EE set to 1 or the exception
1810 * handler will not properly re-enable them.
1811 *
1812 * Note that we don't specify LR as the NIP (return address) for
1813 * the interrupt because that would unbalance the return branch
1814 * predictor.
1815 */
1816 _GLOBAL(__replay_interrupt)
1817 /* We are going to jump to the exception common code which
1818 * will retrieve various register values from the PACA which
1819 * we don't give a damn about, so we don't bother storing them.
1820 */
1821 mfmsr r12
1822 LOAD_REG_ADDR(r11, replay_interrupt_return)
1823 mfcr r9
1824 ori r12,r12,MSR_EE
1825 cmpwi r3,0x900
1826 beq decrementer_common
1827 cmpwi r3,0x500
1828 BEGIN_FTR_SECTION
1829 beq h_virt_irq_common
1830 FTR_SECTION_ELSE
1831 beq hardware_interrupt_common
1832 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300)
1833 cmpwi r3,0xf00
1834 beq performance_monitor_common
1835 BEGIN_FTR_SECTION
1836 cmpwi r3,0xa00
1837 beq h_doorbell_common_msgclr
1838 cmpwi r3,0xe60
1839 beq hmi_exception_common
1840 FTR_SECTION_ELSE
1841 cmpwi r3,0xa00
1842 beq doorbell_super_common_msgclr
1843 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1844 replay_interrupt_return:
1845 blr
1847 _ASM_NOKPROBE_SYMBOL(__replay_interrupt)