1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_S390_PCI_CLP_H
3 #define _ASM_S390_PCI_CLP_H
8 * Call Logical Processor - Command Codes
10 #define CLP_LIST_PCI 0x0002
11 #define CLP_QUERY_PCI_FN 0x0003
12 #define CLP_QUERY_PCI_FNGRP 0x0004
13 #define CLP_SET_PCI_FN 0x0005
15 /* PCI function handle list entry */
16 struct clp_fh_list_entry
{
21 u32 fid
; /* PCI function id */
22 u32 fh
; /* PCI function handle */
25 #define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */
26 #define CLP_RC_SETPCIFN_FHOP 0x0102 /* Fn handle not valid for op */
27 #define CLP_RC_SETPCIFN_DMAAS 0x0103 /* Invalid DMA addr space */
28 #define CLP_RC_SETPCIFN_RES 0x0104 /* Insufficient resources */
29 #define CLP_RC_SETPCIFN_ALRDY 0x0105 /* Fn already in requested state */
30 #define CLP_RC_SETPCIFN_ERR 0x0106 /* Fn in permanent error state */
31 #define CLP_RC_SETPCIFN_RECPND 0x0107 /* Error recovery pending */
32 #define CLP_RC_SETPCIFN_BUSY 0x0108 /* Fn busy */
33 #define CLP_RC_LISTPCI_BADRT 0x010a /* Resume token not recognized */
34 #define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */
36 /* request or response block header length */
37 #define LIST_PCI_HDR_LEN 32
39 /* Number of function handles fitting in response block */
40 #define CLP_FH_LIST_NR_ENTRIES \
41 ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \
42 / sizeof(struct clp_fh_list_entry))
44 #define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */
45 #define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
47 #define CLP_UTIL_STR_LEN 64
48 #define CLP_PFIP_NR_SEGMENTS 4
50 extern bool zpci_unique_uid
;
52 /* List PCI functions request */
53 struct clp_req_list_pci
{
54 struct clp_req_hdr hdr
;
59 /* List PCI functions response */
60 struct clp_rsp_list_pci
{
61 struct clp_rsp_hdr hdr
;
68 struct clp_fh_list_entry fh_list
[CLP_FH_LIST_NR_ENTRIES
];
71 /* Query PCI function request */
72 struct clp_req_query_pci
{
73 struct clp_req_hdr hdr
;
74 u32 fh
; /* function handle */
79 /* Query PCI function response */
80 struct clp_rsp_query_pci
{
81 struct clp_rsp_hdr hdr
;
82 u16 vfn
; /* virtual fn number */
84 u16 util_str_avail
: 1; /* utility string available? */
85 u16 pfgid
: 8; /* pci function group id */
86 u32 fid
; /* pci function id */
87 u8 bar_size
[PCI_BAR_COUNT
];
89 __le32 bar
[PCI_BAR_COUNT
];
90 u8 pfip
[CLP_PFIP_NR_SEGMENTS
]; /* pci function internal path */
93 u8 pft
; /* pci function type */
94 u64 sdma
; /* start dma as */
95 u64 edma
; /* end dma as */
97 u32 uid
; /* user defined id */
98 u8 util_str
[CLP_UTIL_STR_LEN
]; /* utility string */
101 /* Query PCI function group request */
102 struct clp_req_query_pci_grp
{
103 struct clp_req_hdr hdr
;
105 u32 pfgid
: 8; /* function group id */
110 /* Query PCI function group response */
111 struct clp_rsp_query_pci_grp
{
112 struct clp_rsp_hdr hdr
;
114 u16 noi
: 12; /* number of interrupts */
118 u8 refresh
: 1; /* TLB refresh mode */
122 u64 dasm
; /* dma address space mask */
123 u64 msia
; /* MSI address */
128 /* Set PCI function request */
129 struct clp_req_set_pci
{
130 struct clp_req_hdr hdr
;
131 u32 fh
; /* function handle */
133 u8 oc
; /* operation controls */
134 u8 ndas
; /* number of dma spaces */
138 /* Set PCI function response */
139 struct clp_rsp_set_pci
{
140 struct clp_rsp_hdr hdr
;
141 u32 fh
; /* function handle */
146 /* Combined request/response block structures used by clp insn */
147 struct clp_req_rsp_list_pci
{
148 struct clp_req_list_pci request
;
149 struct clp_rsp_list_pci response
;
152 struct clp_req_rsp_set_pci
{
153 struct clp_req_set_pci request
;
154 struct clp_rsp_set_pci response
;
157 struct clp_req_rsp_query_pci
{
158 struct clp_req_query_pci request
;
159 struct clp_rsp_query_pci response
;
162 struct clp_req_rsp_query_pci_grp
{
163 struct clp_req_query_pci_grp request
;
164 struct clp_rsp_query_pci_grp response
;