arch/s390/include/asm/pci_insn.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_S390_PCI_INSN_H
   3 #define _ASM_S390_PCI_INSN_H
   4
   5 /* Load/Store status codes */
   6 #define ZPCI_PCI_ST_FUNC_NOT_ENABLED            4
   7 #define ZPCI_PCI_ST_FUNC_IN_ERR                 8
   8 #define ZPCI_PCI_ST_BLOCKED                     12
   9 #define ZPCI_PCI_ST_INSUF_RES                   16
  10 #define ZPCI_PCI_ST_INVAL_AS                    20
  11 #define ZPCI_PCI_ST_FUNC_ALREADY_ENABLED        24
  12 #define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED          28
  13 #define ZPCI_PCI_ST_2ND_OP_IN_INV_AS            36
  14 #define ZPCI_PCI_ST_FUNC_NOT_AVAIL              40
  15 #define ZPCI_PCI_ST_ALREADY_IN_RQ_STATE         44
  16
  17 /* Load/Store return codes */
  18 #define ZPCI_PCI_LS_OK                          0
  19 #define ZPCI_PCI_LS_ERR                         1
  20 #define ZPCI_PCI_LS_BUSY                        2
  21 #define ZPCI_PCI_LS_INVAL_HANDLE                3
  22
  23 /* Load/Store address space identifiers */
  24 #define ZPCI_PCIAS_MEMIO_0                      0
  25 #define ZPCI_PCIAS_MEMIO_1                      1
  26 #define ZPCI_PCIAS_MEMIO_2                      2
  27 #define ZPCI_PCIAS_MEMIO_3                      3
  28 #define ZPCI_PCIAS_MEMIO_4                      4
  29 #define ZPCI_PCIAS_MEMIO_5                      5
  30 #define ZPCI_PCIAS_CFGSPC                       15
  31
  32 /* Modify PCI Function Controls */
  33 #define ZPCI_MOD_FC_REG_INT     2
  34 #define ZPCI_MOD_FC_DEREG_INT   3
  35 #define ZPCI_MOD_FC_REG_IOAT    4
  36 #define ZPCI_MOD_FC_DEREG_IOAT  5
  37 #define ZPCI_MOD_FC_REREG_IOAT  6
  38 #define ZPCI_MOD_FC_RESET_ERROR 7
  39 #define ZPCI_MOD_FC_RESET_BLOCK 9
  40 #define ZPCI_MOD_FC_SET_MEASURE 10
  41
  42 /* FIB function controls */
  43 #define ZPCI_FIB_FC_ENABLED     0x80
  44 #define ZPCI_FIB_FC_ERROR       0x40
  45 #define ZPCI_FIB_FC_LS_BLOCKED  0x20
  46 #define ZPCI_FIB_FC_DMAAS_REG   0x10
  47
  48 /* FIB function controls */
  49 #define ZPCI_FIB_FC_ENABLED     0x80
  50 #define ZPCI_FIB_FC_ERROR       0x40
  51 #define ZPCI_FIB_FC_LS_BLOCKED  0x20
  52 #define ZPCI_FIB_FC_DMAAS_REG   0x10
  53
  54 /* Function Information Block */
  55 struct zpci_fib {
  56         u32 fmt         :  8;   /* format */
  57         u32             : 24;
  58         u32             : 32;
  59         u8 fc;                  /* function controls */
  60         u64             : 56;
  61         u64 pba;                /* PCI base address */
  62         u64 pal;                /* PCI address limit */
  63         u64 iota;               /* I/O Translation Anchor */
  64         u32             :  1;
  65         u32 isc         :  3;   /* Interrupt subclass */
  66         u32 noi         : 12;   /* Number of interrupts */
  67         u32             :  2;
  68         u32 aibvo       :  6;   /* Adapter interrupt bit vector offset */
  69         u32 sum         :  1;   /* Adapter int summary bit enabled */
  70         u32             :  1;
  71         u32 aisbo       :  6;   /* Adapter int summary bit offset */
  72         u32             : 32;
  73         u64 aibv;               /* Adapter int bit vector address */
  74         u64 aisb;               /* Adapter int summary bit address */
  75         u64 fmb_addr;           /* Function measurement block address and key */
  76         u32             : 32;
  77         u32 gd;
  78 } __packed __aligned(8);
  79
  80 u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status);
  81 int zpci_refresh_trans(u64 fn, u64 addr, u64 range);
  82 int zpci_load(u64 *data, u64 req, u64 offset);
  83 int zpci_store(u64 data, u64 req, u64 offset);
  84 int zpci_store_block(const u64 *data, u64 req, u64 offset);
  85 int zpci_set_irq_ctrl(u16 ctl, char *unused, u8 isc);
  86
  87 #endif