1 /* SPDX-License-Identifier: GPL-2.0 */
3 * etrap.S: Preparing for entry into the kernel on Sparc V9.
5 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
11 #include <asm/pstate.h>
12 #include <asm/ptrace.h>
14 #include <asm/spitfire.h>
16 #include <asm/processor.h>
19 #define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
20 #define ETRAP_PSTATE1 (PSTATE_TSO | PSTATE_PRIV)
21 #define ETRAP_PSTATE2 \
22 (PSTATE_TSO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
25 * On entry, %g7 is return address - 0x4.
26 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
31 .globl etrap_syscall, etrap, etrap_irq, etraptl1
34 etrap_syscall: TRAP_LOAD_THREAD_REG(%g6, %g1)
38 andcc %g1, TSTATE_PRIV, %g0
41 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
42 661: wrpr %g0, 7, %cleanwin
43 .section .fast_win_ctrl_1insn_patch, "ax"
45 .word 0x85880000 ! allclean
48 sethi %hi(TASK_REGOFF), %g2
49 sethi %hi(TSTATE_PEF), %g3
50 or %g2, %lo(TASK_REGOFF), %g2
57 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
59 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
61 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
63 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
64 sethi %hi(PT_REGS_MAGIC), %g3
66 st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]
69 brnz,pt %g1, etrap_save
75 be,pt %xcc, etrap_user_spill
79 brz %g3, etrap_kernel_spill
85 ldx [%g6 + TI_FLAGS], %g3
86 and %g3, _TIF_32BIT, %g3
87 brnz,pt %g3, etrap_user_spill_32bit
89 ba,a,pt %xcc, etrap_user_spill_64bit
91 etrap_save: save %g2, -STACK_BIAS, %sp
95 mov PRIMARY_CONTEXT, %l4
96 661: rdpr %canrestore, %g3
97 .section .fast_win_ctrl_1insn_patch, "ax"
103 661: wrpr %g0, 0, %canrestore
104 .section .fast_win_ctrl_1insn_patch, "ax"
110 /* Set TI_SYS_FPDEPTH to 1 and clear TI_SYS_NOERROR. */
112 sth %l5, [%l6 + TI_SYS_NOERROR]
114 661: wrpr %g3, 0, %otherwin
115 .section .fast_win_ctrl_1insn_patch, "ax"
117 .word 0x87880000 ! otherw
121 sethi %hi(sparc64_kern_pri_context), %g2
122 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
124 661: stxa %g3, [%l4] ASI_DMMU
125 .section .sun4v_1insn_patch, "ax"
127 stxa %g3, [%l4] ASI_MMU
130 sethi %hi(KERNBASE), %l4
137 /* Go to trap time globals so we can save them. */
138 661: wrpr %g0, ETRAP_PSTATE1, %pstate
139 .section .sun4v_1insn_patch, "ax"
144 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
145 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
147 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
149 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
150 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
151 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
152 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
154 sethi %hi(TSTATE_TSO | TSTATE_PEF), %l0
157 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
158 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
159 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
160 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
161 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
162 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
163 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
164 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
166 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
167 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
168 ldx [%g6 + TI_TASK], %g4
172 ldub [%l6 + TI_FPDEPTH], %l5
173 add %l6, TI_FPSAVED + 1, %l4
177 /* Set TI_SYS_FPDEPTH to %l5 and clear TI_SYS_NOERROR. */
178 sth %l5, [%l6 + TI_SYS_NOERROR]
183 etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
184 * We place this right after pt_regs on the trap stack.
194 TRAP_LOAD_THREAD_REG(%g6, %g1)
195 sub %sp, ((4 * 8) * 4) + 8, %g2
200 stx %g3, [%g2 + STACK_BIAS + 0x00]
202 stx %g3, [%g2 + STACK_BIAS + 0x08]
204 stx %g3, [%g2 + STACK_BIAS + 0x10]
206 stx %g3, [%g2 + STACK_BIAS + 0x18]
210 stx %g3, [%g2 + STACK_BIAS + 0x20]
212 stx %g3, [%g2 + STACK_BIAS + 0x28]
214 stx %g3, [%g2 + STACK_BIAS + 0x30]
216 stx %g3, [%g2 + STACK_BIAS + 0x38]
218 sethi %hi(is_sun4v), %g3
219 lduw [%g3 + %lo(is_sun4v)], %g3
220 brnz,pn %g3, finish_tl1_capture
225 stx %g3, [%g2 + STACK_BIAS + 0x40]
227 stx %g3, [%g2 + STACK_BIAS + 0x48]
229 stx %g3, [%g2 + STACK_BIAS + 0x50]
231 stx %g3, [%g2 + STACK_BIAS + 0x58]
235 stx %g3, [%g2 + STACK_BIAS + 0x60]
237 stx %g3, [%g2 + STACK_BIAS + 0x68]
239 stx %g3, [%g2 + STACK_BIAS + 0x70]
241 stx %g3, [%g2 + STACK_BIAS + 0x78]
243 stx %g1, [%g2 + STACK_BIAS + 0x80]
248 .section .sun4v_1insn_patch, "ax"
254 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
256 andcc %g1, TSTATE_PRIV, %g0