include/linux/qcom_scm.h

   1 /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
   2  * Copyright (C) 2015 Linaro Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 #ifndef __QCOM_SCM_H
  14 #define __QCOM_SCM_H
  15
  16 #define QCOM_SCM_VERSION(major, minor)  (((major) << 16) | ((minor) & 0xFF))
  17 #define QCOM_SCM_CPU_PWR_DOWN_L2_ON     0x0
  18 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF    0x1
  19 #define QCOM_SCM_HDCP_MAX_REQ_CNT       5
  20
  21 struct qcom_scm_hdcp_req {
  22         u32 addr;
  23         u32 val;
  24 };
  25
  26 struct qcom_scm_vmperm {
  27         int vmid;
  28         int perm;
  29 };
  30
  31 #define QCOM_SCM_VMID_HLOS       0x3
  32 #define QCOM_SCM_VMID_MSS_MSA    0xF
  33 #define QCOM_SCM_PERM_READ       0x4
  34 #define QCOM_SCM_PERM_WRITE      0x2
  35 #define QCOM_SCM_PERM_EXEC       0x1
  36 #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
  37 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
  38
  39 #if IS_ENABLED(CONFIG_QCOM_SCM)
  40 extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
  41 extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
  42 extern bool qcom_scm_is_available(void);
  43 extern bool qcom_scm_hdcp_available(void);
  44 extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
  45                              u32 *resp);
  46 extern bool qcom_scm_pas_supported(u32 peripheral);
  47 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
  48                                    size_t size);
  49 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
  50                                   phys_addr_t size);
  51 extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
  52 extern int qcom_scm_pas_shutdown(u32 peripheral);
  53 extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
  54                                unsigned int *src, struct qcom_scm_vmperm *newvm,
  55                                int dest_cnt);
  56 extern void qcom_scm_cpu_power_down(u32 flags);
  57 extern u32 qcom_scm_get_version(void);
  58 extern int qcom_scm_set_remote_state(u32 state, u32 id);
  59 extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
  60 extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
  61 extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
  62 extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
  63 extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
  64 #else
  65 static inline
  66 int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
  67 {
  68         return -ENODEV;
  69 }
  70 static inline
  71 int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
  72 {
  73         return -ENODEV;
  74 }
  75 static inline bool qcom_scm_is_available(void) { return false; }
  76 static inline bool qcom_scm_hdcp_available(void) { return false; }
  77 static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
  78                                     u32 *resp) { return -ENODEV; }
  79 static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
  80 static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
  81                                           size_t size) { return -ENODEV; }
  82 static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
  83                                          phys_addr_t size) { return -ENODEV; }
  84 static inline int
  85 qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
  86 static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
  87 static inline void qcom_scm_cpu_power_down(u32 flags) {}
  88 static inline u32 qcom_scm_get_version(void) { return 0; }
  89 static inline u32
  90 qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
  91 static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
  92 static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
  93 static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
  94 static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
  95 static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
  96 #endif
  97 #endif