| blob | dececc4b5ff280f8b40fc22be6c5bc8bdd5ac433 |
1 /*
2 * Device Tree Source for AMCC Kilauea (405EX)
3 *
4 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
11 /dts-v1/;
13 / {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 model = "amcc,kilauea";
17 compatible = "amcc,kilauea";
18 dcr-parent = <&{/cpus/cpu@0}>;
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,405EX";
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <16384>; /* 16 kB */
40 d-cache-size = <16384>; /* 16 kB */
41 dcr-controller;
42 dcr-access-method = "native";
43 };
44 };
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
49 };
51 UIC0: interrupt-controller {
52 compatible = "ibm,uic-405ex", "ibm,uic";
53 interrupt-controller;
54 cell-index = <0>;
55 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
58 #interrupt-cells = <2>;
59 };
61 UIC1: interrupt-controller1 {
62 compatible = "ibm,uic-405ex","ibm,uic";
63 interrupt-controller;
64 cell-index = <1>;
65 dcr-reg = <0x0d0 0x009>;
66 #address-cells = <0>;
67 #size-cells = <0>;
68 #interrupt-cells = <2>;
69 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
70 interrupt-parent = <&UIC0>;
71 };
73 UIC2: interrupt-controller2 {
74 compatible = "ibm,uic-405ex","ibm,uic";
75 interrupt-controller;
76 cell-index = <2>;
77 dcr-reg = <0x0e0 0x009>;
78 #address-cells = <0>;
79 #size-cells = <0>;
80 #interrupt-cells = <2>;
81 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
82 interrupt-parent = <&UIC0>;
83 };
85 plb {
86 compatible = "ibm,plb-405ex", "ibm,plb4";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges;
90 clock-frequency = <0>; /* Filled in by U-Boot */
92 SDRAM0: memory-controller {
93 compatible = "ibm,sdram-405ex";
94 dcr-reg = <0x010 0x002>;
95 };
97 MAL0: mcmal {
98 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
99 dcr-reg = <0x180 0x062>;
100 num-tx-chans = <2>;
101 num-rx-chans = <2>;
102 interrupt-parent = <&MAL0>;
103 interrupts = <0x0 0x1 0x2 0x3 0x4>;
104 #interrupt-cells = <1>;
105 #address-cells = <0>;
106 #size-cells = <0>;
107 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
108 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
109 /*SERR*/ 0x2 &UIC1 0x0 0x4
110 /*TXDE*/ 0x3 &UIC1 0x1 0x4
111 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
112 interrupt-map-mask = <0xffffffff>;
113 };
115 POB0: opb {
116 compatible = "ibm,opb-405ex", "ibm,opb";
117 #address-cells = <1>;
118 #size-cells = <1>;
119 ranges = <0x80000000 0x80000000 0x10000000
120 0xef600000 0xef600000 0x00a00000
121 0xf0000000 0xf0000000 0x10000000>;
122 dcr-reg = <0x0a0 0x005>;
123 clock-frequency = <0>; /* Filled in by U-Boot */
125 EBC0: ebc {
126 compatible = "ibm,ebc-405ex", "ibm,ebc";
127 dcr-reg = <0x012 0x002>;
128 #address-cells = <2>;
129 #size-cells = <1>;
130 clock-frequency = <0>; /* Filled in by U-Boot */
131 /* ranges property is supplied by U-Boot */
132 interrupts = <0x5 0x1>;
133 interrupt-parent = <&UIC1>;
135 nor_flash@0,0 {
136 compatible = "amd,s29gl512n", "cfi-flash";
137 bank-width = <2>;
138 reg = <0x00000000 0x00000000 0x04000000>;
139 #address-cells = <1>;
140 #size-cells = <1>;
141 partition@0 {
142 label = "kernel";
143 reg = <0x00000000 0x00200000>;
144 };
145 partition@200000 {
146 label = "root";
147 reg = <0x00200000 0x00200000>;
148 };
149 partition@400000 {
150 label = "user";
151 reg = <0x00400000 0x03b60000>;
152 };
153 partition@3f60000 {
154 label = "env";
155 reg = <0x03f60000 0x00040000>;
156 };
157 partition@3fa0000 {
158 label = "u-boot";
159 reg = <0x03fa0000 0x00060000>;
160 };
161 };
162 };
164 UART0: serial@ef600200 {
165 device_type = "serial";
166 compatible = "ns16550";
167 reg = <0xef600200 0x00000008>;
168 virtual-reg = <0xef600200>;
169 clock-frequency = <0>; /* Filled in by U-Boot */
170 current-speed = <0>;
171 interrupt-parent = <&UIC0>;
172 interrupts = <0x1a 0x4>;
173 };
175 UART1: serial@ef600300 {
176 device_type = "serial";
177 compatible = "ns16550";
178 reg = <0xef600300 0x00000008>;
179 virtual-reg = <0xef600300>;
180 clock-frequency = <0>; /* Filled in by U-Boot */
181 current-speed = <0>;
182 interrupt-parent = <&UIC0>;
183 interrupts = <0x1 0x4>;
184 };
186 IIC0: i2c@ef600400 {
187 compatible = "ibm,iic-405ex", "ibm,iic";
188 reg = <0xef600400 0x00000014>;
189 interrupt-parent = <&UIC0>;
190 interrupts = <0x2 0x4>;
191 };
193 IIC1: i2c@ef600500 {
194 compatible = "ibm,iic-405ex", "ibm,iic";
195 reg = <0xef600500 0x00000014>;
196 interrupt-parent = <&UIC0>;
197 interrupts = <0x7 0x4>;
198 };
201 RGMII0: emac-rgmii@ef600b00 {
202 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
203 reg = <0xef600b00 0x00000104>;
204 has-mdio;
205 };
207 EMAC0: ethernet@ef600900 {
208 linux,network-index = <0x0>;
209 device_type = "network";
210 compatible = "ibm,emac-405ex", "ibm,emac4sync";
211 interrupt-parent = <&EMAC0>;
212 interrupts = <0x0 0x1>;
213 #interrupt-cells = <1>;
214 #address-cells = <0>;
215 #size-cells = <0>;
216 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
217 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
218 reg = <0xef600900 0x000000c4>;
219 local-mac-address = [000000000000]; /* Filled in by U-Boot */
220 mal-device = <&MAL0>;
221 mal-tx-channel = <0>;
222 mal-rx-channel = <0>;
223 cell-index = <0>;
224 max-frame-size = <9000>;
225 rx-fifo-size = <4096>;
226 tx-fifo-size = <2048>;
227 phy-mode = "rgmii";
228 phy-map = <0x00000000>;
229 rgmii-device = <&RGMII0>;
230 rgmii-channel = <0>;
231 has-inverted-stacr-oc;
232 has-new-stacr-staopc;
233 };
235 EMAC1: ethernet@ef600a00 {
236 linux,network-index = <0x1>;
237 device_type = "network";
238 compatible = "ibm,emac-405ex", "ibm,emac4sync";
239 interrupt-parent = <&EMAC1>;
240 interrupts = <0x0 0x1>;
241 #interrupt-cells = <1>;
242 #address-cells = <0>;
243 #size-cells = <0>;
244 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
245 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
246 reg = <0xef600a00 0x000000c4>;
247 local-mac-address = [000000000000]; /* Filled in by U-Boot */
248 mal-device = <&MAL0>;
249 mal-tx-channel = <1>;
250 mal-rx-channel = <1>;
251 cell-index = <1>;
252 max-frame-size = <9000>;
253 rx-fifo-size = <4096>;
254 tx-fifo-size = <2048>;
255 phy-mode = "rgmii";
256 phy-map = <0x00000000>;
257 rgmii-device = <&RGMII0>;
258 rgmii-channel = <1>;
259 has-inverted-stacr-oc;
260 has-new-stacr-staopc;
261 };
262 };
264 PCIE0: pciex@0a0000000 {
265 device_type = "pci";
266 #interrupt-cells = <1>;
267 #size-cells = <2>;
268 #address-cells = <3>;
269 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
270 primary;
271 port = <0x0>; /* port number */
272 reg = <0xa0000000 0x20000000 /* Config space access */
273 0xef000000 0x00001000>; /* Registers */
274 dcr-reg = <0x040 0x020>;
275 sdr-base = <0x400>;
277 /* Outbound ranges, one memory and one IO,
278 * later cannot be changed
279 */
280 ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
281 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
283 /* Inbound 2GB range starting at 0 */
284 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
286 /* This drives busses 0x00 to 0x3f */
287 bus-range = <0x0 0x3f>;
289 /* Legacy interrupts (note the weird polarity, the bridge seems
290 * to invert PCIe legacy interrupts).
291 * We are de-swizzling here because the numbers are actually for
292 * port of the root complex virtual P2P bridge. But I want
293 * to avoid putting a node for it in the tree, so the numbers
294 * below are basically de-swizzled numbers.
295 * The real slot is on idsel 0, so the swizzling is 1:1
296 */
297 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
298 interrupt-map = <
299 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
300 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
301 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
302 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
303 };
305 PCIE1: pciex@0c0000000 {
306 device_type = "pci";
307 #interrupt-cells = <1>;
308 #size-cells = <2>;
309 #address-cells = <3>;
310 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
311 primary;
312 port = <0x1>; /* port number */
313 reg = <0xc0000000 0x20000000 /* Config space access */
314 0xef001000 0x00001000>; /* Registers */
315 dcr-reg = <0x060 0x020>;
316 sdr-base = <0x440>;
318 /* Outbound ranges, one memory and one IO,
319 * later cannot be changed
320 */
321 ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
322 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
324 /* Inbound 2GB range starting at 0 */
325 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
327 /* This drives busses 0x40 to 0x7f */
328 bus-range = <0x40 0x7f>;
330 /* Legacy interrupts (note the weird polarity, the bridge seems
331 * to invert PCIe legacy interrupts).
332 * We are de-swizzling here because the numbers are actually for
333 * port of the root complex virtual P2P bridge. But I want
334 * to avoid putting a node for it in the tree, so the numbers
335 * below are basically de-swizzled numbers.
336 * The real slot is on idsel 0, so the swizzling is 1:1
337 */
338 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
339 interrupt-map = <
340 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
341 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
342 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
343 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
344 };
345 };
346 };