| blob | 9568bfaff8f74aab49f18c3526edbfa5655b9a13 |
1 /*
2 * MPC8540 ADS Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8540ADS";
16 compatible = "MPC8540ADS", "MPC85xxADS";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 };
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
33 PowerPC,8540@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 timebase-frequency = <0>; // 33 MHz, from uboot
41 bus-frequency = <0>; // 166 MHz
42 clock-frequency = <0>; // 825 MHz, from uboot
43 next-level-cache = <&L2>;
44 };
45 };
47 memory {
48 device_type = "memory";
49 reg = <0x0 0x8000000>; // 128M at 0x0
50 };
52 soc8540@e0000000 {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 device_type = "soc";
56 compatible = "simple-bus";
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x100000>; // CCSRBAR 1M
59 bus-frequency = <0>;
61 memory-controller@2000 {
62 compatible = "fsl,8540-memory-controller";
63 reg = <0x2000 0x1000>;
64 interrupt-parent = <&mpic>;
65 interrupts = <18 2>;
66 };
68 L2: l2-cache-controller@20000 {
69 compatible = "fsl,8540-l2-cache-controller";
70 reg = <0x20000 0x1000>;
71 cache-line-size = <32>; // 32 bytes
72 cache-size = <0x40000>; // L2, 256K
73 interrupt-parent = <&mpic>;
74 interrupts = <16 2>;
75 };
77 i2c@3000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <0>;
81 compatible = "fsl-i2c";
82 reg = <0x3000 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86 };
88 dma@21300 {
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
92 reg = <0x21300 0x4>;
93 ranges = <0x0 0x21100 0x200>;
94 cell-index = <0>;
95 dma-channel@0 {
96 compatible = "fsl,mpc8540-dma-channel",
97 "fsl,eloplus-dma-channel";
98 reg = <0x0 0x80>;
99 cell-index = <0>;
100 interrupt-parent = <&mpic>;
101 interrupts = <20 2>;
102 };
103 dma-channel@80 {
104 compatible = "fsl,mpc8540-dma-channel",
105 "fsl,eloplus-dma-channel";
106 reg = <0x80 0x80>;
107 cell-index = <1>;
108 interrupt-parent = <&mpic>;
109 interrupts = <21 2>;
110 };
111 dma-channel@100 {
112 compatible = "fsl,mpc8540-dma-channel",
113 "fsl,eloplus-dma-channel";
114 reg = <0x100 0x80>;
115 cell-index = <2>;
116 interrupt-parent = <&mpic>;
117 interrupts = <22 2>;
118 };
119 dma-channel@180 {
120 compatible = "fsl,mpc8540-dma-channel",
121 "fsl,eloplus-dma-channel";
122 reg = <0x180 0x80>;
123 cell-index = <3>;
124 interrupt-parent = <&mpic>;
125 interrupts = <23 2>;
126 };
127 };
129 mdio@24520 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "fsl,gianfar-mdio";
133 reg = <0x24520 0x20>;
135 phy0: ethernet-phy@0 {
136 interrupt-parent = <&mpic>;
137 interrupts = <5 1>;
138 reg = <0x0>;
139 device_type = "ethernet-phy";
140 };
141 phy1: ethernet-phy@1 {
142 interrupt-parent = <&mpic>;
143 interrupts = <5 1>;
144 reg = <0x1>;
145 device_type = "ethernet-phy";
146 };
147 phy3: ethernet-phy@3 {
148 interrupt-parent = <&mpic>;
149 interrupts = <7 1>;
150 reg = <0x3>;
151 device_type = "ethernet-phy";
152 };
153 };
155 enet0: ethernet@24000 {
156 cell-index = <0>;
157 device_type = "network";
158 model = "TSEC";
159 compatible = "gianfar";
160 reg = <0x24000 0x1000>;
161 local-mac-address = [ 00 00 00 00 00 00 ];
162 interrupts = <29 2 30 2 34 2>;
163 interrupt-parent = <&mpic>;
164 phy-handle = <&phy0>;
165 };
167 enet1: ethernet@25000 {
168 cell-index = <1>;
169 device_type = "network";
170 model = "TSEC";
171 compatible = "gianfar";
172 reg = <0x25000 0x1000>;
173 local-mac-address = [ 00 00 00 00 00 00 ];
174 interrupts = <35 2 36 2 40 2>;
175 interrupt-parent = <&mpic>;
176 phy-handle = <&phy1>;
177 };
179 enet2: ethernet@26000 {
180 cell-index = <2>;
181 device_type = "network";
182 model = "FEC";
183 compatible = "gianfar";
184 reg = <0x26000 0x1000>;
185 local-mac-address = [ 00 00 00 00 00 00 ];
186 interrupts = <41 2>;
187 interrupt-parent = <&mpic>;
188 phy-handle = <&phy3>;
189 };
191 serial0: serial@4500 {
192 cell-index = <0>;
193 device_type = "serial";
194 compatible = "ns16550";
195 reg = <0x4500 0x100>; // reg base, size
196 clock-frequency = <0>; // should we fill in in uboot?
197 interrupts = <42 2>;
198 interrupt-parent = <&mpic>;
199 };
201 serial1: serial@4600 {
202 cell-index = <1>;
203 device_type = "serial";
204 compatible = "ns16550";
205 reg = <0x4600 0x100>; // reg base, size
206 clock-frequency = <0>; // should we fill in in uboot?
207 interrupts = <42 2>;
208 interrupt-parent = <&mpic>;
209 };
210 mpic: pic@40000 {
211 interrupt-controller;
212 #address-cells = <0>;
213 #interrupt-cells = <2>;
214 reg = <0x40000 0x40000>;
215 compatible = "chrp,open-pic";
216 device_type = "open-pic";
217 };
218 };
220 pci0: pci@e0008000 {
221 cell-index = <0>;
222 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
223 interrupt-map = <
225 /* IDSEL 0x02 */
226 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
227 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
228 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
229 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
231 /* IDSEL 0x03 */
232 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
233 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
234 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
235 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
237 /* IDSEL 0x04 */
238 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
239 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
240 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
241 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
243 /* IDSEL 0x05 */
244 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
245 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
246 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
247 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
249 /* IDSEL 0x0c */
250 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
251 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
252 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
253 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
255 /* IDSEL 0x0d */
256 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
257 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
258 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
259 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
261 /* IDSEL 0x0e */
262 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
263 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
264 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
265 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
267 /* IDSEL 0x0f */
268 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
269 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
270 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
271 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
273 /* IDSEL 0x12 */
274 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
275 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
276 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
277 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
279 /* IDSEL 0x13 */
280 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
281 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
282 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
283 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
285 /* IDSEL 0x14 */
286 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
287 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
288 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
289 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
291 /* IDSEL 0x15 */
292 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
293 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
294 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
295 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
296 interrupt-parent = <&mpic>;
297 interrupts = <24 2>;
298 bus-range = <0 0>;
299 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
300 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
301 clock-frequency = <66666666>;
302 #interrupt-cells = <1>;
303 #size-cells = <2>;
304 #address-cells = <3>;
305 reg = <0xe0008000 0x1000>;
306 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
307 device_type = "pci";
308 };
309 };