| blob | f724d72c7b92db819d2b9229da620938ba6c0104 |
1 /*
2 * MPC8610 HPCD Device Tree Source
3 *
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License Version 2 as published
8 * by the Free Software Foundation.
9 */
11 /dts-v1/;
13 / {
14 model = "MPC8610HPCD";
15 compatible = "fsl,MPC8610HPCD";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 aliases {
20 serial0 = &serial0;
21 serial1 = &serial1;
22 pci0 = &pci0;
23 pci1 = &pci1;
24 pci2 = &pci2;
25 };
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
31 PowerPC,8610@0 {
32 device_type = "cpu";
33 reg = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>; // L1
37 i-cache-size = <32768>; // L1
38 timebase-frequency = <0>; // From uboot
39 bus-frequency = <0>; // From uboot
40 clock-frequency = <0>; // From uboot
41 };
42 };
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x20000000>; // 512M at 0x0
47 };
49 localbus@e0005000 {
50 #address-cells = <2>;
51 #size-cells = <1>;
52 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>;
54 interrupts = <19 2>;
55 interrupt-parent = <&mpic>;
56 ranges = <0 0 0xf8000000 0x08000000
57 1 0 0xf0000000 0x08000000
58 2 0 0xe8400000 0x00008000
59 4 0 0xe8440000 0x00008000
60 5 0 0xe8480000 0x00008000
61 6 0 0xe84c0000 0x00008000
62 3 0 0xe8000000 0x00000020>;
64 flash@0,0 {
65 compatible = "cfi-flash";
66 reg = <0 0 0x8000000>;
67 bank-width = <2>;
68 device-width = <1>;
69 };
71 flash@1,0 {
72 compatible = "cfi-flash";
73 reg = <1 0 0x8000000>;
74 bank-width = <2>;
75 device-width = <1>;
76 };
78 flash@2,0 {
79 compatible = "fsl,mpc8610-fcm-nand",
80 "fsl,elbc-fcm-nand";
81 reg = <2 0 0x8000>;
82 };
84 flash@4,0 {
85 compatible = "fsl,mpc8610-fcm-nand",
86 "fsl,elbc-fcm-nand";
87 reg = <4 0 0x8000>;
88 };
90 flash@5,0 {
91 compatible = "fsl,mpc8610-fcm-nand",
92 "fsl,elbc-fcm-nand";
93 reg = <5 0 0x8000>;
94 };
96 flash@6,0 {
97 compatible = "fsl,mpc8610-fcm-nand",
98 "fsl,elbc-fcm-nand";
99 reg = <6 0 0x8000>;
100 };
102 board-control@3,0 {
103 compatible = "fsl,fpga-pixis";
104 reg = <3 0 0x20>;
105 };
106 };
108 soc@e0000000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 #interrupt-cells = <2>;
112 device_type = "soc";
113 compatible = "fsl,mpc8610-immr", "simple-bus";
114 ranges = <0x0 0xe0000000 0x00100000>;
115 reg = <0xe0000000 0x1000>;
116 bus-frequency = <0>;
118 i2c@3000 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 cell-index = <0>;
122 compatible = "fsl-i2c";
123 reg = <0x3000 0x100>;
124 interrupts = <43 2>;
125 interrupt-parent = <&mpic>;
126 dfsrr;
128 cs4270:codec@4f {
129 compatible = "cirrus,cs4270";
130 reg = <0x4f>;
131 /* MCLK source is a stand-alone oscillator */
132 clock-frequency = <12288000>;
133 };
134 };
136 i2c@3100 {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 cell-index = <1>;
140 compatible = "fsl-i2c";
141 reg = <0x3100 0x100>;
142 interrupts = <43 2>;
143 interrupt-parent = <&mpic>;
144 dfsrr;
145 };
147 serial0: serial@4500 {
148 cell-index = <0>;
149 device_type = "serial";
150 compatible = "ns16550";
151 reg = <0x4500 0x100>;
152 clock-frequency = <0>;
153 interrupts = <42 2>;
154 interrupt-parent = <&mpic>;
155 };
157 serial1: serial@4600 {
158 cell-index = <1>;
159 device_type = "serial";
160 compatible = "ns16550";
161 reg = <0x4600 0x100>;
162 clock-frequency = <0>;
163 interrupts = <42 2>;
164 interrupt-parent = <&mpic>;
165 };
167 display@2c000 {
168 compatible = "fsl,diu";
169 reg = <0x2c000 100>;
170 interrupts = <72 2>;
171 interrupt-parent = <&mpic>;
172 };
174 mpic: interrupt-controller@40000 {
175 interrupt-controller;
176 #address-cells = <0>;
177 #interrupt-cells = <2>;
178 reg = <0x40000 0x40000>;
179 compatible = "chrp,open-pic";
180 device_type = "open-pic";
181 };
183 msi@41600 {
184 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
185 reg = <0x41600 0x80>;
186 msi-available-ranges = <0 0x100>;
187 interrupts = <
188 0xe0 0
189 0xe1 0
190 0xe2 0
191 0xe3 0
192 0xe4 0
193 0xe5 0
194 0xe6 0
195 0xe7 0>;
196 interrupt-parent = <&mpic>;
197 };
199 global-utilities@e0000 {
200 compatible = "fsl,mpc8610-guts";
201 reg = <0xe0000 0x1000>;
202 fsl,has-rstcr;
203 };
205 wdt@e4000 {
206 compatible = "fsl,mpc8610-wdt";
207 reg = <0xe4000 0x100>;
208 };
210 ssi@16000 {
211 compatible = "fsl,mpc8610-ssi";
212 cell-index = <0>;
213 reg = <0x16000 0x100>;
214 interrupt-parent = <&mpic>;
215 interrupts = <62 2>;
216 fsl,mode = "i2s-slave";
217 codec-handle = <&cs4270>;
218 fsl,playback-dma = <&dma00>;
219 fsl,capture-dma = <&dma01>;
220 };
222 ssi@16100 {
223 compatible = "fsl,mpc8610-ssi";
224 cell-index = <1>;
225 reg = <0x16100 0x100>;
226 interrupt-parent = <&mpic>;
227 interrupts = <63 2>;
228 };
230 dma@21300 {
231 #address-cells = <1>;
232 #size-cells = <1>;
233 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
234 cell-index = <0>;
235 reg = <0x21300 0x4>; /* DMA general status register */
236 ranges = <0x0 0x21100 0x200>;
238 dma00: dma-channel@0 {
239 compatible = "fsl,mpc8610-dma-channel",
240 "fsl,ssi-dma-channel";
241 cell-index = <0>;
242 reg = <0x0 0x80>;
243 interrupt-parent = <&mpic>;
244 interrupts = <20 2>;
245 };
246 dma01: dma-channel@1 {
247 compatible = "fsl,mpc8610-dma-channel",
248 "fsl,ssi-dma-channel";
249 cell-index = <1>;
250 reg = <0x80 0x80>;
251 interrupt-parent = <&mpic>;
252 interrupts = <21 2>;
253 };
254 dma-channel@2 {
255 compatible = "fsl,mpc8610-dma-channel",
256 "fsl,eloplus-dma-channel";
257 cell-index = <2>;
258 reg = <0x100 0x80>;
259 interrupt-parent = <&mpic>;
260 interrupts = <22 2>;
261 };
262 dma-channel@3 {
263 compatible = "fsl,mpc8610-dma-channel",
264 "fsl,eloplus-dma-channel";
265 cell-index = <3>;
266 reg = <0x180 0x80>;
267 interrupt-parent = <&mpic>;
268 interrupts = <23 2>;
269 };
270 };
272 dma@c300 {
273 #address-cells = <1>;
274 #size-cells = <1>;
275 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
276 cell-index = <1>;
277 reg = <0xc300 0x4>; /* DMA general status register */
278 ranges = <0x0 0xc100 0x200>;
280 dma-channel@0 {
281 compatible = "fsl,mpc8610-dma-channel",
282 "fsl,eloplus-dma-channel";
283 cell-index = <0>;
284 reg = <0x0 0x80>;
285 interrupt-parent = <&mpic>;
286 interrupts = <76 2>;
287 };
288 dma-channel@1 {
289 compatible = "fsl,mpc8610-dma-channel",
290 "fsl,eloplus-dma-channel";
291 cell-index = <1>;
292 reg = <0x80 0x80>;
293 interrupt-parent = <&mpic>;
294 interrupts = <77 2>;
295 };
296 dma-channel@2 {
297 compatible = "fsl,mpc8610-dma-channel",
298 "fsl,eloplus-dma-channel";
299 cell-index = <2>;
300 reg = <0x100 0x80>;
301 interrupt-parent = <&mpic>;
302 interrupts = <78 2>;
303 };
304 dma-channel@3 {
305 compatible = "fsl,mpc8610-dma-channel",
306 "fsl,eloplus-dma-channel";
307 cell-index = <3>;
308 reg = <0x180 0x80>;
309 interrupt-parent = <&mpic>;
310 interrupts = <79 2>;
311 };
312 };
314 };
316 pci0: pci@e0008000 {
317 cell-index = <0>;
318 compatible = "fsl,mpc8610-pci";
319 device_type = "pci";
320 #interrupt-cells = <1>;
321 #size-cells = <2>;
322 #address-cells = <3>;
323 reg = <0xe0008000 0x1000>;
324 bus-range = <0 0>;
325 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
326 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
327 clock-frequency = <33333333>;
328 interrupt-parent = <&mpic>;
329 interrupts = <24 2>;
330 interrupt-map-mask = <0xf800 0 0 7>;
331 interrupt-map = <
332 /* IDSEL 0x11 */
333 0x8800 0 0 1 &mpic 4 1
334 0x8800 0 0 2 &mpic 5 1
335 0x8800 0 0 3 &mpic 6 1
336 0x8800 0 0 4 &mpic 7 1
338 /* IDSEL 0x12 */
339 0x9000 0 0 1 &mpic 5 1
340 0x9000 0 0 2 &mpic 6 1
341 0x9000 0 0 3 &mpic 7 1
342 0x9000 0 0 4 &mpic 4 1
343 >;
344 };
346 pci1: pcie@e000a000 {
347 cell-index = <1>;
348 compatible = "fsl,mpc8641-pcie";
349 device_type = "pci";
350 #interrupt-cells = <1>;
351 #size-cells = <2>;
352 #address-cells = <3>;
353 reg = <0xe000a000 0x1000>;
354 bus-range = <1 3>;
355 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
356 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
357 clock-frequency = <33333333>;
358 interrupt-parent = <&mpic>;
359 interrupts = <26 2>;
360 interrupt-map-mask = <0xf800 0 0 7>;
362 interrupt-map = <
363 /* IDSEL 0x1b */
364 0xd800 0 0 1 &mpic 2 1
366 /* IDSEL 0x1c*/
367 0xe000 0 0 1 &mpic 1 1
368 0xe000 0 0 2 &mpic 1 1
369 0xe000 0 0 3 &mpic 1 1
370 0xe000 0 0 4 &mpic 1 1
372 /* IDSEL 0x1f */
373 0xf800 0 0 1 &mpic 3 2
374 0xf800 0 0 2 &mpic 0 1
375 >;
377 pcie@0 {
378 reg = <0 0 0 0 0>;
379 #size-cells = <2>;
380 #address-cells = <3>;
381 device_type = "pci";
382 ranges = <0x02000000 0x0 0xa0000000
383 0x02000000 0x0 0xa0000000
384 0x0 0x10000000
385 0x01000000 0x0 0x00000000
386 0x01000000 0x0 0x00000000
387 0x0 0x00100000>;
388 uli1575@0 {
389 reg = <0 0 0 0 0>;
390 #size-cells = <2>;
391 #address-cells = <3>;
392 ranges = <0x02000000 0x0 0xa0000000
393 0x02000000 0x0 0xa0000000
394 0x0 0x10000000
395 0x01000000 0x0 0x00000000
396 0x01000000 0x0 0x00000000
397 0x0 0x00100000>;
399 isa@1e {
400 device_type = "isa";
401 #size-cells = <1>;
402 #address-cells = <2>;
403 reg = <0xf000 0 0 0 0>;
404 ranges = <1 0 0x01000000 0 0
405 0x00001000>;
407 rtc@70 {
408 compatible = "pnpPNP,b00";
409 reg = <1 0x70 2>;
410 };
411 };
412 };
413 };
414 };
416 pci2: pcie@e0009000 {
417 #address-cells = <3>;
418 #size-cells = <2>;
419 #interrupt-cells = <1>;
420 device_type = "pci";
421 compatible = "fsl,mpc8641-pcie";
422 reg = <0xe0009000 0x00001000>;
423 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
424 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
425 bus-range = <0 255>;
426 interrupt-map-mask = <0xf800 0 0 7>;
427 interrupt-map = <0x0000 0 0 1 &mpic 4 1
428 0x0000 0 0 2 &mpic 5 1
429 0x0000 0 0 3 &mpic 6 1
430 0x0000 0 0 4 &mpic 7 1>;
431 interrupt-parent = <&mpic>;
432 interrupts = <25 2>;
433 clock-frequency = <33333333>;
434 };
435 };