2 * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source
4 * Copyright 2006 Pengutronix
5 * Sascha Hauer <s.hauer@pengutronix.de>
6 * Copyright 2007 Pengutronix
7 * Juergen Beisert <j.beisert@pengutronix.de>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
18 model = "phytec,pcm030";
19 compatible = "phytec,pcm030";
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; /* L1, 16K */
33 i-cache-size = <0x4000>; /* L1, 16K */
34 timebase-frequency = <0>; /* From Bootloader */
35 bus-frequency = <0>; /* From Bootloader */
36 clock-frequency = <0>; /* From Bootloader */
41 device_type = "memory";
42 reg = <0x00000000 0x04000000>; /* 64MB */
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0x0 0xf0000000 0x0000c000>;
50 bus-frequency = <0>; /* From bootloader */
51 system-frequency = <0>; /* From bootloader */
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
58 mpc5200_pic: interrupt-controller@500 {
59 /* 5200 interrupts are encoded into two levels; */
61 #interrupt-cells = <3>;
62 device_type = "interrupt-controller";
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
67 timer@600 { /* General Purpose Timer */
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
71 interrupts = <0x1 0x9 0x0>;
72 interrupt-parent = <&mpc5200_pic>;
76 timer@610 { /* General Purpose Timer */
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
80 interrupts = <0x1 0xa 0x0>;
81 interrupt-parent = <&mpc5200_pic>;
84 gpt2: timer@620 { /* General Purpose Timer in GPIO mode */
85 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
88 interrupts = <0x1 0xb 0x0>;
89 interrupt-parent = <&mpc5200_pic>;
94 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
95 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
98 interrupts = <0x1 0xc 0x0>;
99 interrupt-parent = <&mpc5200_pic>;
104 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
108 interrupts = <0x1 0xd 0x0>;
109 interrupt-parent = <&mpc5200_pic>;
114 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
115 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
118 interrupts = <0x1 0xe 0x0>;
119 interrupt-parent = <&mpc5200_pic>;
124 gpt6: timer@660 { /* General Purpose Timer in GPIO mode */
125 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
128 interrupts = <0x1 0xf 0x0>;
129 interrupt-parent = <&mpc5200_pic>;
134 gpt7: timer@670 { /* General Purpose Timer in GPIO mode */
135 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
138 interrupts = <0x1 0x10 0x0>;
139 interrupt-parent = <&mpc5200_pic>;
144 rtc@800 { // Real time clock
145 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
148 interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>;
149 interrupt-parent = <&mpc5200_pic>;
153 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
155 interrupts = <0x2 0x11 0x0>;
156 interrupt-parent = <&mpc5200_pic>;
161 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
163 interrupts = <0x2 0x12 0x0>;
164 interrupt-parent = <&mpc5200_pic>;
168 gpio_simple: gpio@b00 {
169 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
171 interrupts = <0x1 0x7 0x0>;
172 interrupt-parent = <&mpc5200_pic>;
177 gpio_wkup: gpio-wkup@c00 {
178 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
180 interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>;
181 interrupt-parent = <&mpc5200_pic>;
187 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
189 interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>;
190 interrupt-parent = <&mpc5200_pic>;
194 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
196 interrupts = <0x2 0x6 0x0>;
197 interrupt-parent = <&mpc5200_pic>;
200 dma-controller@1200 {
201 device_type = "dma-controller";
202 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
204 interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0
205 0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0
206 0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0
207 0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>;
208 interrupt-parent = <&mpc5200_pic>;
212 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
213 reg = <0x1f00 0x100>;
216 ac97@2000 { /* PSC1 in ac97 mode */
217 device_type = "sound";
218 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
220 reg = <0x2000 0x100>;
221 interrupts = <0x2 0x2 0x0>;
222 interrupt-parent = <&mpc5200_pic>;
225 /* PSC2 port is used by CAN1/2 */
227 serial@2400 { /* PSC3 in UART mode */
228 device_type = "serial";
229 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
232 reg = <0x2400 0x100>;
233 interrupts = <0x2 0x3 0x0>;
234 interrupt-parent = <&mpc5200_pic>;
241 serial@2c00 { /* PSC6 in UART mode */
242 device_type = "serial";
243 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
246 reg = <0x2c00 0x100>;
247 interrupts = <0x2 0x4 0x0>;
248 interrupt-parent = <&mpc5200_pic>;
252 device_type = "network";
253 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
254 reg = <0x3000 0x400>;
255 local-mac-address = [00 00 00 00 00 00];
256 interrupts = <0x2 0x5 0x0>;
257 interrupt-parent = <&mpc5200_pic>;
258 phy-handle = <&phy0>;
262 #address-cells = <1>;
264 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
265 reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */
266 interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */
267 interrupt-parent = <&mpc5200_pic>;
269 phy0:ethernet-phy@0 {
270 device_type = "ethernet-phy";
277 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
278 reg = <0x3a00 0x100>;
279 interrupts = <0x2 0x7 0x0>;
280 interrupt-parent = <&mpc5200_pic>;
284 #address-cells = <1>;
286 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
289 interrupts = <0x2 0xf 0x0>;
290 interrupt-parent = <&mpc5200_pic>;
295 #address-cells = <1>;
297 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
300 interrupts = <0x2 0x10 0x0>;
301 interrupt-parent = <&mpc5200_pic>;
305 compatible = "nxp,pcf8563";
312 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
313 reg = <0x8000 0x4000>;
316 /* This is only an example device to show the usage of gpios. It maps all available
317 * gpios to the "gpio-provider" device.
320 compatible = "gpio-provider";
322 /* mpc52xx exp.con patchfield */
323 gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */
324 &gpio_wkup 1 0 /* GPIO_WKUP_6 14c */
325 &gpio_wkup 6 0 /* PSC2_4 43c x5-11 */
326 &gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */
327 &gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */
328 &gpt2 0 0 /* timer2 12d x4-4 */
329 &gpt3 0 0 /* timer3 13d x6-4 */
330 &gpt4 0 0 /* timer4 61c x2-16 */
331 &gpt5 0 0 /* timer5 44c x7-11 */
332 &gpt6 0 0 /* timer6 60c x8-15 */
333 &gpt7 0 0 /* timer7 36a x17-9 */
339 #interrupt-cells = <1>;
341 #address-cells = <3>;
343 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
344 reg = <0xf0000d00 0x100>;
345 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
346 interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */
347 0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3
348 0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3
349 0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3
351 0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */
352 0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3
353 0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3
354 0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>;
355 clock-frequency = <0>; // From boot loader
356 interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>;
357 interrupt-parent = <&mpc5200_pic>;
359 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
360 0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
361 0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>;