arch/powerpc/include/asm/pgtable-ppc32.h

   1 #ifndef _ASM_POWERPC_PGTABLE_PPC32_H
   2 #define _ASM_POWERPC_PGTABLE_PPC32_H
   3
   4 #include <asm-generic/pgtable-nopmd.h>
   5
   6 #ifndef __ASSEMBLY__
   7 #include <linux/sched.h>
   8 #include <linux/threads.h>
   9 #include <asm/io.h>                     /* For sub-arch specific PPC_PIN_SIZE */
  10
  11 extern unsigned long va_to_phys(unsigned long address);
  12 extern pte_t *va_to_pte(unsigned long address);
  13 extern unsigned long ioremap_bot, ioremap_base;
  14
  15 #ifdef CONFIG_44x
  16 extern int icache_44x_need_flush;
  17 #endif
  18
  19 #endif /* __ASSEMBLY__ */
  20
  21 /*
  22  * The PowerPC MMU uses a hash table containing PTEs, together with
  23  * a set of 16 segment registers (on 32-bit implementations), to define
  24  * the virtual to physical address mapping.
  25  *
  26  * We use the hash table as an extended TLB, i.e. a cache of currently
  27  * active mappings.  We maintain a two-level page table tree, much
  28  * like that used by the i386, for the sake of the Linux memory
  29  * management code.  Low-level assembler code in hashtable.S
  30  * (procedure hash_page) is responsible for extracting ptes from the
  31  * tree and putting them into the hash table when necessary, and
  32  * updating the accessed and modified bits in the page table tree.
  33  */
  34
  35 /*
  36  * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
  37  * We also use the two level tables, but we can put the real bits in them
  38  * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
  39  * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
  40  * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
  41  * based upon user/super access.  The TLB does not have accessed nor write
  42  * protect.  We assume that if the TLB get loaded with an entry it is
  43  * accessed, and overload the changed bit for write protect.  We use
  44  * two bits in the software pte that are supposed to be set to zero in
  45  * the TLB entry (24 and 25) for these indicators.  Although the level 1
  46  * descriptor contains the guarded and writethrough/copyback bits, we can
  47  * set these at the page level since they get copied from the Mx_TWC
  48  * register when the TLB entry is loaded.  We will use bit 27 for guard, since
  49  * that is where it exists in the MD_TWC, and bit 26 for writethrough.
  50  * These will get masked from the level 2 descriptor at TLB load time, and
  51  * copied to the MD_TWC before it gets loaded.
  52  * Large page sizes added.  We currently support two sizes, 4K and 8M.
  53  * This also allows a TLB hander optimization because we can directly
  54  * load the PMD into MD_TWC.  The 8M pages are only used for kernel
  55  * mapping of well known areas.  The PMD (PGD) entries contain control
  56  * flags in addition to the address, so care must be taken that the
  57  * software no longer assumes these are only pointers.
  58  */
  59
  60 /*
  61  * At present, all PowerPC 400-class processors share a similar TLB
  62  * architecture. The instruction and data sides share a unified,
  63  * 64-entry, fully-associative TLB which is maintained totally under
  64  * software control. In addition, the instruction side has a
  65  * hardware-managed, 4-entry, fully-associative TLB which serves as a
  66  * first level to the shared TLB. These two TLBs are known as the UTLB
  67  * and ITLB, respectively (see "mmu.h" for definitions).
  68  */
  69
  70 /*
  71  * The normal case is that PTEs are 32-bits and we have a 1-page
  72  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
  73  *
  74  * For any >32-bit physical address platform, we can use the following
  75  * two level page table layout where the pgdir is 8KB and the MS 13 bits
  76  * are an index to the second level table.  The combined pgdir/pmd first
  77  * level has 2048 entries and the second level has 512 64-bit PTE entries.
  78  * -Matt
  79  */
  80 /* PGDIR_SHIFT determines what a top-level page table entry can map */
  81 #define PGDIR_SHIFT     (PAGE_SHIFT + PTE_SHIFT)
  82 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  83 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  84
  85 /*
  86  * entries per page directory level: our page-table tree is two-level, so
  87  * we don't really have any PMD directory.
  88  */
  89 #ifndef __ASSEMBLY__
  90 #define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_SHIFT)
  91 #define PGD_TABLE_SIZE  (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
  92 #endif  /* __ASSEMBLY__ */
  93
  94 #define PTRS_PER_PTE    (1 << PTE_SHIFT)
  95 #define PTRS_PER_PMD    1
  96 #define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
  97
  98 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
  99 #define FIRST_USER_ADDRESS      0
 100
 101 #define pte_ERROR(e) \
 102         printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
 103                 (unsigned long long)pte_val(e))
 104 #define pgd_ERROR(e) \
 105         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 106
 107 /*
 108  * Just any arbitrary offset to the start of the vmalloc VM area: the
 109  * current 64MB value just means that there will be a 64MB "hole" after the
 110  * physical memory until the kernel virtual memory starts.  That means that
 111  * any out-of-bounds memory accesses will hopefully be caught.
 112  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 113  * area for the same reason. ;)
 114  *
 115  * We no longer map larger than phys RAM with the BATs so we don't have
 116  * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
 117  * about clashes between our early calls to ioremap() that start growing down
 118  * from ioremap_base being run into the VM area allocations (growing upwards
 119  * from VMALLOC_START).  For this reason we have ioremap_bot to check when
 120  * we actually run into our mappings setup in the early boot with the VM
 121  * system.  This really does become a problem for machines with good amounts
 122  * of RAM.  -- Cort
 123  */
 124 #define VMALLOC_OFFSET (0x1000000) /* 16M */
 125 #ifdef PPC_PIN_SIZE
 126 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 127 #else
 128 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 129 #endif
 130 #define VMALLOC_END     ioremap_bot
 131
 132 /*
 133  * Bits in a linux-style PTE.  These match the bits in the
 134  * (hardware-defined) PowerPC PTE as closely as possible.
 135  */
 136
 137 #if defined(CONFIG_40x)
 138
 139 /* There are several potential gotchas here.  The 40x hardware TLBLO
 140    field looks like this:
 141
 142    0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 143    RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
 144
 145    Where possible we make the Linux PTE bits match up with this
 146
 147    - bits 20 and 21 must be cleared, because we use 4k pages (40x can
 148      support down to 1k pages), this is done in the TLBMiss exception
 149      handler.
 150    - We use only zones 0 (for kernel pages) and 1 (for user pages)
 151      of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
 152      miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
 153      zone.
 154    - PRESENT *must* be in the bottom two bits because swap cache
 155      entries use the top 30 bits.  Because 40x doesn't support SMP
 156      anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
 157      is cleared in the TLB miss handler before the TLB entry is loaded.
 158    - All other bits of the PTE are loaded into TLBLO without
 159      modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
 160      software PTE bits.  We actually use use bits 21, 24, 25, and
 161      30 respectively for the software bits: ACCESSED, DIRTY, RW, and
 162      PRESENT.
 163 */
 164
 165 /* Definitions for 40x embedded chips. */
 166 #define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
 167 #define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
 168 #define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
 169 #define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
 170 #define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
 171 #define _PAGE_USER      0x010   /* matches one of the zone permission bits */
 172 #define _PAGE_RW        0x040   /* software: Writes permitted */
 173 #define _PAGE_DIRTY     0x080   /* software: dirty page */
 174 #define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
 175 #define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
 176 #define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
 177
 178 #define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
 179 #define _PMD_BAD        0x802
 180 #define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
 181 #define _PMD_SIZE_4M    0x0c0
 182 #define _PMD_SIZE_16M   0x0e0
 183 #define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
 184
 185 /* Until my rework is finished, 40x still needs atomic PTE updates */
 186 #define PTE_ATOMIC_UPDATES      1
 187
 188 #elif defined(CONFIG_44x)
 189 /*
 190  * Definitions for PPC440
 191  *
 192  * Because of the 3 word TLB entries to support 36-bit addressing,
 193  * the attribute are difficult to map in such a fashion that they
 194  * are easily loaded during exception processing.  I decided to
 195  * organize the entry so the ERPN is the only portion in the
 196  * upper word of the PTE and the attribute bits below are packed
 197  * in as sensibly as they can be in the area below a 4KB page size
 198  * oriented RPN.  This at least makes it easy to load the RPN and
 199  * ERPN fields in the TLB. -Matt
 200  *
 201  * Note that these bits preclude future use of a page size
 202  * less than 4KB.
 203  *
 204  *
 205  * PPC 440 core has following TLB attribute fields;
 206  *
 207  *   TLB1:
 208  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 209  *   RPN.................................  -  -  -  -  -  - ERPN.......
 210  *
 211  *   TLB2:
 212  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 213  *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
 214  *
 215  * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
 216  * TLB2 storage attibute fields. Those are:
 217  *
 218  *   TLB2:
 219  *   0...10    11   12   13   14   15   16...31
 220  *   no change WL1  IL1I IL1D IL2I IL2D no change
 221  *
 222  * There are some constrains and options, to decide mapping software bits
 223  * into TLB entry.
 224  *
 225  *   - PRESENT *must* be in the bottom three bits because swap cache
 226  *     entries use the top 29 bits for TLB2.
 227  *
 228  *   - FILE *must* be in the bottom three bits because swap cache
 229  *     entries use the top 29 bits for TLB2.
 230  *
 231  *   - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
 232  *     doesn't support SMP. So we can use this as software bit, like
 233  *     DIRTY.
 234  *
 235  * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
 236  * for memory protection related functions (see PTE structure in
 237  * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
 238  * above bits.  Note that the bit values are CPU specific, not architecture
 239  * specific.
 240  *
 241  * The kernel PTE entry holds an arch-dependent swp_entry structure under
 242  * certain situations. In other words, in such situations some portion of
 243  * the PTE bits are used as a swp_entry. In the PPC implementation, the
 244  * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
 245  * hold protection values. That means the three protection bits are
 246  * reserved for both PTE and SWAP entry at the most significant three
 247  * LSBs.
 248  *
 249  * There are three protection bits available for SWAP entry:
 250  *      _PAGE_PRESENT
 251  *      _PAGE_FILE
 252  *      _PAGE_HASHPTE (if HW has)
 253  *
 254  * So those three bits have to be inside of 0-2nd LSB of PTE.
 255  *
 256  */
 257
 258 #define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
 259 #define _PAGE_RW        0x00000002              /* S: Write permission */
 260 #define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
 261 #define _PAGE_HWEXEC    0x00000004              /* H: Execute permission */
 262 #define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
 263 #define _PAGE_DIRTY     0x00000010              /* S: Page dirty */
 264 #define _PAGE_SPECIAL   0x00000020              /* S: Special page */
 265 #define _PAGE_USER      0x00000040              /* S: User page */
 266 #define _PAGE_ENDIAN    0x00000080              /* H: E bit */
 267 #define _PAGE_GUARDED   0x00000100              /* H: G bit */
 268 #define _PAGE_COHERENT  0x00000200              /* H: M bit */
 269 #define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
 270 #define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
 271
 272 /* TODO: Add large page lowmem mapping support */
 273 #define _PMD_PRESENT    0
 274 #define _PMD_PRESENT_MASK (PAGE_MASK)
 275 #define _PMD_BAD        (~PAGE_MASK)
 276
 277 /* ERPN in a PTE never gets cleared, ignore it */
 278 #define _PTE_NONE_MASK  0xffffffff00000000ULL
 279
 280 #define __HAVE_ARCH_PTE_SPECIAL
 281
 282 #elif defined(CONFIG_FSL_BOOKE)
 283 /*
 284    MMU Assist Register 3:
 285
 286    32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
 287    RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
 288
 289    - PRESENT *must* be in the bottom three bits because swap cache
 290      entries use the top 29 bits.
 291
 292    - FILE *must* be in the bottom three bits because swap cache
 293      entries use the top 29 bits.
 294 */
 295
 296 /* Definitions for FSL Book-E Cores */
 297 #define _PAGE_PRESENT   0x00001 /* S: PTE contains a translation */
 298 #define _PAGE_USER      0x00002 /* S: User page (maps to UR) */
 299 #define _PAGE_FILE      0x00002 /* S: when !present: nonlinear file mapping */
 300 #define _PAGE_RW        0x00004 /* S: Write permission (SW) */
 301 #define _PAGE_DIRTY     0x00008 /* S: Page dirty */
 302 #define _PAGE_HWEXEC    0x00010 /* H: SX permission */
 303 #define _PAGE_ACCESSED  0x00020 /* S: Page referenced */
 304
 305 #define _PAGE_ENDIAN    0x00040 /* H: E bit */
 306 #define _PAGE_GUARDED   0x00080 /* H: G bit */
 307 #define _PAGE_COHERENT  0x00100 /* H: M bit */
 308 #define _PAGE_NO_CACHE  0x00200 /* H: I bit */
 309 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
 310 #define _PAGE_SPECIAL   0x00800 /* S: Special page */
 311
 312 #ifdef CONFIG_PTE_64BIT
 313 /* ERPN in a PTE never gets cleared, ignore it */
 314 #define _PTE_NONE_MASK  0xffffffffffff0000ULL
 315 #endif
 316
 317 #define _PMD_PRESENT    0
 318 #define _PMD_PRESENT_MASK (PAGE_MASK)
 319 #define _PMD_BAD        (~PAGE_MASK)
 320
 321 #define __HAVE_ARCH_PTE_SPECIAL
 322
 323 #elif defined(CONFIG_8xx)
 324 /* Definitions for 8xx embedded chips. */
 325 #define _PAGE_PRESENT   0x0001  /* Page is valid */
 326 #define _PAGE_FILE      0x0002  /* when !present: nonlinear file mapping */
 327 #define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
 328 #define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
 329
 330 /* These five software bits must be masked out when the entry is loaded
 331  * into the TLB.
 332  */
 333 #define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
 334 #define _PAGE_GUARDED   0x0010  /* software: guarded access */
 335 #define _PAGE_DIRTY     0x0020  /* software: page changed */
 336 #define _PAGE_RW        0x0040  /* software: user write access allowed */
 337 #define _PAGE_ACCESSED  0x0080  /* software: page referenced */
 338
 339 /* Setting any bits in the nibble with the follow two controls will
 340  * require a TLB exception handler change.  It is assumed unused bits
 341  * are always zero.
 342  */
 343 #define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
 344 #define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
 345
 346 #define _PMD_PRESENT    0x0001
 347 #define _PMD_BAD        0x0ff0
 348 #define _PMD_PAGE_MASK  0x000c
 349 #define _PMD_PAGE_8M    0x000c
 350
 351 #define _PTE_NONE_MASK _PAGE_ACCESSED
 352
 353 /* Until my rework is finished, 8xx still needs atomic PTE updates */
 354 #define PTE_ATOMIC_UPDATES      1
 355
 356 #else /* CONFIG_6xx */
 357 /* Definitions for 60x, 740/750, etc. */
 358 #define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
 359 #define _PAGE_HASHPTE   0x002   /* hash_page has made an HPTE for this pte */
 360 #define _PAGE_FILE      0x004   /* when !present: nonlinear file mapping */
 361 #define _PAGE_USER      0x004   /* usermode access allowed */
 362 #define _PAGE_GUARDED   0x008   /* G: prohibit speculative access */
 363 #define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
 364 #define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
 365 #define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
 366 #define _PAGE_DIRTY     0x080   /* C: page changed */
 367 #define _PAGE_ACCESSED  0x100   /* R: page referenced */
 368 #define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
 369 #define _PAGE_RW        0x400   /* software: user write access allowed */
 370 #define _PAGE_SPECIAL   0x800   /* software: Special page */
 371
 372 #ifdef CONFIG_PTE_64BIT
 373 /* We never clear the high word of the pte */
 374 #define _PTE_NONE_MASK  (0xffffffff00000000ULL | _PAGE_HASHPTE)
 375 #else
 376 #define _PTE_NONE_MASK  _PAGE_HASHPTE
 377 #endif
 378
 379 #define _PMD_PRESENT    0
 380 #define _PMD_PRESENT_MASK (PAGE_MASK)
 381 #define _PMD_BAD        (~PAGE_MASK)
 382
 383 /* Hash table based platforms need atomic updates of the linux PTE */
 384 #define PTE_ATOMIC_UPDATES      1
 385
 386 #define __HAVE_ARCH_PTE_SPECIAL
 387
 388 #endif
 389
 390 /*
 391  * Some bits are only used on some cpu families...
 392  */
 393 #ifndef _PAGE_HASHPTE
 394 #define _PAGE_HASHPTE   0
 395 #endif
 396 #ifndef _PTE_NONE_MASK
 397 #define _PTE_NONE_MASK 0
 398 #endif
 399 #ifndef _PAGE_SHARED
 400 #define _PAGE_SHARED    0
 401 #endif
 402 #ifndef _PAGE_HWWRITE
 403 #define _PAGE_HWWRITE   0
 404 #endif
 405 #ifndef _PAGE_HWEXEC
 406 #define _PAGE_HWEXEC    0
 407 #endif
 408 #ifndef _PAGE_EXEC
 409 #define _PAGE_EXEC      0
 410 #endif
 411 #ifndef _PAGE_ENDIAN
 412 #define _PAGE_ENDIAN    0
 413 #endif
 414 #ifndef _PAGE_COHERENT
 415 #define _PAGE_COHERENT  0
 416 #endif
 417 #ifndef _PAGE_WRITETHRU
 418 #define _PAGE_WRITETHRU 0
 419 #endif
 420 #ifndef _PAGE_SPECIAL
 421 #define _PAGE_SPECIAL   0
 422 #endif
 423 #ifndef _PMD_PRESENT_MASK
 424 #define _PMD_PRESENT_MASK       _PMD_PRESENT
 425 #endif
 426 #ifndef _PMD_SIZE
 427 #define _PMD_SIZE       0
 428 #define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
 429 #endif
 430
 431 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 432
 433
 434 #define PAGE_PROT_BITS  (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
 435                          _PAGE_WRITETHRU | _PAGE_ENDIAN | \
 436                          _PAGE_USER | _PAGE_ACCESSED | \
 437                          _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
 438                          _PAGE_EXEC | _PAGE_HWEXEC)
 439 /*
 440  * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
 441  * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
 442  * to have it in the Linux PTE, and in fact the bit could be reused for
 443  * another purpose.  -- paulus.
 444  */
 445
 446 #ifdef CONFIG_44x
 447 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
 448 #else
 449 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
 450 #endif
 451 #define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
 452 #define _PAGE_KERNEL    (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
 453
 454 #ifdef CONFIG_PPC_STD_MMU
 455 /* On standard PPC MMU, no user access implies kernel read/write access,
 456  * so to write-protect kernel memory we must turn on user access */
 457 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
 458 #else
 459 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
 460 #endif
 461
 462 #define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
 463 #define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
 464
 465 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
 466         defined(CONFIG_KPROBES)
 467 /* We want the debuggers to be able to set breakpoints anywhere, so
 468  * don't write protect the kernel text */
 469 #define _PAGE_RAM_TEXT  _PAGE_RAM
 470 #else
 471 #define _PAGE_RAM_TEXT  (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
 472 #endif
 473
 474 #define PAGE_NONE       __pgprot(_PAGE_BASE)
 475 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
 476 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 477 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
 478 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
 479 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
 480 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 481
 482 #define PAGE_KERNEL             __pgprot(_PAGE_RAM)
 483 #define PAGE_KERNEL_NOCACHE     __pgprot(_PAGE_IO)
 484
 485 /*
 486  * The PowerPC can only do execute protection on a segment (256MB) basis,
 487  * not on a page basis.  So we consider execute permission the same as read.
 488  * Also, write permissions imply read permissions.
 489  * This is the closest we can get..
 490  */
 491 #define __P000  PAGE_NONE
 492 #define __P001  PAGE_READONLY_X
 493 #define __P010  PAGE_COPY
 494 #define __P011  PAGE_COPY_X
 495 #define __P100  PAGE_READONLY
 496 #define __P101  PAGE_READONLY_X
 497 #define __P110  PAGE_COPY
 498 #define __P111  PAGE_COPY_X
 499
 500 #define __S000  PAGE_NONE
 501 #define __S001  PAGE_READONLY_X
 502 #define __S010  PAGE_SHARED
 503 #define __S011  PAGE_SHARED_X
 504 #define __S100  PAGE_READONLY
 505 #define __S101  PAGE_READONLY_X
 506 #define __S110  PAGE_SHARED
 507 #define __S111  PAGE_SHARED_X
 508
 509 #ifndef __ASSEMBLY__
 510 /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
 511  * kernel without large page PMD support */
 512 extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
 513
 514 /*
 515  * Conversions between PTE values and page frame numbers.
 516  */
 517
 518 /* in some case we want to additionaly adjust where the pfn is in the pte to
 519  * allow room for more flags */
 520 #if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
 521 #define PFN_SHIFT_OFFSET        (PAGE_SHIFT + 8)
 522 #else
 523 #define PFN_SHIFT_OFFSET        (PAGE_SHIFT)
 524 #endif
 525
 526 #define pte_pfn(x)              (pte_val(x) >> PFN_SHIFT_OFFSET)
 527 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 528
 529 #define pfn_pte(pfn, prot)      __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
 530                                         pgprot_val(prot))
 531 #define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 532 #endif /* __ASSEMBLY__ */
 533
 534 #define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
 535 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
 536 #define pte_clear(mm, addr, ptep) \
 537         do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
 538
 539 #define pmd_none(pmd)           (!pmd_val(pmd))
 540 #define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
 541 #define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
 542 #define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
 543
 544 #ifndef __ASSEMBLY__
 545 /*
 546  * The following only work if pte_present() is true.
 547  * Undefined behaviour if not..
 548  */
 549 static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
 550 static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 551 static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 552 static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
 553 static inline int pte_special(pte_t pte)        { return pte_val(pte) & _PAGE_SPECIAL; }
 554
 555 static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
 556 static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
 557
 558 static inline pte_t pte_wrprotect(pte_t pte) {
 559         pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
 560 static inline pte_t pte_mkclean(pte_t pte) {
 561         pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
 562 static inline pte_t pte_mkold(pte_t pte) {
 563         pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 564
 565 static inline pte_t pte_mkwrite(pte_t pte) {
 566         pte_val(pte) |= _PAGE_RW; return pte; }
 567 static inline pte_t pte_mkdirty(pte_t pte) {
 568         pte_val(pte) |= _PAGE_DIRTY; return pte; }
 569 static inline pte_t pte_mkyoung(pte_t pte) {
 570         pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 571 static inline pte_t pte_mkspecial(pte_t pte) {
 572         pte_val(pte) |= _PAGE_SPECIAL; return pte; }
 573 static inline pgprot_t pte_pgprot(pte_t pte)
 574 {
 575         return __pgprot(pte_val(pte) & PAGE_PROT_BITS);
 576 }
 577
 578 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 579 {
 580         pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
 581         return pte;
 582 }
 583
 584 /*
 585  * When flushing the tlb entry for a page, we also need to flush the hash
 586  * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
 587  */
 588 extern int flush_hash_pages(unsigned context, unsigned long va,
 589                             unsigned long pmdval, int count);
 590
 591 /* Add an HPTE to the hash table */
 592 extern void add_hash_page(unsigned context, unsigned long va,
 593                           unsigned long pmdval);
 594
 595 /* Flush an entry from the TLB/hash table */
 596 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
 597                              unsigned long address);
 598
 599 /*
 600  * Atomic PTE updates.
 601  *
 602  * pte_update clears and sets bit atomically, and returns
 603  * the old pte value.  In the 64-bit PTE case we lock around the
 604  * low PTE word since we expect ALL flag bits to be there
 605  */
 606 #ifndef CONFIG_PTE_64BIT
 607 static inline unsigned long pte_update(pte_t *p,
 608                                        unsigned long clr,
 609                                        unsigned long set)
 610 {
 611 #ifdef PTE_ATOMIC_UPDATES
 612         unsigned long old, tmp;
 613
 614         __asm__ __volatile__("\
 615 1:      lwarx   %0,0,%3\n\
 616         andc    %1,%0,%4\n\
 617         or      %1,%1,%5\n"
 618         PPC405_ERR77(0,%3)
 619 "       stwcx.  %1,0,%3\n\
 620         bne-    1b"
 621         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 622         : "r" (p), "r" (clr), "r" (set), "m" (*p)
 623         : "cc" );
 624 #else /* PTE_ATOMIC_UPDATES */
 625         unsigned long old = pte_val(*p);
 626         *p = __pte((old & ~clr) | set);
 627 #endif /* !PTE_ATOMIC_UPDATES */
 628
 629 #ifdef CONFIG_44x
 630         if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
 631                 icache_44x_need_flush = 1;
 632 #endif
 633         return old;
 634 }
 635 #else /* CONFIG_PTE_64BIT */
 636 static inline unsigned long long pte_update(pte_t *p,
 637                                             unsigned long clr,
 638                                             unsigned long set)
 639 {
 640 #ifdef PTE_ATOMIC_UPDATES
 641         unsigned long long old;
 642         unsigned long tmp;
 643
 644         __asm__ __volatile__("\
 645 1:      lwarx   %L0,0,%4\n\
 646         lwzx    %0,0,%3\n\
 647         andc    %1,%L0,%5\n\
 648         or      %1,%1,%6\n"
 649         PPC405_ERR77(0,%3)
 650 "       stwcx.  %1,0,%4\n\
 651         bne-    1b"
 652         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 653         : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
 654         : "cc" );
 655 #else /* PTE_ATOMIC_UPDATES */
 656         unsigned long long old = pte_val(*p);
 657         *p = __pte((old & ~(unsigned long long)clr) | set);
 658 #endif /* !PTE_ATOMIC_UPDATES */
 659
 660 #ifdef CONFIG_44x
 661         if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
 662                 icache_44x_need_flush = 1;
 663 #endif
 664         return old;
 665 }
 666 #endif /* CONFIG_PTE_64BIT */
 667
 668 /*
 669  * set_pte stores a linux PTE into the linux page table.
 670  * On machines which use an MMU hash table we avoid changing the
 671  * _PAGE_HASHPTE bit.
 672  */
 673
 674 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
 675                               pte_t *ptep, pte_t pte)
 676 {
 677 #if (_PAGE_HASHPTE != 0) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
 678         pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
 679 #elif defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)
 680 #if _PAGE_HASHPTE != 0
 681         if (pte_val(*ptep) & _PAGE_HASHPTE)
 682                 flush_hash_entry(mm, ptep, addr);
 683 #endif
 684         __asm__ __volatile__("\
 685                 stw%U0%X0 %2,%0\n\
 686                 eieio\n\
 687                 stw%U0%X0 %L2,%1"
 688         : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
 689         : "r" (pte) : "memory");
 690 #else
 691         *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
 692                       | (pte_val(pte) & ~_PAGE_HASHPTE));
 693 #endif
 694 }
 695
 696 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 697                               pte_t *ptep, pte_t pte)
 698 {
 699 #if defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)
 700         WARN_ON(pte_present(*ptep));
 701 #endif
 702         __set_pte_at(mm, addr, ptep, pte);
 703 }
 704
 705 /*
 706  * 2.6 calls this without flushing the TLB entry; this is wrong
 707  * for our hash-based implementation, we fix that up here.
 708  */
 709 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 710 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
 711 {
 712         unsigned long old;
 713         old = pte_update(ptep, _PAGE_ACCESSED, 0);
 714 #if _PAGE_HASHPTE != 0
 715         if (old & _PAGE_HASHPTE) {
 716                 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
 717                 flush_hash_pages(context, addr, ptephys, 1);
 718         }
 719 #endif
 720         return (old & _PAGE_ACCESSED) != 0;
 721 }
 722 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
 723         __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
 724
 725 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 726 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
 727                                        pte_t *ptep)
 728 {
 729         return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
 730 }
 731
 732 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 733 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 734                                       pte_t *ptep)
 735 {
 736         pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
 737 }
 738 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
 739                                            unsigned long addr, pte_t *ptep)
 740 {
 741         ptep_set_wrprotect(mm, addr, ptep);
 742 }
 743
 744
 745 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 746 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 747 {
 748         unsigned long bits = pte_val(entry) &
 749                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
 750         pte_update(ptep, 0, bits);
 751 }
 752
 753 #define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
 754 ({                                                                         \
 755         int __changed = !pte_same(*(__ptep), __entry);                     \
 756         if (__changed) {                                                   \
 757                 __ptep_set_access_flags(__ptep, __entry, __dirty);         \
 758                 flush_tlb_page_nohash(__vma, __address);                   \
 759         }                                                                  \
 760         __changed;                                                         \
 761 })
 762
 763 /*
 764  * Macro to mark a page protection value as "uncacheable".
 765  */
 766 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 767
 768 struct file;
 769 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 770                                      unsigned long size, pgprot_t vma_prot);
 771 #define __HAVE_PHYS_MEM_ACCESS_PROT
 772
 773 #define __HAVE_ARCH_PTE_SAME
 774 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
 775
 776 /*
 777  * Note that on Book E processors, the pmd contains the kernel virtual
 778  * (lowmem) address of the pte page.  The physical address is less useful
 779  * because everything runs with translation enabled (even the TLB miss
 780  * handler).  On everything else the pmd contains the physical address
 781  * of the pte page.  -- paulus
 782  */
 783 #ifndef CONFIG_BOOKE
 784 #define pmd_page_vaddr(pmd)     \
 785         ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 786 #define pmd_page(pmd)           \
 787         (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
 788 #else
 789 #define pmd_page_vaddr(pmd)     \
 790         ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
 791 #define pmd_page(pmd)           \
 792         pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
 793 #endif
 794
 795 /* to find an entry in a kernel page-table-directory */
 796 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 797
 798 /* to find an entry in a page-table-directory */
 799 #define pgd_index(address)       ((address) >> PGDIR_SHIFT)
 800 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 801
 802 /* Find an entry in the third-level page table.. */
 803 #define pte_index(address)              \
 804         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 805 #define pte_offset_kernel(dir, addr)    \
 806         ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
 807 #define pte_offset_map(dir, addr)               \
 808         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
 809 #define pte_offset_map_nested(dir, addr)        \
 810         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
 811
 812 #define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
 813 #define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
 814
 815 /*
 816  * Encode and decode a swap entry.
 817  * Note that the bits we use in a PTE for representing a swap entry
 818  * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
 819  *_PAGE_HASHPTE bit (if used).  -- paulus
 820  */
 821 #define __swp_type(entry)               ((entry).val & 0x1f)
 822 #define __swp_offset(entry)             ((entry).val >> 5)
 823 #define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
 824 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
 825 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
 826
 827 /* Encode and decode a nonlinear file mapping entry */
 828 #define PTE_FILE_MAX_BITS       29
 829 #define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
 830 #define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
 831
 832 /*
 833  * No page table caches to initialise
 834  */
 835 #define pgtable_cache_init()    do { } while (0)
 836
 837 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
 838                       pmd_t **pmdp);
 839
 840 #endif /* !__ASSEMBLY__ */
 841
 842 #endif /* _ASM_POWERPC_PGTABLE_PPC32_H */