5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
12 #include <asm/pgtable.h>
14 #include <asm/hydra.h>
16 #include <asm/machdep.h>
17 #include <asm/sections.h>
18 #include <asm/pci-bridge.h>
19 #include <asm/grackle.h>
26 void __iomem
*gg2_pci_config_base
;
29 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
30 * limit the bus number to 3 bits
33 int gg2_read_config(struct pci_bus
*bus
, unsigned int devfn
, int off
,
36 volatile void __iomem
*cfg_data
;
37 struct pci_controller
*hose
= bus
->sysdata
;
40 return PCIBIOS_DEVICE_NOT_FOUND
;
42 * Note: the caller has already checked that off is
43 * suitably aligned and that len is 1, 2 or 4.
45 cfg_data
= hose
->cfg_data
+ ((bus
->number
<<16) | (devfn
<<8) | off
);
48 *val
= in_8(cfg_data
);
51 *val
= in_le16(cfg_data
);
54 *val
= in_le32(cfg_data
);
57 return PCIBIOS_SUCCESSFUL
;
60 int gg2_write_config(struct pci_bus
*bus
, unsigned int devfn
, int off
,
63 volatile void __iomem
*cfg_data
;
64 struct pci_controller
*hose
= bus
->sysdata
;
67 return PCIBIOS_DEVICE_NOT_FOUND
;
69 * Note: the caller has already checked that off is
70 * suitably aligned and that len is 1, 2 or 4.
72 cfg_data
= hose
->cfg_data
+ ((bus
->number
<<16) | (devfn
<<8) | off
);
78 out_le16(cfg_data
, val
);
81 out_le32(cfg_data
, val
);
84 return PCIBIOS_SUCCESSFUL
;
87 static struct pci_ops gg2_pci_ops
=
89 .read
= gg2_read_config
,
90 .write
= gg2_write_config
,
94 * Access functions for PCI config space using RTAS calls.
96 int rtas_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
99 struct pci_controller
*hose
= bus
->sysdata
;
100 unsigned long addr
= (offset
& 0xff) | ((devfn
& 0xff) << 8)
101 | (((bus
->number
- hose
->first_busno
) & 0xff) << 16)
102 | (hose
->global_number
<< 24);
106 rval
= rtas_call(rtas_token("read-pci-config"), 2, 2, &ret
, addr
, len
);
108 return rval
? PCIBIOS_DEVICE_NOT_FOUND
: PCIBIOS_SUCCESSFUL
;
111 int rtas_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
114 struct pci_controller
*hose
= bus
->sysdata
;
115 unsigned long addr
= (offset
& 0xff) | ((devfn
& 0xff) << 8)
116 | (((bus
->number
- hose
->first_busno
) & 0xff) << 16)
117 | (hose
->global_number
<< 24);
120 rval
= rtas_call(rtas_token("write-pci-config"), 3, 1, NULL
,
122 return rval
? PCIBIOS_DEVICE_NOT_FOUND
: PCIBIOS_SUCCESSFUL
;
125 static struct pci_ops rtas_pci_ops
=
127 .read
= rtas_read_config
,
128 .write
= rtas_write_config
,
131 volatile struct Hydra __iomem
*Hydra
= NULL
;
136 struct device_node
*np
;
139 np
= of_find_node_by_name(NULL
, "mac-io");
140 if (np
== NULL
|| of_address_to_resource(np
, 0, &r
)) {
144 Hydra
= ioremap(r
.start
, r
.end
-r
.start
);
145 printk("Hydra Mac I/O at %llx\n", (unsigned long long)r
.start
);
146 printk("Hydra Feature_Control was %x",
147 in_le32(&Hydra
->Feature_Control
));
148 out_le32(&Hydra
->Feature_Control
, (HYDRA_FC_SCC_CELL_EN
|
149 HYDRA_FC_SCSI_CELL_EN
|
150 HYDRA_FC_SCCA_ENABLE
|
151 HYDRA_FC_SCCB_ENABLE
|
152 HYDRA_FC_ARB_BYPASS
|
153 HYDRA_FC_MPIC_ENABLE
|
154 HYDRA_FC_SLOW_SCC_PCLK
|
155 HYDRA_FC_MPIC_IS_MASTER
));
156 printk(", now %x\n", in_le32(&Hydra
->Feature_Control
));
160 #define PRG_CL_RESET_VALID 0x00010000
163 setup_python(struct pci_controller
*hose
, struct device_node
*dev
)
169 if (of_address_to_resource(dev
, 0, &r
)) {
170 printk(KERN_ERR
"No address for Python PCI controller\n");
174 /* Clear the magic go-slow bit */
175 reg
= ioremap(r
.start
+ 0xf6000, 0x40);
177 val
= in_be32(®
[12]);
178 if (val
& PRG_CL_RESET_VALID
) {
179 out_be32(®
[12], val
& ~PRG_CL_RESET_VALID
);
184 setup_indirect_pci(hose
, r
.start
+ 0xf8000, r
.start
+ 0xf8010, 0);
187 /* Marvell Discovery II based Pegasos 2 */
188 static void __init
setup_peg2(struct pci_controller
*hose
, struct device_node
*dev
)
190 struct device_node
*root
= of_find_node_by_path("/");
191 struct device_node
*rtas
;
193 rtas
= of_find_node_by_name (root
, "rtas");
195 hose
->ops
= &rtas_pci_ops
;
198 printk ("RTAS supporting Pegasos OF not found, please upgrade"
201 ppc_pci_flags
|= PPC_PCI_REASSIGN_ALL_BUS
;
202 /* keep the reference to the root node */
206 chrp_find_bridges(void)
208 struct device_node
*dev
;
209 const int *bus_range
;
211 struct pci_controller
*hose
;
212 const unsigned int *dma
;
213 const char *model
, *machine
;
214 int is_longtrail
= 0, is_mot
= 0, is_pegasos
= 0;
215 struct device_node
*root
= of_find_node_by_path("/");
218 * The PCI host bridge nodes on some machines don't have
219 * properties to adequately identify them, so we have to
220 * look at what sort of machine this is as well.
222 machine
= of_get_property(root
, "model", NULL
);
223 if (machine
!= NULL
) {
224 is_longtrail
= strncmp(machine
, "IBM,LongTrail", 13) == 0;
225 is_mot
= strncmp(machine
, "MOT", 3) == 0;
226 if (strncmp(machine
, "Pegasos2", 8) == 0)
228 else if (strncmp(machine
, "Pegasos", 7) == 0)
231 for (dev
= root
->child
; dev
!= NULL
; dev
= dev
->sibling
) {
232 if (dev
->type
== NULL
|| strcmp(dev
->type
, "pci") != 0)
235 /* The GG2 bridge on the LongTrail doesn't have an address */
236 if (of_address_to_resource(dev
, 0, &r
) && !is_longtrail
) {
237 printk(KERN_WARNING
"Can't use %s: no address\n",
241 bus_range
= of_get_property(dev
, "bus-range", &len
);
242 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
243 printk(KERN_WARNING
"Can't get bus-range for %s\n",
247 if (bus_range
[1] == bus_range
[0])
248 printk(KERN_INFO
"PCI bus %d", bus_range
[0]);
250 printk(KERN_INFO
"PCI buses %d..%d",
251 bus_range
[0], bus_range
[1]);
252 printk(" controlled by %s", dev
->full_name
);
254 printk(" at %llx", (unsigned long long)r
.start
);
257 hose
= pcibios_alloc_controller(dev
);
259 printk("Can't allocate PCI controller structure for %s\n",
263 hose
->first_busno
= hose
->self_busno
= bus_range
[0];
264 hose
->last_busno
= bus_range
[1];
266 model
= of_get_property(dev
, "model", NULL
);
269 if (strncmp(model
, "IBM, Python", 11) == 0) {
270 setup_python(hose
, dev
);
272 || strncmp(model
, "Motorola, Grackle", 17) == 0) {
274 } else if (is_longtrail
) {
275 void __iomem
*p
= ioremap(GG2_PCI_CONFIG_BASE
, 0x80000);
276 hose
->ops
= &gg2_pci_ops
;
278 gg2_pci_config_base
= p
;
279 } else if (is_pegasos
== 1) {
280 setup_indirect_pci(hose
, 0xfec00cf8, 0xfee00cfc, 0);
281 } else if (is_pegasos
== 2) {
282 setup_peg2(hose
, dev
);
283 } else if (!strncmp(model
, "IBM,CPC710", 10)) {
284 setup_indirect_pci(hose
,
285 r
.start
+ 0x000f8000,
286 r
.start
+ 0x000f8010,
289 dma
= of_get_property(dev
, "system-dma-base",
291 if (dma
&& len
>= sizeof(*dma
)) {
292 dma
= (unsigned int *)
293 (((unsigned long)dma
) +
295 pci_dram_offset
= *dma
;
299 printk("No methods for %s (model %s), using RTAS\n",
300 dev
->full_name
, model
);
301 hose
->ops
= &rtas_pci_ops
;
304 pci_process_bridge_OF_ranges(hose
, dev
, index
== 0);
306 /* check the first bridge for a property that we can
307 use to set pci_dram_offset */
308 dma
= of_get_property(dev
, "ibm,dma-ranges", &len
);
309 if (index
== 0 && dma
!= NULL
&& len
>= 6 * sizeof(*dma
)) {
310 pci_dram_offset
= dma
[2] - dma
[3];
311 printk("pci_dram_offset = %lx\n", pci_dram_offset
);
317 /* SL82C105 IDE Control/Status Register */
318 #define SL82C105_IDECSR 0x40
320 /* Fixup for Winbond ATA quirk, required for briq mostly because the
321 * 8259 is configured for level sensitive IRQ 14 and so wants the
322 * ATA controller to be set to fully native mode or bad things
325 static void __devinit
chrp_pci_fixup_winbond_ata(struct pci_dev
*sl82c105
)
329 /* If non-briq machines need that fixup too, please speak up */
330 if (!machine_is(chrp
) || _chrp_type
!= _CHRP_briq
)
333 if ((sl82c105
->class & 5) != 5) {
334 printk("W83C553: Switching SL82C105 IDE to PCI native mode\n");
335 /* Enable SL82C105 PCI native IDE mode */
336 pci_read_config_byte(sl82c105
, PCI_CLASS_PROG
, &progif
);
337 pci_write_config_byte(sl82c105
, PCI_CLASS_PROG
, progif
| 0x05);
338 sl82c105
->class |= 0x05;
339 /* Disable SL82C105 second port */
340 pci_write_config_word(sl82c105
, SL82C105_IDECSR
, 0x0003);
341 /* Clear IO BARs, they will be reassigned */
342 pci_write_config_dword(sl82c105
, PCI_BASE_ADDRESS_0
, 0);
343 pci_write_config_dword(sl82c105
, PCI_BASE_ADDRESS_1
, 0);
344 pci_write_config_dword(sl82c105
, PCI_BASE_ADDRESS_2
, 0);
345 pci_write_config_dword(sl82c105
, PCI_BASE_ADDRESS_3
, 0);
348 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_WINBOND
, PCI_DEVICE_ID_WINBOND_82C105
,
349 chrp_pci_fixup_winbond_ata
);
351 /* Pegasos2 firmware version 20040810 configures the built-in IDE controller
352 * in legacy mode, but sets the PCI registers to PCI native mode.
353 * The chip can only operate in legacy mode, so force the PCI class into legacy
354 * mode as well. The same fixup must be done to the class-code property in
355 * the IDE node /pci@80000000/ide@C,1
357 static void chrp_pci_fixup_vt8231_ata(struct pci_dev
*viaide
)
360 struct pci_dev
*viaisa
;
362 if (!machine_is(chrp
) || _chrp_type
!= _CHRP_Pegasos
)
364 if (viaide
->irq
!= 14)
367 viaisa
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
370 dev_info(&viaide
->dev
, "Fixing VIA IDE, force legacy mode on\n");
372 pci_read_config_byte(viaide
, PCI_CLASS_PROG
, &progif
);
373 pci_write_config_byte(viaide
, PCI_CLASS_PROG
, progif
& ~0x5);
374 viaide
->class &= ~0x5;
378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_1
, chrp_pci_fixup_vt8231_ata
);