arch/sh/include/asm/pgtable.h

   1 /*
   2  * This file contains the functions and defines necessary to modify and
   3  * use the SuperH page table tree.
   4  *
   5  * Copyright (C) 1999 Niibe Yutaka
   6  * Copyright (C) 2002 - 2007 Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General
   9  * Public License.  See the file "COPYING" in the main directory of this
  10  * archive for more details.
  11  */
  12 #ifndef __ASM_SH_PGTABLE_H
  13 #define __ASM_SH_PGTABLE_H
  14
  15 #include <asm-generic/pgtable-nopmd.h>
  16 #include <asm/page.h>
  17
  18 #ifndef __ASSEMBLY__
  19 #include <asm/addrspace.h>
  20 #include <asm/fixmap.h>
  21
  22 /*
  23  * ZERO_PAGE is a global shared page that is always zero: used
  24  * for zero-mapped memory areas etc..
  25  */
  26 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
  27 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
  28
  29 #endif /* !__ASSEMBLY__ */
  30
  31 /*
  32  * Effective and physical address definitions, to aid with sign
  33  * extension.
  34  */
  35 #define NEFF            32
  36 #define NEFF_SIGN       (1LL << (NEFF - 1))
  37 #define NEFF_MASK       (-1LL << NEFF)
  38
  39 #ifdef CONFIG_29BIT
  40 #define NPHYS           29
  41 #else
  42 #define NPHYS           32
  43 #endif
  44
  45 #define NPHYS_SIGN      (1LL << (NPHYS - 1))
  46 #define NPHYS_MASK      (-1LL << NPHYS)
  47
  48 /*
  49  * traditional two-level paging structure
  50  */
  51 /* PTE bits */
  52 #if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64)
  53 # define PTE_MAGNITUDE  3       /* 64-bit PTEs on extended mode SH-X2 TLB */
  54 #else
  55 # define PTE_MAGNITUDE  2       /* 32-bit PTEs */
  56 #endif
  57 #define PTE_SHIFT       PAGE_SHIFT
  58 #define PTE_BITS        (PTE_SHIFT - PTE_MAGNITUDE)
  59
  60 /* PGD bits */
  61 #define PGDIR_SHIFT     (PTE_SHIFT + PTE_BITS)
  62 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  63 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  64
  65 /* Entries per level */
  66 #define PTRS_PER_PTE    (PAGE_SIZE / (1 << PTE_MAGNITUDE))
  67 #define PTRS_PER_PGD    (PAGE_SIZE / sizeof(pgd_t))
  68
  69 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
  70 #define FIRST_USER_ADDRESS      0
  71
  72 #ifdef CONFIG_32BIT
  73 #define PHYS_ADDR_MASK          0xffffffff
  74 #else
  75 #define PHYS_ADDR_MASK          0x1fffffff
  76 #endif
  77
  78 #define PTE_PHYS_MASK           (PHYS_ADDR_MASK & PAGE_MASK)
  79 #define PTE_FLAGS_MASK          (~(PTE_PHYS_MASK) << PAGE_SHIFT)
  80
  81 #ifdef CONFIG_SUPERH32
  82 #define VMALLOC_START   (P3SEG)
  83 #else
  84 #define VMALLOC_START   (0xf0000000)
  85 #endif
  86 #define VMALLOC_END     (FIXADDR_START-2*PAGE_SIZE)
  87
  88 #if defined(CONFIG_SUPERH32)
  89 #include <asm/pgtable_32.h>
  90 #else
  91 #include <asm/pgtable_64.h>
  92 #endif
  93
  94 /*
  95  * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
  96  * protection for execute, and considers it the same as a read. Also, write
  97  * permission implies read permission. This is the closest we can get..
  98  *
  99  * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
 100  * not only supporting separate execute, read, and write bits, but having
 101  * completely separate permission bits for user and kernel space.
 102  */
 103          /*xwr*/
 104 #define __P000  PAGE_NONE
 105 #define __P001  PAGE_READONLY
 106 #define __P010  PAGE_COPY
 107 #define __P011  PAGE_COPY
 108 #define __P100  PAGE_EXECREAD
 109 #define __P101  PAGE_EXECREAD
 110 #define __P110  PAGE_COPY
 111 #define __P111  PAGE_COPY
 112
 113 #define __S000  PAGE_NONE
 114 #define __S001  PAGE_READONLY
 115 #define __S010  PAGE_WRITEONLY
 116 #define __S011  PAGE_SHARED
 117 #define __S100  PAGE_EXECREAD
 118 #define __S101  PAGE_EXECREAD
 119 #define __S110  PAGE_RWX
 120 #define __S111  PAGE_RWX
 121
 122 typedef pte_t *pte_addr_t;
 123
 124 #define kern_addr_valid(addr)   (1)
 125
 126 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 127                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 128
 129 #define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
 130
 131 /*
 132  * No page table caches to initialise
 133  */
 134 #define pgtable_cache_init()    do { } while (0)
 135
 136 #if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
 137         defined(CONFIG_SH7705_CACHE_32KB))
 138 struct mm_struct;
 139 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 140 pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
 141 #endif
 142
 143 struct vm_area_struct;
 144 extern void update_mmu_cache(struct vm_area_struct * vma,
 145                              unsigned long address, pte_t pte);
 146 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 147 extern void paging_init(void);
 148 extern void page_table_range_init(unsigned long start, unsigned long end,
 149                                   pgd_t *pgd);
 150
 151 #if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_CPU_SH4) && defined(CONFIG_MMU)
 152 extern void kmap_coherent_init(void);
 153 #else
 154 #define kmap_coherent_init()    do { } while (0)
 155 #endif
 156
 157 #include <asm-generic/pgtable.h>
 158
 159 #endif /* __ASM_SH_PGTABLE_H */