2 * arch/sh/kernel/cpu/sh2a/clock-sh7206.c
4 * SH7206 support for the clock framework
6 * Copyright (C) 2006 Yoshinori Sato
9 * Copyright (C) 2005 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <asm/clock.h>
21 static const int pll1rate
[]={1,2,3,4,6,8};
22 static const int pfc_divisors
[]={1,2,3,4,6,8,12};
23 #define ifc_divisors pfc_divisors
25 #if (CONFIG_SH_CLK_MD == 2)
27 #elif (CONFIG_SH_CLK_MD == 6)
29 #elif (CONFIG_SH_CLK_MD == 7)
32 #error "Illigal Clock Mode!"
35 static void master_clk_init(struct clk
*clk
)
37 clk
->rate
*= PLL2
* pll1rate
[(ctrl_inw(FREQCR
) >> 8) & 0x0007];
40 static struct clk_ops sh7206_master_clk_ops
= {
41 .init
= master_clk_init
,
44 static void module_clk_recalc(struct clk
*clk
)
46 int idx
= (ctrl_inw(FREQCR
) & 0x0007);
47 clk
->rate
= clk
->parent
->rate
/ pfc_divisors
[idx
];
50 static struct clk_ops sh7206_module_clk_ops
= {
51 .recalc
= module_clk_recalc
,
54 static void bus_clk_recalc(struct clk
*clk
)
56 clk
->rate
= clk
->parent
->rate
/ pll1rate
[(ctrl_inw(FREQCR
) >> 8) & 0x0007];
59 static struct clk_ops sh7206_bus_clk_ops
= {
60 .recalc
= bus_clk_recalc
,
63 static void cpu_clk_recalc(struct clk
*clk
)
65 int idx
= (ctrl_inw(FREQCR
) & 0x0007);
66 clk
->rate
= clk
->parent
->rate
/ ifc_divisors
[idx
];
69 static struct clk_ops sh7206_cpu_clk_ops
= {
70 .recalc
= cpu_clk_recalc
,
73 static struct clk_ops
*sh7206_clk_ops
[] = {
74 &sh7206_master_clk_ops
,
75 &sh7206_module_clk_ops
,
80 void __init
arch_init_clk_ops(struct clk_ops
**ops
, int idx
)
82 if (idx
< ARRAY_SIZE(sh7206_clk_ops
))
83 *ops
= sh7206_clk_ops
[idx
];