arch/sh/kernel/cpu/sh4a/setup-sh7763.c

   1 /*
   2  * SH7763 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2007  Yoshihiro Shimoda
   6  *  Copyright (C) 2008  Nobuhiro Iwamatsu
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/io.h>
  16 #include <linux/serial_sci.h>
  17
  18 static struct resource rtc_resources[] = {
  19         [0] = {
  20                 .start  = 0xffe80000,
  21                 .end    = 0xffe80000 + 0x58 - 1,
  22                 .flags  = IORESOURCE_IO,
  23         },
  24         [1] = {
  25                 /* Period IRQ */
  26                 .start  = 21,
  27                 .flags  = IORESOURCE_IRQ,
  28         },
  29         [2] = {
  30                 /* Carry IRQ */
  31                 .start  = 22,
  32                 .flags  = IORESOURCE_IRQ,
  33         },
  34         [3] = {
  35                 /* Alarm IRQ */
  36                 .start  = 20,
  37                 .flags  = IORESOURCE_IRQ,
  38         },
  39 };
  40
  41 static struct platform_device rtc_device = {
  42         .name           = "sh-rtc",
  43         .id             = -1,
  44         .num_resources  = ARRAY_SIZE(rtc_resources),
  45         .resource       = rtc_resources,
  46 };
  47
  48 static struct plat_sci_port sci_platform_data[] = {
  49         {
  50                 .mapbase        = 0xffe00000,
  51                 .flags          = UPF_BOOT_AUTOCONF,
  52                 .type           = PORT_SCIF,
  53                 .irqs           = { 40, 41, 43, 42 },
  54         }, {
  55                 .mapbase        = 0xffe08000,
  56                 .flags          = UPF_BOOT_AUTOCONF,
  57                 .type           = PORT_SCIF,
  58                 .irqs           = { 76, 77, 79, 78 },
  59         }, {
  60                 .mapbase        = 0xffe10000,
  61                 .flags          = UPF_BOOT_AUTOCONF,
  62                 .type           = PORT_SCIF,
  63                 .irqs           = { 104, 105, 107, 106 },
  64         }, {
  65                 .flags = 0,
  66         }
  67 };
  68
  69 static struct platform_device sci_device = {
  70         .name           = "sh-sci",
  71         .id             = -1,
  72         .dev            = {
  73                 .platform_data  = sci_platform_data,
  74         },
  75 };
  76
  77 static struct resource usb_ohci_resources[] = {
  78         [0] = {
  79                 .start  = 0xffec8000,
  80                 .end    = 0xffec80ff,
  81                 .flags  = IORESOURCE_MEM,
  82         },
  83         [1] = {
  84                 .start  = 83,
  85                 .end    = 83,
  86                 .flags  = IORESOURCE_IRQ,
  87         },
  88 };
  89
  90 static u64 usb_ohci_dma_mask = 0xffffffffUL;
  91 static struct platform_device usb_ohci_device = {
  92         .name           = "sh_ohci",
  93         .id             = -1,
  94         .dev = {
  95                 .dma_mask               = &usb_ohci_dma_mask,
  96                 .coherent_dma_mask      = 0xffffffff,
  97         },
  98         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
  99         .resource       = usb_ohci_resources,
 100 };
 101
 102 static struct resource usbf_resources[] = {
 103         [0] = {
 104                 .start  = 0xffec0000,
 105                 .end    = 0xffec00ff,
 106                 .flags  = IORESOURCE_MEM,
 107         },
 108         [1] = {
 109                 .start  = 84,
 110                 .end    = 84,
 111                 .flags  = IORESOURCE_IRQ,
 112         },
 113 };
 114
 115 static struct platform_device usbf_device = {
 116         .name           = "sh_udc",
 117         .id             = -1,
 118         .dev = {
 119                 .dma_mask               = NULL,
 120                 .coherent_dma_mask      = 0xffffffff,
 121         },
 122         .num_resources  = ARRAY_SIZE(usbf_resources),
 123         .resource       = usbf_resources,
 124 };
 125
 126 static struct platform_device *sh7763_devices[] __initdata = {
 127         &rtc_device,
 128         &sci_device,
 129         &usb_ohci_device,
 130         &usbf_device,
 131 };
 132
 133 static int __init sh7763_devices_setup(void)
 134 {
 135         return platform_add_devices(sh7763_devices,
 136                                     ARRAY_SIZE(sh7763_devices));
 137 }
 138 __initcall(sh7763_devices_setup);
 139
 140 enum {
 141         UNUSED = 0,
 142
 143         /* interrupt sources */
 144
 145         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 146         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 147         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 148         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 149
 150         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 151         RTC_ATI, RTC_PRI, RTC_CUI,
 152         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 153         HUDI, LCDC,
 154         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
 155         SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
 156         DMAC0_DMINT4, DMAC0_DMINT5,
 157         IIC0, IIC1,
 158         CMT,
 159         GEINT0, GEINT1, GEINT2,
 160         HAC,
 161         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
 162         PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
 163         STIF0, STIF1,
 164         SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
 165         SIOF0, SIOF1, SIOF2,
 166         USBH, USBFI0, USBFI1,
 167         TPU, PCC,
 168         MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
 169         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
 170         TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
 171         SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
 172         GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3,
 173
 174         /* interrupt groups */
 175
 176         TMU012, TMU345, RTC, DMAC, SCIF0, GETHER, PCIC5,
 177         SCIF1, USBF, MMCIF, SIM, SCIF2, GPIO,
 178 };
 179
 180 static struct intc_vect vectors[] __initdata = {
 181         INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
 182         INTC_VECT(RTC_CUI, 0x4c0),
 183         INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
 184         INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
 185         INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
 186         INTC_VECT(LCDC, 0x620),
 187         INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
 188         INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0),
 189         INTC_VECT(DMAC0_DMAE, 0x6c0),
 190         INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
 191         INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
 192         INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0),
 193         INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
 194         INTC_VECT(CMT, 0x900), INTC_VECT(GEINT0, 0x920),
 195         INTC_VECT(GEINT1, 0x940), INTC_VECT(GEINT2, 0x960),
 196         INTC_VECT(HAC, 0x980),
 197         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 198         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 199         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
 200         INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
 201         INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
 202         INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
 203         INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0),
 204         INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0),
 205         INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
 206         INTC_VECT(USBH, 0xc60), INTC_VECT(USBFI0, 0xc80),
 207         INTC_VECT(USBFI1, 0xca0),
 208         INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
 209         INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
 210         INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
 211         INTC_VECT(SIM_ERI, 0xd80), INTC_VECT(SIM_RXI, 0xda0),
 212         INTC_VECT(SIM_TXI, 0xdc0), INTC_VECT(SIM_TEND, 0xde0),
 213         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 214         INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
 215         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 216         INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
 217         INTC_VECT(SCIF2_ERI, 0xf00), INTC_VECT(SCIF2_RXI, 0xf20),
 218         INTC_VECT(SCIF2_BRI, 0xf40), INTC_VECT(SCIF2_TXI, 0xf60),
 219         INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0),
 220         INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0),
 221 };
 222
 223 static struct intc_group groups[] __initdata = {
 224         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 225         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 226         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 227         INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 228                    DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
 229         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
 230         INTC_GROUP(GETHER, GEINT0, GEINT1, GEINT2),
 231         INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
 232         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
 233         INTC_GROUP(USBF, USBFI0, USBFI1),
 234         INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
 235         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
 236         INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
 237         INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
 238 };
 239
 240 static struct intc_mask_reg mask_registers[] __initdata = {
 241         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 242           { 0, 0, 0, 0, 0, 0, GPIO, 0,
 243             SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 244             PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
 245             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 246         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 247           { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
 248             0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
 249             PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
 250             LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
 251 };
 252
 253 static struct intc_prio_reg prio_registers[] __initdata = {
 254         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 255                                                  TMU2, TMU2_TICPI } },
 256         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 257         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 258         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
 259         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 260                                                  PCISERR, PCIINTA } },
 261         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 262                                                  PCIINTD, PCIC5 } },
 263         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
 264         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
 265         { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
 266         { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
 267         { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
 268         { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
 269         { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
 270         { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
 271 };
 272
 273 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
 274                          mask_registers, prio_registers, NULL);
 275
 276 /* Support for external interrupt pins in IRQ mode */
 277 static struct intc_vect irq_vectors[] __initdata = {
 278         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 279         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 280         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 281         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 282 };
 283
 284 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 285         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 286           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 287 };
 288
 289 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 290         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 291                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 292 };
 293
 294 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 295         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 296                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 297 };
 298
 299 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 300         { 0xffd00024, 0, 32, /* INTREQ */
 301           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 302 };
 303
 304 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
 305                              NULL, irq_mask_registers, irq_prio_registers,
 306                              irq_sense_registers, irq_ack_registers);
 307
 308
 309 /* External interrupt pins in IRL mode */
 310 static struct intc_vect irl_vectors[] __initdata = {
 311         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 312         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 313         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 314         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 315         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 316         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 317         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 318         INTC_VECT(IRL_HHHL, 0x3c0),
 319 };
 320
 321 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 322         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 323           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 324             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 325             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 326             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 327 };
 328
 329 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 330         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 331           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 332             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 333             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 334             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 335             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 336 };
 337
 338 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
 339                         NULL, irl7654_mask_registers, NULL, NULL);
 340
 341 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 342                         NULL, irl3210_mask_registers, NULL, NULL);
 343
 344 #define INTC_ICR0       0xffd00000
 345 #define INTC_INTMSK0    0xffd00044
 346 #define INTC_INTMSK1    0xffd00048
 347 #define INTC_INTMSK2    0xffd40080
 348 #define INTC_INTMSKCLR1 0xffd00068
 349 #define INTC_INTMSKCLR2 0xffd40084
 350
 351 void __init plat_irq_setup(void)
 352 {
 353         /* disable IRQ7-0 */
 354         ctrl_outl(0xff000000, INTC_INTMSK0);
 355
 356         /* disable IRL3-0 + IRL7-4 */
 357         ctrl_outl(0xc0000000, INTC_INTMSK1);
 358         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 359
 360         register_intc_controller(&intc_desc);
 361 }
 362
 363 void __init plat_irq_setup_pins(int mode)
 364 {
 365         switch (mode) {
 366         case IRQ_MODE_IRQ:
 367                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 368                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 369                 register_intc_controller(&intc_irq_desc);
 370                 break;
 371         case IRQ_MODE_IRL7654:
 372                 /* enable IRL7-4 but don't provide any masking */
 373                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 374                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 375                 break;
 376         case IRQ_MODE_IRL3210:
 377                 /* enable IRL0-3 but don't provide any masking */
 378                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 379                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 380                 break;
 381         case IRQ_MODE_IRL7654_MASK:
 382                 /* enable IRL7-4 and mask using cpu intc controller */
 383                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 384                 register_intc_controller(&intc_irl7654_desc);
 385                 break;
 386         case IRQ_MODE_IRL3210_MASK:
 387                 /* enable IRL0-3 and mask using cpu intc controller */
 388                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 389                 register_intc_controller(&intc_irl3210_desc);
 390                 break;
 391         default:
 392                 BUG();
 393         }
 394 }