4 * Copyright (C) 2007 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
16 #include <asm/mmzone.h>
18 static struct plat_sci_port sci_platform_data
[] = {
20 .mapbase
= 0xffea0000,
21 .flags
= UPF_BOOT_AUTOCONF
,
23 .irqs
= { 40, 41, 43, 42 },
25 .mapbase
= 0xffeb0000,
26 .flags
= UPF_BOOT_AUTOCONF
,
28 .irqs
= { 44, 45, 47, 46 },
32 * The rest of these all have multiplexed IRQs
35 .mapbase
= 0xffec0000,
36 .flags
= UPF_BOOT_AUTOCONF
,
38 .irqs
= { 60, 60, 60, 60 },
40 .mapbase
= 0xffed0000,
41 .flags
= UPF_BOOT_AUTOCONF
,
43 .irqs
= { 61, 61, 61, 61 },
45 .mapbase
= 0xffee0000,
46 .flags
= UPF_BOOT_AUTOCONF
,
48 .irqs
= { 62, 62, 62, 62 },
50 .mapbase
= 0xffef0000,
51 .flags
= UPF_BOOT_AUTOCONF
,
53 .irqs
= { 63, 63, 63, 63 },
59 static struct platform_device sci_device
= {
63 .platform_data
= sci_platform_data
,
67 static struct platform_device
*sh7785_devices
[] __initdata
= {
71 static int __init
sh7785_devices_setup(void)
73 return platform_add_devices(sh7785_devices
,
74 ARRAY_SIZE(sh7785_devices
));
76 __initcall(sh7785_devices_setup
);
81 /* interrupt sources */
83 IRL0_LLLL
, IRL0_LLLH
, IRL0_LLHL
, IRL0_LLHH
,
84 IRL0_LHLL
, IRL0_LHLH
, IRL0_LHHL
, IRL0_LHHH
,
85 IRL0_HLLL
, IRL0_HLLH
, IRL0_HLHL
, IRL0_HLHH
,
86 IRL0_HHLL
, IRL0_HHLH
, IRL0_HHHL
,
88 IRL4_LLLL
, IRL4_LLLH
, IRL4_LLHL
, IRL4_LLHH
,
89 IRL4_LHLL
, IRL4_LHLH
, IRL4_LHHL
, IRL4_LHHH
,
90 IRL4_HLLL
, IRL4_HLLH
, IRL4_HLHL
, IRL4_HLHH
,
91 IRL4_HHLL
, IRL4_HHLH
, IRL4_HHHL
,
93 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
95 TMU0
, TMU1
, TMU2
, TMU2_TICPI
,
97 DMAC0_DMINT0
, DMAC0_DMINT1
, DMAC0_DMINT2
, DMAC0_DMINT3
,
98 DMAC0_DMINT4
, DMAC0_DMINT5
, DMAC0_DMAE
,
99 SCIF0_ERI
, SCIF0_RXI
, SCIF0_BRI
, SCIF0_TXI
,
100 SCIF1_ERI
, SCIF1_RXI
, SCIF1_BRI
, SCIF1_TXI
,
101 DMAC1_DMINT6
, DMAC1_DMINT7
, DMAC1_DMINT8
, DMAC1_DMINT9
,
102 DMAC1_DMINT10
, DMAC1_DMINT11
, DMAC1_DMAE
,
104 SCIF2
, SCIF3
, SCIF4
, SCIF5
,
105 PCISERR
, PCIINTA
, PCIINTB
, PCIINTC
, PCIINTD
,
106 PCIERR
, PCIPWD3
, PCIPWD2
, PCIPWD1
, PCIPWD0
,
108 MMCIF_FSTAT
, MMCIF_TRAN
, MMCIF_ERR
, MMCIF_FRDY
,
110 GDTA_GACLI
, GDTA_GAMCI
, GDTA_GAERI
,
114 FLCTL_FLSTE
, FLCTL_FLEND
, FLCTL_FLTRQ0
, FLCTL_FLTRQ1
,
115 GPIOI0
, GPIOI1
, GPIOI2
, GPIOI3
,
117 /* interrupt groups */
119 TMU012
, DMAC0
, SCIF0
, SCIF1
, DMAC1
,
120 PCIC5
, MMCIF
, GDTA
, TMU345
, FLCTL
, GPIO
123 static struct intc_vect vectors
[] __initdata
= {
124 INTC_VECT(WDT
, 0x560),
125 INTC_VECT(TMU0
, 0x580), INTC_VECT(TMU1
, 0x5a0),
126 INTC_VECT(TMU2
, 0x5c0), INTC_VECT(TMU2_TICPI
, 0x5e0),
127 INTC_VECT(HUDI
, 0x600),
128 INTC_VECT(DMAC0_DMINT0
, 0x620), INTC_VECT(DMAC0_DMINT1
, 0x640),
129 INTC_VECT(DMAC0_DMINT2
, 0x660), INTC_VECT(DMAC0_DMINT3
, 0x680),
130 INTC_VECT(DMAC0_DMINT4
, 0x6a0), INTC_VECT(DMAC0_DMINT5
, 0x6c0),
131 INTC_VECT(DMAC0_DMAE
, 0x6e0),
132 INTC_VECT(SCIF0_ERI
, 0x700), INTC_VECT(SCIF0_RXI
, 0x720),
133 INTC_VECT(SCIF0_BRI
, 0x740), INTC_VECT(SCIF0_TXI
, 0x760),
134 INTC_VECT(SCIF1_ERI
, 0x780), INTC_VECT(SCIF1_RXI
, 0x7a0),
135 INTC_VECT(SCIF1_BRI
, 0x7c0), INTC_VECT(SCIF1_TXI
, 0x7e0),
136 INTC_VECT(DMAC1_DMINT6
, 0x880), INTC_VECT(DMAC1_DMINT7
, 0x8a0),
137 INTC_VECT(DMAC1_DMINT8
, 0x8c0), INTC_VECT(DMAC1_DMINT9
, 0x8e0),
138 INTC_VECT(DMAC1_DMINT10
, 0x900), INTC_VECT(DMAC1_DMINT11
, 0x920),
139 INTC_VECT(DMAC1_DMAE
, 0x940),
140 INTC_VECT(HSPI
, 0x960),
141 INTC_VECT(SCIF2
, 0x980), INTC_VECT(SCIF3
, 0x9a0),
142 INTC_VECT(SCIF4
, 0x9c0), INTC_VECT(SCIF5
, 0x9e0),
143 INTC_VECT(PCISERR
, 0xa00), INTC_VECT(PCIINTA
, 0xa20),
144 INTC_VECT(PCIINTB
, 0xa40), INTC_VECT(PCIINTC
, 0xa60),
145 INTC_VECT(PCIINTD
, 0xa80), INTC_VECT(PCIERR
, 0xaa0),
146 INTC_VECT(PCIPWD3
, 0xac0), INTC_VECT(PCIPWD2
, 0xae0),
147 INTC_VECT(PCIPWD1
, 0xb00), INTC_VECT(PCIPWD0
, 0xb20),
148 INTC_VECT(SIOF
, 0xc00),
149 INTC_VECT(MMCIF_FSTAT
, 0xd00), INTC_VECT(MMCIF_TRAN
, 0xd20),
150 INTC_VECT(MMCIF_ERR
, 0xd40), INTC_VECT(MMCIF_FRDY
, 0xd60),
151 INTC_VECT(DU
, 0xd80),
152 INTC_VECT(GDTA_GACLI
, 0xda0), INTC_VECT(GDTA_GAMCI
, 0xdc0),
153 INTC_VECT(GDTA_GAERI
, 0xde0),
154 INTC_VECT(TMU3
, 0xe00), INTC_VECT(TMU4
, 0xe20),
155 INTC_VECT(TMU5
, 0xe40),
156 INTC_VECT(SSI0
, 0xe80), INTC_VECT(SSI1
, 0xea0),
157 INTC_VECT(HAC0
, 0xec0), INTC_VECT(HAC1
, 0xee0),
158 INTC_VECT(FLCTL_FLSTE
, 0xf00), INTC_VECT(FLCTL_FLEND
, 0xf20),
159 INTC_VECT(FLCTL_FLTRQ0
, 0xf40), INTC_VECT(FLCTL_FLTRQ1
, 0xf60),
160 INTC_VECT(GPIOI0
, 0xf80), INTC_VECT(GPIOI1
, 0xfa0),
161 INTC_VECT(GPIOI2
, 0xfc0), INTC_VECT(GPIOI3
, 0xfe0),
164 static struct intc_group groups
[] __initdata
= {
165 INTC_GROUP(TMU012
, TMU0
, TMU1
, TMU2
, TMU2_TICPI
),
166 INTC_GROUP(DMAC0
, DMAC0_DMINT0
, DMAC0_DMINT1
, DMAC0_DMINT2
,
167 DMAC0_DMINT3
, DMAC0_DMINT4
, DMAC0_DMINT5
, DMAC0_DMAE
),
168 INTC_GROUP(SCIF0
, SCIF0_ERI
, SCIF0_RXI
, SCIF0_BRI
, SCIF0_TXI
),
169 INTC_GROUP(SCIF1
, SCIF1_ERI
, SCIF1_RXI
, SCIF1_BRI
, SCIF1_TXI
),
170 INTC_GROUP(DMAC1
, DMAC1_DMINT6
, DMAC1_DMINT7
, DMAC1_DMINT8
,
171 DMAC1_DMINT9
, DMAC1_DMINT10
, DMAC1_DMINT11
, DMAC1_DMAE
),
172 INTC_GROUP(PCIC5
, PCIERR
, PCIPWD3
, PCIPWD2
, PCIPWD1
, PCIPWD0
),
173 INTC_GROUP(MMCIF
, MMCIF_FSTAT
, MMCIF_TRAN
, MMCIF_ERR
, MMCIF_FRDY
),
174 INTC_GROUP(GDTA
, GDTA_GACLI
, GDTA_GAMCI
, GDTA_GAERI
),
175 INTC_GROUP(TMU345
, TMU3
, TMU4
, TMU5
),
176 INTC_GROUP(FLCTL
, FLCTL_FLSTE
, FLCTL_FLEND
,
177 FLCTL_FLTRQ0
, FLCTL_FLTRQ1
),
178 INTC_GROUP(GPIO
, GPIOI0
, GPIOI1
, GPIOI2
, GPIOI3
),
181 static struct intc_mask_reg mask_registers
[] __initdata
= {
182 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
183 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
185 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
186 { IRL0_LLLL
, IRL0_LLLH
, IRL0_LLHL
, IRL0_LLHH
,
187 IRL0_LHLL
, IRL0_LHLH
, IRL0_LHHL
, IRL0_LHHH
,
188 IRL0_HLLL
, IRL0_HLLH
, IRL0_HLHL
, IRL0_HLHH
,
189 IRL0_HHLL
, IRL0_HHLH
, IRL0_HHHL
, 0,
190 IRL4_LLLL
, IRL4_LLLH
, IRL4_LLHL
, IRL4_LLHH
,
191 IRL4_LHLL
, IRL4_LHLH
, IRL4_LHHL
, IRL4_LHHH
,
192 IRL4_HLLL
, IRL4_HLLH
, IRL4_HLHL
, IRL4_HLHH
,
193 IRL4_HHLL
, IRL4_HHLH
, IRL4_HHHL
, 0, } },
195 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
196 { 0, 0, 0, GDTA
, DU
, SSI0
, SSI1
, GPIO
,
197 FLCTL
, MMCIF
, HSPI
, SIOF
, PCIC5
, PCIINTD
, PCIINTC
, PCIINTB
,
198 PCIINTA
, PCISERR
, HAC1
, HAC0
, DMAC1
, DMAC0
, HUDI
, WDT
,
199 SCIF5
, SCIF4
, SCIF3
, SCIF2
, SCIF1
, SCIF0
, TMU345
, TMU012
} },
202 static struct intc_prio_reg prio_registers
[] __initdata
= {
203 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
,
204 IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
205 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0
, TMU1
,
206 TMU2
, TMU2_TICPI
} },
207 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3
, TMU4
, TMU5
, } },
208 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0
, SCIF1
,
210 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4
, SCIF5
, WDT
, } },
211 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI
, DMAC0
, DMAC1
, } },
212 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0
, HAC1
,
213 PCISERR
, PCIINTA
} },
214 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB
, PCIINTC
,
216 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF
, HSPI
, MMCIF
, } },
217 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL
, GPIO
, SSI0
, SSI1
, } },
218 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU
, GDTA
, } },
221 static DECLARE_INTC_DESC(intc_desc
, "sh7785", vectors
, groups
,
222 mask_registers
, prio_registers
, NULL
);
224 /* Support for external interrupt pins in IRQ mode */
226 static struct intc_vect vectors_irq0123
[] __initdata
= {
227 INTC_VECT(IRQ0
, 0x240), INTC_VECT(IRQ1
, 0x280),
228 INTC_VECT(IRQ2
, 0x2c0), INTC_VECT(IRQ3
, 0x300),
231 static struct intc_vect vectors_irq4567
[] __initdata
= {
232 INTC_VECT(IRQ4
, 0x340), INTC_VECT(IRQ5
, 0x380),
233 INTC_VECT(IRQ6
, 0x3c0), INTC_VECT(IRQ7
, 0x200),
236 static struct intc_sense_reg sense_registers
[] __initdata
= {
237 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
,
238 IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
241 static struct intc_mask_reg ack_registers
[] __initdata
= {
242 { 0xffd00024, 0, 32, /* INTREQ */
243 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
246 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123
, "sh7785-irq0123",
247 vectors_irq0123
, NULL
, mask_registers
,
248 prio_registers
, sense_registers
, ack_registers
);
250 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567
, "sh7785-irq4567",
251 vectors_irq4567
, NULL
, mask_registers
,
252 prio_registers
, sense_registers
, ack_registers
);
254 /* External interrupt pins in IRL mode */
256 static struct intc_vect vectors_irl0123
[] __initdata
= {
257 INTC_VECT(IRL0_LLLL
, 0x200), INTC_VECT(IRL0_LLLH
, 0x220),
258 INTC_VECT(IRL0_LLHL
, 0x240), INTC_VECT(IRL0_LLHH
, 0x260),
259 INTC_VECT(IRL0_LHLL
, 0x280), INTC_VECT(IRL0_LHLH
, 0x2a0),
260 INTC_VECT(IRL0_LHHL
, 0x2c0), INTC_VECT(IRL0_LHHH
, 0x2e0),
261 INTC_VECT(IRL0_HLLL
, 0x300), INTC_VECT(IRL0_HLLH
, 0x320),
262 INTC_VECT(IRL0_HLHL
, 0x340), INTC_VECT(IRL0_HLHH
, 0x360),
263 INTC_VECT(IRL0_HHLL
, 0x380), INTC_VECT(IRL0_HHLH
, 0x3a0),
264 INTC_VECT(IRL0_HHHL
, 0x3c0),
267 static struct intc_vect vectors_irl4567
[] __initdata
= {
268 INTC_VECT(IRL4_LLLL
, 0xb00), INTC_VECT(IRL4_LLLH
, 0xb20),
269 INTC_VECT(IRL4_LLHL
, 0xb40), INTC_VECT(IRL4_LLHH
, 0xb60),
270 INTC_VECT(IRL4_LHLL
, 0xb80), INTC_VECT(IRL4_LHLH
, 0xba0),
271 INTC_VECT(IRL4_LHHL
, 0xbc0), INTC_VECT(IRL4_LHHH
, 0xbe0),
272 INTC_VECT(IRL4_HLLL
, 0xc00), INTC_VECT(IRL4_HLLH
, 0xc20),
273 INTC_VECT(IRL4_HLHL
, 0xc40), INTC_VECT(IRL4_HLHH
, 0xc60),
274 INTC_VECT(IRL4_HHLL
, 0xc80), INTC_VECT(IRL4_HHLH
, 0xca0),
275 INTC_VECT(IRL4_HHHL
, 0xcc0),
278 static DECLARE_INTC_DESC(intc_desc_irl0123
, "sh7785-irl0123", vectors_irl0123
,
279 NULL
, mask_registers
, NULL
, NULL
);
281 static DECLARE_INTC_DESC(intc_desc_irl4567
, "sh7785-irl4567", vectors_irl4567
,
282 NULL
, mask_registers
, NULL
, NULL
);
284 #define INTC_ICR0 0xffd00000
285 #define INTC_INTMSK0 0xffd00044
286 #define INTC_INTMSK1 0xffd00048
287 #define INTC_INTMSK2 0xffd40080
288 #define INTC_INTMSKCLR1 0xffd00068
289 #define INTC_INTMSKCLR2 0xffd40084
291 void __init
plat_irq_setup(void)
293 /* disable IRQ3-0 + IRQ7-4 */
294 ctrl_outl(0xff000000, INTC_INTMSK0
);
296 /* disable IRL3-0 + IRL7-4 */
297 ctrl_outl(0xc0000000, INTC_INTMSK1
);
298 ctrl_outl(0xfffefffe, INTC_INTMSK2
);
300 /* select IRL mode for IRL3-0 + IRL7-4 */
301 ctrl_outl(ctrl_inl(INTC_ICR0
) & ~0x00c00000, INTC_ICR0
);
303 /* disable holding function, ie enable "SH-4 Mode" */
304 ctrl_outl(ctrl_inl(INTC_ICR0
) | 0x00200000, INTC_ICR0
);
306 register_intc_controller(&intc_desc
);
309 void __init
plat_irq_setup_pins(int mode
)
312 case IRQ_MODE_IRQ7654
:
313 /* select IRQ mode for IRL7-4 */
314 ctrl_outl(ctrl_inl(INTC_ICR0
) | 0x00400000, INTC_ICR0
);
315 register_intc_controller(&intc_desc_irq4567
);
317 case IRQ_MODE_IRQ3210
:
318 /* select IRQ mode for IRL3-0 */
319 ctrl_outl(ctrl_inl(INTC_ICR0
) | 0x00800000, INTC_ICR0
);
320 register_intc_controller(&intc_desc_irq0123
);
322 case IRQ_MODE_IRL7654
:
323 /* enable IRL7-4 but don't provide any masking */
324 ctrl_outl(0x40000000, INTC_INTMSKCLR1
);
325 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2
);
327 case IRQ_MODE_IRL3210
:
328 /* enable IRL0-3 but don't provide any masking */
329 ctrl_outl(0x80000000, INTC_INTMSKCLR1
);
330 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2
);
332 case IRQ_MODE_IRL7654_MASK
:
333 /* enable IRL7-4 and mask using cpu intc controller */
334 ctrl_outl(0x40000000, INTC_INTMSKCLR1
);
335 register_intc_controller(&intc_desc_irl4567
);
337 case IRQ_MODE_IRL3210_MASK
:
338 /* enable IRL0-3 and mask using cpu intc controller */
339 ctrl_outl(0x80000000, INTC_INTMSKCLR1
);
340 register_intc_controller(&intc_desc_irl0123
);
347 void __init
plat_mem_setup(void)
349 /* Register the URAM space as Node 1 */
350 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);