3 SATA nodes are defined to describe on-chip Serial ATA controllers.
4 Each SATA controller should have its own node.
6 It is possible, but not required, to represent each port as a sub-node.
7 It allows to enable each port independently when dealing with multiple
11 - compatible : compatible string, one of:
12 - "allwinner,sun4i-a10-ahci"
14 - "hisilicon,hisi-ahci"
15 - "cavium,octeon-7130-ahci"
17 - "marvell,armada-380-ahci"
18 - "marvell,armada-3700-ahci"
20 - "snps,exynos5440-ahci"
23 - interrupts : <interrupt mapping for SATA IRQ>
24 - reg : <registers mapping>
26 Please note that when using "generic-ahci" you must also specify a SoC specific
28 compatible = "manufacturer,soc-model-ahci", "generic-ahci";
31 - dma-coherent : Present if dma operations are coherent
32 - clocks : a list of phandle + clock specifier pairs
33 - target-supply : regulator for SATA target power
34 - phys : reference to the SATA PHY node
35 - phy-names : must be "sata-phy"
36 - ports-implemented : Mask that indicates which ports that the HBA supports
37 are available for software to use. Useful if PORTS_IMPL
38 is not programmed by the BIOS, which is true with
41 Required properties when using sub-nodes:
42 - #address-cells : number of cells to encode an address
43 - #size-cells : number of cells representing the size of an address
46 Sub-nodes required properties:
47 - reg : the port number
48 And at least one of the following properties:
49 - phys : reference to the SATA PHY node
50 - target-supply : regulator for SATA target power
54 compatible = "snps,spear-ahci";
55 reg = <0xffe08000 0x1000>;
60 compatible = "allwinner,sun4i-a10-ahci";
61 reg = <0x01c18000 0x1000>;
63 clocks = <&pll6 0>, <&ahb_gates 25>;
64 target-supply = <®_ahci_5v>;
69 compatible = "marvell,berlin2q-achi", "generic-ahci";
70 reg = <0xe90000 0x1000>;
71 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
72 clocks = <&chip CLKID_SATA>;
79 target-supply = <®_sata0>;
85 target-supply = <®_sata1>;;