arch/arc/kernel/intc-compact.c

   1 /*
   2  * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <linux/interrupt.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/irqdomain.h>
  14 #include <linux/irqchip.h>
  15 #include <asm/irq.h>
  16
  17 #define NR_CPU_IRQS     32      /* number of irq lines coming in */
  18 #define TIMER0_IRQ      3       /* Fixed by ISA */
  19
  20 /*
  21  * Early Hardware specific Interrupt setup
  22  * -Platform independent, needed for each CPU (not foldable into init_IRQ)
  23  * -Called very early (start_kernel -> setup_arch -> setup_processor)
  24  *
  25  * what it does ?
  26  * -Optionally, setup the High priority Interrupts as Level 2 IRQs
  27  */
  28 void arc_init_IRQ(void)
  29 {
  30         unsigned int level_mask = 0, i;
  31
  32        /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
  33         level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
  34
  35         /*
  36          * Write to register, even if no LV2 IRQs configured to reset it
  37          * in case bootloader had mucked with it
  38          */
  39         write_aux_reg(AUX_IRQ_LEV, level_mask);
  40
  41         if (level_mask)
  42                 pr_info("Level-2 interrupts bitset %x\n", level_mask);
  43
  44         /*
  45          * Disable all IRQ lines so faulty external hardware won't
  46          * trigger interrupt that kernel is not ready to handle.
  47          */
  48         for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) {
  49                 unsigned int ienb;
  50
  51                 ienb = read_aux_reg(AUX_IENABLE);
  52                 ienb &= ~(1 << i);
  53                 write_aux_reg(AUX_IENABLE, ienb);
  54         }
  55 }
  56
  57 /*
  58  * ARC700 core includes a simple on-chip intc supporting
  59  * -per IRQ enable/disable
  60  * -2 levels of interrupts (high/low)
  61  * -all interrupts being level triggered
  62  *
  63  * To reduce platform code, we assume all IRQs directly hooked-up into intc.
  64  * Platforms with external intc, hence cascaded IRQs, are free to over-ride
  65  * below, per IRQ.
  66  */
  67
  68 static void arc_irq_mask(struct irq_data *data)
  69 {
  70         unsigned int ienb;
  71
  72         ienb = read_aux_reg(AUX_IENABLE);
  73         ienb &= ~(1 << data->hwirq);
  74         write_aux_reg(AUX_IENABLE, ienb);
  75 }
  76
  77 static void arc_irq_unmask(struct irq_data *data)
  78 {
  79         unsigned int ienb;
  80
  81         ienb = read_aux_reg(AUX_IENABLE);
  82         ienb |= (1 << data->hwirq);
  83         write_aux_reg(AUX_IENABLE, ienb);
  84 }
  85
  86 static struct irq_chip onchip_intc = {
  87         .name           = "ARC In-core Intc",
  88         .irq_mask       = arc_irq_mask,
  89         .irq_unmask     = arc_irq_unmask,
  90 };
  91
  92 static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
  93                                irq_hw_number_t hw)
  94 {
  95         switch (hw) {
  96         case TIMER0_IRQ:
  97                 irq_set_percpu_devid(irq);
  98                 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
  99                 break;
 100         default:
 101                 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
 102         }
 103         return 0;
 104 }
 105
 106 static const struct irq_domain_ops arc_intc_domain_ops = {
 107         .xlate = irq_domain_xlate_onecell,
 108         .map = arc_intc_domain_map,
 109 };
 110
 111 static int __init
 112 init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
 113 {
 114         struct irq_domain *root_domain;
 115
 116         if (parent)
 117                 panic("DeviceTree incore intc not a root irq controller\n");
 118
 119         root_domain = irq_domain_add_linear(intc, NR_CPU_IRQS,
 120                                             &arc_intc_domain_ops, NULL);
 121         if (!root_domain)
 122                 panic("root irq domain not avail\n");
 123
 124         /*
 125          * Needed for primary domain lookup to succeed
 126          * This is a primary irqchip, and can never have a parent
 127          */
 128         irq_set_default_host(root_domain);
 129
 130         return 0;
 131 }
 132
 133 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
 134
 135 /*
 136  * arch_local_irq_enable - Enable interrupts.
 137  *
 138  * 1. Explicitly called to re-enable interrupts
 139  * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
 140  *    which maybe in hard ISR itself
 141  *
 142  * Semantics of this function change depending on where it is called from:
 143  *
 144  * -If called from hard-ISR, it must not invert interrupt priorities
 145  *  e.g. suppose TIMER is high priority (Level 2) IRQ
 146  *    Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
 147  *    Here local_irq_enable( ) shd not re-enable lower priority interrupts
 148  * -If called from soft-ISR, it must re-enable all interrupts
 149  *    soft ISR are low prioity jobs which can be very slow, thus all IRQs
 150  *    must be enabled while they run.
 151  *    Now hardware context wise we may still be in L2 ISR (not done rtie)
 152  *    still we must re-enable both L1 and L2 IRQs
 153  *  Another twist is prev scenario with flow being
 154  *     L1 ISR ==> interrupted by L2 ISR  ==> L2 soft ISR
 155  *     here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
 156  *     over-written (this is deficiency in ARC700 Interrupt mechanism)
 157  */
 158
 159 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS    /* Complex version for 2 IRQ levels */
 160
 161 void arch_local_irq_enable(void)
 162 {
 163         unsigned long flags = arch_local_save_flags();
 164
 165         if (flags & STATUS_A2_MASK)
 166                 flags |= STATUS_E2_MASK;
 167         else if (flags & STATUS_A1_MASK)
 168                 flags |= STATUS_E1_MASK;
 169
 170         arch_local_irq_restore(flags);
 171 }
 172
 173 EXPORT_SYMBOL(arch_local_irq_enable);
 174 #endif