arch/arm/mach-bcm/platsmp.c

   1 /*
   2  * Copyright (C) 2014-2015 Broadcom Corporation
   3  * Copyright 2014 Linaro Limited
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation version 2.
   8  *
   9  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  10  * kind, whether express or implied; without even the implied warranty
  11  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/cpumask.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/irqchip/irq-bcm2836.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/sched.h>
  25 #include <linux/sched/clock.h>
  26 #include <linux/smp.h>
  27
  28 #include <asm/cacheflush.h>
  29 #include <asm/smp.h>
  30 #include <asm/smp_plat.h>
  31 #include <asm/smp_scu.h>
  32
  33 /* Size of mapped Cortex A9 SCU address space */
  34 #define CORTEX_A9_SCU_SIZE      0x58
  35
  36 #define SECONDARY_TIMEOUT_NS    NSEC_PER_MSEC   /* 1 msec (in nanoseconds) */
  37 #define BOOT_ADDR_CPUID_MASK    0x3
  38
  39 /* Name of device node property defining secondary boot register location */
  40 #define OF_SECONDARY_BOOT       "secondary-boot-reg"
  41 #define MPIDR_CPUID_BITMASK     0x3
  42
  43 /*
  44  * Enable the Cortex A9 Snoop Control Unit
  45  *
  46  * By the time this is called we already know there are multiple
  47  * cores present.  We assume we're running on a Cortex A9 processor,
  48  * so any trouble getting the base address register or getting the
  49  * SCU base is a problem.
  50  *
  51  * Return 0 if successful or an error code otherwise.
  52  */
  53 static int __init scu_a9_enable(void)
  54 {
  55         unsigned long config_base;
  56         void __iomem *scu_base;
  57
  58         if (!scu_a9_has_base()) {
  59                 pr_err("no configuration base address register!\n");
  60                 return -ENXIO;
  61         }
  62
  63         /* Config base address register value is zero for uniprocessor */
  64         config_base = scu_a9_get_base();
  65         if (!config_base) {
  66                 pr_err("hardware reports only one core\n");
  67                 return -ENOENT;
  68         }
  69
  70         scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
  71         if (!scu_base) {
  72                 pr_err("failed to remap config base (%lu/%u) for SCU\n",
  73                         config_base, CORTEX_A9_SCU_SIZE);
  74                 return -ENOMEM;
  75         }
  76
  77         scu_enable(scu_base);
  78
  79         iounmap(scu_base);      /* That's the last we'll need of this */
  80
  81         return 0;
  82 }
  83
  84 static u32 secondary_boot_addr_for(unsigned int cpu)
  85 {
  86         u32 secondary_boot_addr = 0;
  87         struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
  88
  89         if (!cpu_node) {
  90                 pr_err("Failed to find device tree node for CPU%u\n", cpu);
  91                 return 0;
  92         }
  93
  94         if (of_property_read_u32(cpu_node,
  95                                  OF_SECONDARY_BOOT,
  96                                  &secondary_boot_addr))
  97                 pr_err("required secondary boot register not specified for CPU%u\n",
  98                         cpu);
  99
 100         of_node_put(cpu_node);
 101
 102         return secondary_boot_addr;
 103 }
 104
 105 static int nsp_write_lut(unsigned int cpu)
 106 {
 107         void __iomem *sku_rom_lut;
 108         phys_addr_t secondary_startup_phy;
 109         const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
 110
 111         if (!secondary_boot_addr)
 112                 return -EINVAL;
 113
 114         sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
 115                                       sizeof(phys_addr_t));
 116         if (!sku_rom_lut) {
 117                 pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
 118                 return -ENOMEM;
 119         }
 120
 121         secondary_startup_phy = __pa_symbol(secondary_startup);
 122         BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
 123
 124         writel_relaxed(secondary_startup_phy, sku_rom_lut);
 125
 126         /* Ensure the write is visible to the secondary core */
 127         smp_wmb();
 128
 129         iounmap(sku_rom_lut);
 130
 131         return 0;
 132 }
 133
 134 static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
 135 {
 136         const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
 137
 138         /* Enable the SCU on Cortex A9 based SoCs */
 139         if (scu_a9_enable()) {
 140                 /* Update the CPU present map to reflect uniprocessor mode */
 141                 pr_warn("failed to enable A9 SCU - disabling SMP\n");
 142                 init_cpu_present(&only_cpu_0);
 143         }
 144 }
 145
 146 /*
 147  * The ROM code has the secondary cores looping, waiting for an event.
 148  * When an event occurs each core examines the bottom two bits of the
 149  * secondary boot register.  When a core finds those bits contain its
 150  * own core id, it performs initialization, including computing its boot
 151  * address by clearing the boot register value's bottom two bits.  The
 152  * core signals that it is beginning its execution by writing its boot
 153  * address back to the secondary boot register, and finally jumps to
 154  * that address.
 155  *
 156  * So to start a core executing we need to:
 157  * - Encode the (hardware) CPU id with the bottom bits of the secondary
 158  *   start address.
 159  * - Write that value into the secondary boot register.
 160  * - Generate an event to wake up the secondary CPU(s).
 161  * - Wait for the secondary boot register to be re-written, which
 162  *   indicates the secondary core has started.
 163  */
 164 static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
 165 {
 166         void __iomem *boot_reg;
 167         phys_addr_t boot_func;
 168         u64 start_clock;
 169         u32 cpu_id;
 170         u32 boot_val;
 171         bool timeout = false;
 172         const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
 173
 174         cpu_id = cpu_logical_map(cpu);
 175         if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
 176                 pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
 177                 return -EINVAL;
 178         }
 179
 180         if (!secondary_boot_addr)
 181                 return -EINVAL;
 182
 183         boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr,
 184                                    sizeof(phys_addr_t));
 185         if (!boot_reg) {
 186                 pr_err("unable to map boot register for cpu %u\n", cpu_id);
 187                 return -ENOMEM;
 188         }
 189
 190         /*
 191          * Secondary cores will start in secondary_startup(),
 192          * defined in "arch/arm/kernel/head.S"
 193          */
 194         boot_func = __pa_symbol(secondary_startup);
 195         BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
 196         BUG_ON(boot_func > (phys_addr_t)U32_MAX);
 197
 198         /* The core to start is encoded in the low bits */
 199         boot_val = (u32)boot_func | cpu_id;
 200         writel_relaxed(boot_val, boot_reg);
 201
 202         sev();
 203
 204         /* The low bits will be cleared once the core has started */
 205         start_clock = local_clock();
 206         while (!timeout && readl_relaxed(boot_reg) == boot_val)
 207                 timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
 208
 209         iounmap(boot_reg);
 210
 211         if (!timeout)
 212                 return 0;
 213
 214         pr_err("timeout waiting for cpu %u to start\n", cpu_id);
 215
 216         return -ENXIO;
 217 }
 218
 219 /* Cluster Dormant Control command to bring CPU into a running state */
 220 #define CDC_CMD                 6
 221 #define CDC_CMD_OFFSET          0
 222 #define CDC_CMD_REG(cpu)        (CDC_CMD_OFFSET + 4*(cpu))
 223
 224 /*
 225  * BCM23550 has a Cluster Dormant Control block that keeps the core in
 226  * idle state. A command needs to be sent to the block to bring the CPU
 227  * into running state.
 228  */
 229 static int bcm23550_boot_secondary(unsigned int cpu, struct task_struct *idle)
 230 {
 231         void __iomem *cdc_base;
 232         struct device_node *dn;
 233         char *name;
 234         int ret;
 235
 236         /* Make sure a CDC node exists before booting the
 237          * secondary core.
 238          */
 239         name = "brcm,bcm23550-cdc";
 240         dn = of_find_compatible_node(NULL, NULL, name);
 241         if (!dn) {
 242                 pr_err("unable to find cdc node\n");
 243                 return -ENODEV;
 244         }
 245
 246         cdc_base = of_iomap(dn, 0);
 247         of_node_put(dn);
 248
 249         if (!cdc_base) {
 250                 pr_err("unable to remap cdc base register\n");
 251                 return -ENOMEM;
 252         }
 253
 254         /* Boot the secondary core */
 255         ret = kona_boot_secondary(cpu, idle);
 256         if (ret)
 257                 goto out;
 258
 259         /* Bring this CPU to RUN state so that nIRQ nFIQ
 260          * signals are unblocked.
 261          */
 262         writel_relaxed(CDC_CMD, cdc_base + CDC_CMD_REG(cpu));
 263
 264 out:
 265         iounmap(cdc_base);
 266
 267         return ret;
 268 }
 269
 270 static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
 271 {
 272         int ret;
 273
 274         /*
 275          * After wake up, secondary core branches to the startup
 276          * address programmed at SKU ROM LUT location.
 277          */
 278         ret = nsp_write_lut(cpu);
 279         if (ret) {
 280                 pr_err("unable to write startup addr to SKU ROM LUT\n");
 281                 goto out;
 282         }
 283
 284         /* Send a CPU wakeup interrupt to the secondary core */
 285         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 286
 287 out:
 288         return ret;
 289 }
 290
 291 static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle)
 292 {
 293         void __iomem *intc_base;
 294         struct device_node *dn;
 295         char *name;
 296
 297         name = "brcm,bcm2836-l1-intc";
 298         dn = of_find_compatible_node(NULL, NULL, name);
 299         if (!dn) {
 300                 pr_err("unable to find intc node\n");
 301                 return -ENODEV;
 302         }
 303
 304         intc_base = of_iomap(dn, 0);
 305         of_node_put(dn);
 306
 307         if (!intc_base) {
 308                 pr_err("unable to remap intc base register\n");
 309                 return -ENOMEM;
 310         }
 311
 312         writel(virt_to_phys(secondary_startup),
 313                intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
 314
 315         dsb(sy);
 316         sev();
 317
 318         iounmap(intc_base);
 319
 320         return 0;
 321 }
 322
 323 static const struct smp_operations kona_smp_ops __initconst = {
 324         .smp_prepare_cpus       = bcm_smp_prepare_cpus,
 325         .smp_boot_secondary     = kona_boot_secondary,
 326 };
 327 CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
 328                         &kona_smp_ops);
 329
 330 static const struct smp_operations bcm23550_smp_ops __initconst = {
 331         .smp_boot_secondary     = bcm23550_boot_secondary,
 332 };
 333 CPU_METHOD_OF_DECLARE(bcm_smp_bcm23550, "brcm,bcm23550",
 334                         &bcm23550_smp_ops);
 335
 336 static const struct smp_operations nsp_smp_ops __initconst = {
 337         .smp_prepare_cpus       = bcm_smp_prepare_cpus,
 338         .smp_boot_secondary     = nsp_boot_secondary,
 339 };
 340 CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
 341
 342 const struct smp_operations bcm2836_smp_ops __initconst = {
 343         .smp_boot_secondary     = bcm2836_boot_secondary,
 344 };
 345 CPU_METHOD_OF_DECLARE(bcm_smp_bcm2836, "brcm,bcm2836-smp", &bcm2836_smp_ops);