arch/arm/mach-imx/cpuidle-imx6sx.c

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/cpuidle.h>
  10 #include <linux/cpu_pm.h>
  11 #include <linux/module.h>
  12 #include <asm/cacheflush.h>
  13 #include <asm/cpuidle.h>
  14 #include <asm/suspend.h>
  15
  16 #include "common.h"
  17 #include "cpuidle.h"
  18
  19 static int imx6sx_idle_finish(unsigned long val)
  20 {
  21         /*
  22          * for Cortex-A7 which has an internal L2
  23          * cache, need to flush it before powering
  24          * down ARM platform, since flushing L1 cache
  25          * here again has very small overhead, compared
  26          * to adding conditional code for L2 cache type,
  27          * just call flush_cache_all() is fine.
  28          */
  29         flush_cache_all();
  30         cpu_do_idle();
  31
  32         return 0;
  33 }
  34
  35 static int imx6sx_enter_wait(struct cpuidle_device *dev,
  36                             struct cpuidle_driver *drv, int index)
  37 {
  38         imx6_set_lpm(WAIT_UNCLOCKED);
  39
  40         switch (index) {
  41         case 1:
  42                 cpu_do_idle();
  43                 break;
  44         case 2:
  45                 imx6_enable_rbc(true);
  46                 imx_gpc_set_arm_power_in_lpm(true);
  47                 imx_set_cpu_jump(0, v7_cpu_resume);
  48                 /* Need to notify there is a cpu pm operation. */
  49                 cpu_pm_enter();
  50                 cpu_cluster_pm_enter();
  51
  52                 cpu_suspend(0, imx6sx_idle_finish);
  53
  54                 cpu_cluster_pm_exit();
  55                 cpu_pm_exit();
  56                 imx_gpc_set_arm_power_in_lpm(false);
  57                 imx6_enable_rbc(false);
  58                 break;
  59         default:
  60                 break;
  61         }
  62
  63         imx6_set_lpm(WAIT_CLOCKED);
  64
  65         return index;
  66 }
  67
  68 static struct cpuidle_driver imx6sx_cpuidle_driver = {
  69         .name = "imx6sx_cpuidle",
  70         .owner = THIS_MODULE,
  71         .states = {
  72                 /* WFI */
  73                 ARM_CPUIDLE_WFI_STATE,
  74                 /* WAIT */
  75                 {
  76                         .exit_latency = 50,
  77                         .target_residency = 75,
  78                         .flags = CPUIDLE_FLAG_TIMER_STOP,
  79                         .enter = imx6sx_enter_wait,
  80                         .name = "WAIT",
  81                         .desc = "Clock off",
  82                 },
  83                 /* WAIT + ARM power off  */
  84                 {
  85                         /*
  86                          * ARM gating 31us * 5 + RBC clear 65us
  87                          * and some margin for SW execution, here set it
  88                          * to 300us.
  89                          */
  90                         .exit_latency = 300,
  91                         .target_residency = 500,
  92                         .enter = imx6sx_enter_wait,
  93                         .name = "LOW-POWER-IDLE",
  94                         .desc = "ARM power off",
  95                 },
  96         },
  97         .state_count = 3,
  98         .safe_state_index = 0,
  99 };
 100
 101 int __init imx6sx_cpuidle_init(void)
 102 {
 103         imx6_set_int_mem_clk_lpm(true);
 104         imx6_enable_rbc(false);
 105         /*
 106          * set ARM power up/down timing to the fastest,
 107          * sw2iso and sw can be set to one 32K cycle = 31us
 108          * except for power up sw2iso which need to be
 109          * larger than LDO ramp up time.
 110          */
 111         imx_gpc_set_arm_power_up_timing(2, 1);
 112         imx_gpc_set_arm_power_down_timing(1, 1);
 113
 114         return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
 115 }