arch/arm/mach-omap2/cm2_44xx.h

   1 /*
   2  * OMAP44xx CM2 instance offset macros
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
  22  *     or "OMAP4430".
  23  */
  24
  25 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
  26 #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
  27
  28 /* CM2 base address */
  29 #define OMAP4430_CM2_BASE               0x4a008000
  30
  31 #define OMAP44XX_CM2_REGADDR(inst, reg)                         \
  32         OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
  33
  34 /* CM2 instances */
  35 #define OMAP4430_CM2_OCP_SOCKET_INST    0x0000
  36 #define OMAP4430_CM2_CKGEN_INST         0x0100
  37 #define OMAP4430_CM2_ALWAYS_ON_INST     0x0600
  38 #define OMAP4430_CM2_CORE_INST          0x0700
  39 #define OMAP4430_CM2_IVAHD_INST         0x0f00
  40 #define OMAP4430_CM2_CAM_INST           0x1000
  41 #define OMAP4430_CM2_DSS_INST           0x1100
  42 #define OMAP4430_CM2_GFX_INST           0x1200
  43 #define OMAP4430_CM2_L3INIT_INST        0x1300
  44 #define OMAP4430_CM2_L4PER_INST         0x1400
  45 #define OMAP4430_CM2_CEFUSE_INST        0x1600
  46 #define OMAP4430_CM2_RESTORE_INST       0x1e00
  47 #define OMAP4430_CM2_INSTR_INST         0x1f00
  48
  49 /* CM2 clockdomain register offsets (from instance start) */
  50 #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS     0x0000
  51 #define OMAP4430_CM2_CORE_L3_1_CDOFFS           0x0000
  52 #define OMAP4430_CM2_CORE_L3_2_CDOFFS           0x0100
  53 #define OMAP4430_CM2_CORE_DUCATI_CDOFFS         0x0200
  54 #define OMAP4430_CM2_CORE_SDMA_CDOFFS           0x0300
  55 #define OMAP4430_CM2_CORE_MEMIF_CDOFFS          0x0400
  56 #define OMAP4430_CM2_CORE_D2D_CDOFFS            0x0500
  57 #define OMAP4430_CM2_CORE_L4CFG_CDOFFS          0x0600
  58 #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS        0x0700
  59 #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS         0x0000
  60 #define OMAP4430_CM2_CAM_CAM_CDOFFS             0x0000
  61 #define OMAP4430_CM2_DSS_DSS_CDOFFS             0x0000
  62 #define OMAP4430_CM2_GFX_GFX_CDOFFS             0x0000
  63 #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS       0x0000
  64 #define OMAP4430_CM2_L4PER_L4PER_CDOFFS         0x0000
  65 #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS         0x0180
  66 #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS       0x0000
  67
  68 /* CM2 */
  69
  70 /* CM2.OCP_SOCKET_CM2 register offsets */
  71 #define OMAP4_REVISION_CM2_OFFSET                       0x0000
  72 #define OMAP4430_REVISION_CM2                           OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000)
  73 #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET           0x0040
  74 #define OMAP4430_CM_CM2_PROFILING_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040)
  75
  76 /* CM2.CKGEN_CM2 register offsets */
  77 #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET          0x0000
  78 #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000)
  79 #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET                0x0004
  80 #define OMAP4430_CM_CLKSEL_USB_60MHZ                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004)
  81 #define OMAP4_CM_SCALE_FCLK_OFFSET                      0x0008
  82 #define OMAP4430_CM_SCALE_FCLK                          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008)
  83 #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET                 0x0010
  84 #define OMAP4430_CM_CORE_DVFS_PERF1                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010)
  85 #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET                 0x0014
  86 #define OMAP4430_CM_CORE_DVFS_PERF2                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014)
  87 #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET                 0x0018
  88 #define OMAP4430_CM_CORE_DVFS_PERF3                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018)
  89 #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET                 0x001c
  90 #define OMAP4430_CM_CORE_DVFS_PERF4                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c)
  91 #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET               0x0024
  92 #define OMAP4430_CM_CORE_DVFS_CURRENT                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024)
  93 #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET             0x0028
  94 #define OMAP4430_CM_IVA_DVFS_PERF_TESLA                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028)
  95 #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET             0x002c
  96 #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c)
  97 #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET               0x0030
  98 #define OMAP4430_CM_IVA_DVFS_PERF_ABE                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030)
  99 #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET                0x0038
 100 #define OMAP4430_CM_IVA_DVFS_CURRENT                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038)
 101 #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET                0x0040
 102 #define OMAP4430_CM_CLKMODE_DPLL_PER                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040)
 103 #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET                 0x0044
 104 #define OMAP4430_CM_IDLEST_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044)
 105 #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET               0x0048
 106 #define OMAP4430_CM_AUTOIDLE_DPLL_PER                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048)
 107 #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET                 0x004c
 108 #define OMAP4430_CM_CLKSEL_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c)
 109 #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET                 0x0050
 110 #define OMAP4430_CM_DIV_M2_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050)
 111 #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET                 0x0054
 112 #define OMAP4430_CM_DIV_M3_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054)
 113 #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET                 0x0058
 114 #define OMAP4430_CM_DIV_M4_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058)
 115 #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET                 0x005c
 116 #define OMAP4430_CM_DIV_M5_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c)
 117 #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET                 0x0060
 118 #define OMAP4430_CM_DIV_M6_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060)
 119 #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET                 0x0064
 120 #define OMAP4430_CM_DIV_M7_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
 121 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET         0x0068
 122 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
 123 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET         0x006c
 124 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
 125 #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET                0x0080
 126 #define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
 127 #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET                 0x0084
 128 #define OMAP4430_CM_IDLEST_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084)
 129 #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET               0x0088
 130 #define OMAP4430_CM_AUTOIDLE_DPLL_USB                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088)
 131 #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET                 0x008c
 132 #define OMAP4430_CM_CLKSEL_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c)
 133 #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET                 0x0090
 134 #define OMAP4430_CM_DIV_M2_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
 135 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET         0x00a8
 136 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
 137 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET         0x00ac
 138 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
 139 #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET              0x00b4
 140 #define OMAP4430_CM_CLKDCOLDO_DPLL_USB                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
 141 #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET             0x00c0
 142 #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0)
 143 #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET              0x00c4
 144 #define OMAP4430_CM_IDLEST_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4)
 145 #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET            0x00c8
 146 #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8)
 147 #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET              0x00cc
 148 #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc)
 149 #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET              0x00d0
 150 #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
 151 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET      0x00e8
 152 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
 153 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET      0x00ec
 154 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
 155
 156 /* CM2.ALWAYS_ON_CM2 register offsets */
 157 #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET                 0x0000
 158 #define OMAP4430_CM_ALWON_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000)
 159 #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET           0x0020
 160 #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020)
 161 #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET            0x0028
 162 #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028)
 163 #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET            0x0030
 164 #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030)
 165 #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET           0x0038
 166 #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038)
 167 #define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET            0x0040
 168 #define OMAP4430_CM_ALWON_USBPHY_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040)
 169
 170 /* CM2.CORE_CM2 register offsets */
 171 #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET                  0x0000
 172 #define OMAP4430_CM_L3_1_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000)
 173 #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET                 0x0008
 174 #define OMAP4430_CM_L3_1_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008)
 175 #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET               0x0020
 176 #define OMAP4430_CM_L3_1_L3_1_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020)
 177 #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET                  0x0100
 178 #define OMAP4430_CM_L3_2_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100)
 179 #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET                 0x0108
 180 #define OMAP4430_CM_L3_2_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108)
 181 #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET               0x0120
 182 #define OMAP4430_CM_L3_2_L3_2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120)
 183 #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET               0x0128
 184 #define OMAP4430_CM_L3_2_GPMC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128)
 185 #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET           0x0130
 186 #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130)
 187 #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET                0x0200
 188 #define OMAP4430_CM_DUCATI_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200)
 189 #define OMAP4_CM_DUCATI_STATICDEP_OFFSET                0x0204
 190 #define OMAP4430_CM_DUCATI_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204)
 191 #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET               0x0208
 192 #define OMAP4430_CM_DUCATI_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208)
 193 #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET           0x0220
 194 #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220)
 195 #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET                  0x0300
 196 #define OMAP4430_CM_SDMA_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300)
 197 #define OMAP4_CM_SDMA_STATICDEP_OFFSET                  0x0304
 198 #define OMAP4430_CM_SDMA_STATICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304)
 199 #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET                 0x0308
 200 #define OMAP4430_CM_SDMA_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308)
 201 #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET               0x0320
 202 #define OMAP4430_CM_SDMA_SDMA_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320)
 203 #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET                 0x0400
 204 #define OMAP4430_CM_MEMIF_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400)
 205 #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET               0x0420
 206 #define OMAP4430_CM_MEMIF_DMM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420)
 207 #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET           0x0428
 208 #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428)
 209 #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET            0x0430
 210 #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430)
 211 #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET            0x0438
 212 #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438)
 213 #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET               0x0440
 214 #define OMAP4430_CM_MEMIF_DLL_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440)
 215 #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET           0x0450
 216 #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450)
 217 #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET           0x0458
 218 #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458)
 219 #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET             0x0460
 220 #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460)
 221 #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET                   0x0500
 222 #define OMAP4430_CM_D2D_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500)
 223 #define OMAP4_CM_D2D_STATICDEP_OFFSET                   0x0504
 224 #define OMAP4430_CM_D2D_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504)
 225 #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET                  0x0508
 226 #define OMAP4430_CM_D2D_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
 227 #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET               0x0520
 228 #define OMAP4430_CM_D2D_SAD2D_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
 229 #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET           0x0528
 230 #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
 231 #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET            0x0530
 232 #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
 233 #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET                 0x0600
 234 #define OMAP4430_CM_L4CFG_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600)
 235 #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET                0x0608
 236 #define OMAP4430_CM_L4CFG_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608)
 237 #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET            0x0620
 238 #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620)
 239 #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET            0x0628
 240 #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628)
 241 #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET           0x0630
 242 #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630)
 243 #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET           0x0638
 244 #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638)
 245 #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET               0x0700
 246 #define OMAP4430_CM_L3INSTR_CLKSTCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700)
 247 #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET            0x0720
 248 #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720)
 249 #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET        0x0728
 250 #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728)
 251 #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET         0x0740
 252 #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740)
 253
 254 /* CM2.IVAHD_CM2 register offsets */
 255 #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET                 0x0000
 256 #define OMAP4430_CM_IVAHD_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000)
 257 #define OMAP4_CM_IVAHD_STATICDEP_OFFSET                 0x0004
 258 #define OMAP4430_CM_IVAHD_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004)
 259 #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET                0x0008
 260 #define OMAP4430_CM_IVAHD_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008)
 261 #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET             0x0020
 262 #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020)
 263 #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET               0x0028
 264 #define OMAP4430_CM_IVAHD_SL2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028)
 265
 266 /* CM2.CAM_CM2 register offsets */
 267 #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET                   0x0000
 268 #define OMAP4430_CM_CAM_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000)
 269 #define OMAP4_CM_CAM_STATICDEP_OFFSET                   0x0004
 270 #define OMAP4430_CM_CAM_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004)
 271 #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET                  0x0008
 272 #define OMAP4430_CM_CAM_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008)
 273 #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET                 0x0020
 274 #define OMAP4430_CM_CAM_ISS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020)
 275 #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET                0x0028
 276 #define OMAP4430_CM_CAM_FDIF_CLKCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028)
 277
 278 /* CM2.DSS_CM2 register offsets */
 279 #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET                   0x0000
 280 #define OMAP4430_CM_DSS_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000)
 281 #define OMAP4_CM_DSS_STATICDEP_OFFSET                   0x0004
 282 #define OMAP4430_CM_DSS_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004)
 283 #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET                  0x0008
 284 #define OMAP4430_CM_DSS_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008)
 285 #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET                 0x0020
 286 #define OMAP4430_CM_DSS_DSS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020)
 287 #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET               0x0028
 288 #define OMAP4430_CM_DSS_DEISS_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028)
 289
 290 /* CM2.GFX_CM2 register offsets */
 291 #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET                   0x0000
 292 #define OMAP4430_CM_GFX_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000)
 293 #define OMAP4_CM_GFX_STATICDEP_OFFSET                   0x0004
 294 #define OMAP4430_CM_GFX_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004)
 295 #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET                  0x0008
 296 #define OMAP4430_CM_GFX_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008)
 297 #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET                 0x0020
 298 #define OMAP4430_CM_GFX_GFX_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020)
 299
 300 /* CM2.L3INIT_CM2 register offsets */
 301 #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET                0x0000
 302 #define OMAP4430_CM_L3INIT_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000)
 303 #define OMAP4_CM_L3INIT_STATICDEP_OFFSET                0x0004
 304 #define OMAP4430_CM_L3INIT_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004)
 305 #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET               0x0008
 306 #define OMAP4430_CM_L3INIT_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008)
 307 #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET             0x0028
 308 #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028)
 309 #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET             0x0030
 310 #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030)
 311 #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET              0x0038
 312 #define OMAP4430_CM_L3INIT_HSI_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038)
 313 #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET          0x0040
 314 #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040)
 315 #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET         0x0058
 316 #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058)
 317 #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET          0x0060
 318 #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060)
 319 #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET          0x0068
 320 #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068)
 321 #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET            0x0078
 322 #define OMAP4430_CM_L3INIT_P1500_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078)
 323 #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET             0x0080
 324 #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080)
 325 #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET             0x0088
 326 #define OMAP4430_CM_L3INIT_SATA_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088)
 327 #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET            0x0090
 328 #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090)
 329 #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET           0x0098
 330 #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098)
 331 #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET            0x00a8
 332 #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8)
 333 #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET             0x00c0
 334 #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0)
 335 #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET             0x00c8
 336 #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8)
 337 #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET      0x00d0
 338 #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0)
 339 #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET    0x00e0
 340 #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0)
 341
 342 /* CM2.L4PER_CM2 register offsets */
 343 #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET                 0x0000
 344 #define OMAP4430_CM_L4PER_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000)
 345 #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET                0x0008
 346 #define OMAP4430_CM_L4PER_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008)
 347 #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET               0x0020
 348 #define OMAP4430_CM_L4PER_ADC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020)
 349 #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET         0x0028
 350 #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028)
 351 #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET         0x0030
 352 #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030)
 353 #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET          0x0038
 354 #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038)
 355 #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET          0x0040
 356 #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040)
 357 #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET          0x0048
 358 #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048)
 359 #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET          0x0050
 360 #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050)
 361 #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET               0x0058
 362 #define OMAP4430_CM_L4PER_ELM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058)
 363 #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET             0x0060
 364 #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060)
 365 #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET             0x0068
 366 #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068)
 367 #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET             0x0070
 368 #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070)
 369 #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET             0x0078
 370 #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078)
 371 #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET             0x0080
 372 #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080)
 373 #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET             0x0088
 374 #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088)
 375 #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET             0x0090
 376 #define OMAP4430_CM_L4PER_HECC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090)
 377 #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET             0x0098
 378 #define OMAP4430_CM_L4PER_HECC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098)
 379 #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET              0x00a0
 380 #define OMAP4430_CM_L4PER_I2C1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0)
 381 #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET              0x00a8
 382 #define OMAP4430_CM_L4PER_I2C2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8)
 383 #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET              0x00b0
 384 #define OMAP4430_CM_L4PER_I2C3_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0)
 385 #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET              0x00b8
 386 #define OMAP4430_CM_L4PER_I2C4_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8)
 387 #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET             0x00c0
 388 #define OMAP4430_CM_L4PER_L4PER_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0)
 389 #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET            0x00d0
 390 #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0)
 391 #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET            0x00d8
 392 #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8)
 393 #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET            0x00e0
 394 #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0)
 395 #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET             0x00e8
 396 #define OMAP4430_CM_L4PER_MGATE_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8)
 397 #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET            0x00f0
 398 #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0)
 399 #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET            0x00f8
 400 #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8)
 401 #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET            0x0100
 402 #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100)
 403 #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET            0x0108
 404 #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108)
 405 #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET            0x0120
 406 #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120)
 407 #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET            0x0128
 408 #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128)
 409 #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET           0x0130
 410 #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130)
 411 #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET          0x0138
 412 #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138)
 413 #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET             0x0140
 414 #define OMAP4430_CM_L4PER_UART1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140)
 415 #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET             0x0148
 416 #define OMAP4430_CM_L4PER_UART2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148)
 417 #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET             0x0150
 418 #define OMAP4430_CM_L4PER_UART3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150)
 419 #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET             0x0158
 420 #define OMAP4430_CM_L4PER_UART4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158)
 421 #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET            0x0160
 422 #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160)
 423 #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET              0x0168
 424 #define OMAP4430_CM_L4PER_I2C5_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168)
 425 #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET                 0x0180
 426 #define OMAP4430_CM_L4SEC_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180)
 427 #define OMAP4_CM_L4SEC_STATICDEP_OFFSET                 0x0184
 428 #define OMAP4430_CM_L4SEC_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184)
 429 #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET                0x0188
 430 #define OMAP4430_CM_L4SEC_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188)
 431 #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET              0x01a0
 432 #define OMAP4430_CM_L4SEC_AES1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0)
 433 #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET              0x01a8
 434 #define OMAP4430_CM_L4SEC_AES2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8)
 435 #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET           0x01b0
 436 #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0)
 437 #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET          0x01b8
 438 #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8)
 439 #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET               0x01c0
 440 #define OMAP4430_CM_L4SEC_RNG_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0)
 441 #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET          0x01c8
 442 #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8)
 443 #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET         0x01d8
 444 #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8)
 445
 446 /* CM2.CEFUSE_CM2 register offsets */
 447 #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET                0x0000
 448 #define OMAP4430_CM_CEFUSE_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000)
 449 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
 450 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
 451
 452 #endif