arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * XXX handle crossbar/shared link difference for L3?
  13  * XXX these should be marked initdata for multi-OMAP kernels
  14  */
  15
  16 #include <linux/i2c-omap.h>
  17 #include <linux/platform_data/spi-omap2-mcspi.h>
  18 #include <linux/omap-dma.h>
  19 #include <plat/dmtimer.h>
  20
  21 #include "omap_hwmod.h"
  22 #include "l3_2xxx.h"
  23 #include "l4_2xxx.h"
  24
  25 #include "omap_hwmod_common_data.h"
  26
  27 #include "cm-regbits-24xx.h"
  28 #include "prm-regbits-24xx.h"
  29 #include "i2c.h"
  30 #include "mmc.h"
  31 #include "serial.h"
  32 #include "wd_timer.h"
  33
  34 /*
  35  * OMAP2420 hardware module integration data
  36  *
  37  * All of the data in this section should be autogeneratable from the
  38  * TI hardware database or other technical documentation.  Data that
  39  * is driver-specific or driver-kernel integration-specific belongs
  40  * elsewhere.
  41  */
  42
  43 /*
  44  * IP blocks
  45  */
  46
  47 /* IVA1 (IVA1) */
  48 static struct omap_hwmod_class iva1_hwmod_class = {
  49         .name           = "iva1",
  50 };
  51
  52 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
  53         { .name = "iva", .rst_shift = 8 },
  54 };
  55
  56 static struct omap_hwmod omap2420_iva_hwmod = {
  57         .name           = "iva",
  58         .class          = &iva1_hwmod_class,
  59         .clkdm_name     = "iva1_clkdm",
  60         .rst_lines      = omap2420_iva_resets,
  61         .rst_lines_cnt  = ARRAY_SIZE(omap2420_iva_resets),
  62         .main_clk       = "iva1_ifck",
  63 };
  64
  65 /* DSP */
  66 static struct omap_hwmod_class dsp_hwmod_class = {
  67         .name           = "dsp",
  68 };
  69
  70 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
  71         { .name = "logic", .rst_shift = 0 },
  72         { .name = "mmu", .rst_shift = 1 },
  73 };
  74
  75 static struct omap_hwmod omap2420_dsp_hwmod = {
  76         .name           = "dsp",
  77         .class          = &dsp_hwmod_class,
  78         .clkdm_name     = "dsp_clkdm",
  79         .rst_lines      = omap2420_dsp_resets,
  80         .rst_lines_cnt  = ARRAY_SIZE(omap2420_dsp_resets),
  81         .main_clk       = "dsp_fck",
  82 };
  83
  84 /* I2C common */
  85 static struct omap_hwmod_class_sysconfig i2c_sysc = {
  86         .rev_offs       = 0x00,
  87         .sysc_offs      = 0x20,
  88         .syss_offs      = 0x10,
  89         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  90         .sysc_fields    = &omap_hwmod_sysc_type1,
  91 };
  92
  93 static struct omap_hwmod_class i2c_class = {
  94         .name           = "i2c",
  95         .sysc           = &i2c_sysc,
  96         .rev            = OMAP_I2C_IP_VERSION_1,
  97         .reset          = &omap_i2c_reset,
  98 };
  99
 100 static struct omap_i2c_dev_attr i2c_dev_attr = {
 101         .flags          = OMAP_I2C_FLAG_NO_FIFO |
 102                           OMAP_I2C_FLAG_SIMPLE_CLOCK |
 103                           OMAP_I2C_FLAG_16BIT_DATA_REG |
 104                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 105 };
 106
 107 /* I2C1 */
 108 static struct omap_hwmod omap2420_i2c1_hwmod = {
 109         .name           = "i2c1",
 110         .main_clk       = "i2c1_fck",
 111         .prcm           = {
 112                 .omap2 = {
 113                         .module_offs = CORE_MOD,
 114                         .idlest_reg_id = 1,
 115                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
 116                 },
 117         },
 118         .class          = &i2c_class,
 119         .dev_attr       = &i2c_dev_attr,
 120         /*
 121          * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
 122          * while a transfer is active seems to cause the I2C block to
 123          * timeout. Why? Good question."
 124          */
 125         .flags          = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
 126 };
 127
 128 /* I2C2 */
 129 static struct omap_hwmod omap2420_i2c2_hwmod = {
 130         .name           = "i2c2",
 131         .main_clk       = "i2c2_fck",
 132         .prcm           = {
 133                 .omap2 = {
 134                         .module_offs = CORE_MOD,
 135                         .idlest_reg_id = 1,
 136                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
 137                 },
 138         },
 139         .class          = &i2c_class,
 140         .dev_attr       = &i2c_dev_attr,
 141         .flags          = HWMOD_16BIT_REG,
 142 };
 143
 144 /* dma attributes */
 145 static struct omap_dma_dev_attr dma_dev_attr = {
 146         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 147                                                 IS_CSSA_32 | IS_CDSA_32,
 148         .lch_count = 32,
 149 };
 150
 151 static struct omap_hwmod omap2420_dma_system_hwmod = {
 152         .name           = "dma",
 153         .class          = &omap2xxx_dma_hwmod_class,
 154         .main_clk       = "core_l3_ck",
 155         .dev_attr       = &dma_dev_attr,
 156         .flags          = HWMOD_NO_IDLEST,
 157 };
 158
 159 /* mailbox */
 160 static struct omap_hwmod omap2420_mailbox_hwmod = {
 161         .name           = "mailbox",
 162         .class          = &omap2xxx_mailbox_hwmod_class,
 163         .main_clk       = "mailboxes_ick",
 164         .prcm           = {
 165                 .omap2 = {
 166                         .module_offs = CORE_MOD,
 167                         .idlest_reg_id = 1,
 168                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
 169                 },
 170         },
 171 };
 172
 173 /*
 174  * 'mcbsp' class
 175  * multi channel buffered serial port controller
 176  */
 177
 178 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
 179         .name = "mcbsp",
 180 };
 181
 182 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 183         { .role = "pad_fck", .clk = "mcbsp_clks" },
 184         { .role = "prcm_fck", .clk = "func_96m_ck" },
 185 };
 186
 187 /* mcbsp1 */
 188 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 189         .name           = "mcbsp1",
 190         .class          = &omap2420_mcbsp_hwmod_class,
 191         .main_clk       = "mcbsp1_fck",
 192         .prcm           = {
 193                 .omap2 = {
 194                         .module_offs = CORE_MOD,
 195                         .idlest_reg_id = 1,
 196                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
 197                 },
 198         },
 199         .opt_clks       = mcbsp_opt_clks,
 200         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 201 };
 202
 203 /* mcbsp2 */
 204 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
 205         .name           = "mcbsp2",
 206         .class          = &omap2420_mcbsp_hwmod_class,
 207         .main_clk       = "mcbsp2_fck",
 208         .prcm           = {
 209                 .omap2 = {
 210                         .module_offs = CORE_MOD,
 211                         .idlest_reg_id = 1,
 212                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
 213                 },
 214         },
 215         .opt_clks       = mcbsp_opt_clks,
 216         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 217 };
 218
 219 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
 220         .rev_offs       = 0x3c,
 221         .sysc_offs      = 0x64,
 222         .syss_offs      = 0x68,
 223         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 224         .sysc_fields    = &omap_hwmod_sysc_type1,
 225 };
 226
 227 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
 228         .name   = "msdi",
 229         .sysc   = &omap2420_msdi_sysc,
 230         .reset  = &omap_msdi_reset,
 231 };
 232
 233 /* msdi1 */
 234 static struct omap_hwmod omap2420_msdi1_hwmod = {
 235         .name           = "msdi1",
 236         .class          = &omap2420_msdi_hwmod_class,
 237         .main_clk       = "mmc_fck",
 238         .prcm           = {
 239                 .omap2 = {
 240                         .module_offs = CORE_MOD,
 241                         .idlest_reg_id = 1,
 242                         .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
 243                 },
 244         },
 245         .flags          = HWMOD_16BIT_REG,
 246 };
 247
 248 /* HDQ1W/1-wire */
 249 static struct omap_hwmod omap2420_hdq1w_hwmod = {
 250         .name           = "hdq1w",
 251         .main_clk       = "hdq_fck",
 252         .prcm           = {
 253                 .omap2 = {
 254                         .module_offs = CORE_MOD,
 255                         .idlest_reg_id = 1,
 256                         .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
 257                 },
 258         },
 259         .class          = &omap2_hdq1w_class,
 260 };
 261
 262 /*
 263  * interfaces
 264  */
 265
 266 /* L4 CORE -> I2C1 interface */
 267 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 268         .master         = &omap2xxx_l4_core_hwmod,
 269         .slave          = &omap2420_i2c1_hwmod,
 270         .clk            = "i2c1_ick",
 271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 272 };
 273
 274 /* L4 CORE -> I2C2 interface */
 275 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 276         .master         = &omap2xxx_l4_core_hwmod,
 277         .slave          = &omap2420_i2c2_hwmod,
 278         .clk            = "i2c2_ick",
 279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 280 };
 281
 282 /* IVA <- L3 interface */
 283 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 284         .master         = &omap2xxx_l3_main_hwmod,
 285         .slave          = &omap2420_iva_hwmod,
 286         .clk            = "core_l3_ck",
 287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 288 };
 289
 290 /* DSP <- L3 interface */
 291 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
 292         .master         = &omap2xxx_l3_main_hwmod,
 293         .slave          = &omap2420_dsp_hwmod,
 294         .clk            = "dsp_ick",
 295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 296 };
 297
 298 /* l4_wkup -> timer1 */
 299 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 300         .master         = &omap2xxx_l4_wkup_hwmod,
 301         .slave          = &omap2xxx_timer1_hwmod,
 302         .clk            = "gpt1_ick",
 303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 304 };
 305
 306 /* l4_wkup -> wd_timer2 */
 307 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 308         .master         = &omap2xxx_l4_wkup_hwmod,
 309         .slave          = &omap2xxx_wd_timer2_hwmod,
 310         .clk            = "mpu_wdt_ick",
 311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 312 };
 313
 314 /* l4_wkup -> gpio1 */
 315 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
 316         .master         = &omap2xxx_l4_wkup_hwmod,
 317         .slave          = &omap2xxx_gpio1_hwmod,
 318         .clk            = "gpios_ick",
 319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 320 };
 321
 322 /* l4_wkup -> gpio2 */
 323 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
 324         .master         = &omap2xxx_l4_wkup_hwmod,
 325         .slave          = &omap2xxx_gpio2_hwmod,
 326         .clk            = "gpios_ick",
 327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 328 };
 329
 330 /* l4_wkup -> gpio3 */
 331 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
 332         .master         = &omap2xxx_l4_wkup_hwmod,
 333         .slave          = &omap2xxx_gpio3_hwmod,
 334         .clk            = "gpios_ick",
 335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 336 };
 337
 338 /* l4_wkup -> gpio4 */
 339 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
 340         .master         = &omap2xxx_l4_wkup_hwmod,
 341         .slave          = &omap2xxx_gpio4_hwmod,
 342         .clk            = "gpios_ick",
 343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 344 };
 345
 346 /* dma_system -> L3 */
 347 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
 348         .master         = &omap2420_dma_system_hwmod,
 349         .slave          = &omap2xxx_l3_main_hwmod,
 350         .clk            = "core_l3_ck",
 351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 352 };
 353
 354 /* l4_core -> dma_system */
 355 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
 356         .master         = &omap2xxx_l4_core_hwmod,
 357         .slave          = &omap2420_dma_system_hwmod,
 358         .clk            = "sdma_ick",
 359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 360 };
 361
 362 /* l4_core -> mailbox */
 363 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
 364         .master         = &omap2xxx_l4_core_hwmod,
 365         .slave          = &omap2420_mailbox_hwmod,
 366         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 367 };
 368
 369 /* l4_core -> mcbsp1 */
 370 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
 371         .master         = &omap2xxx_l4_core_hwmod,
 372         .slave          = &omap2420_mcbsp1_hwmod,
 373         .clk            = "mcbsp1_ick",
 374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 375 };
 376
 377 /* l4_core -> mcbsp2 */
 378 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
 379         .master         = &omap2xxx_l4_core_hwmod,
 380         .slave          = &omap2420_mcbsp2_hwmod,
 381         .clk            = "mcbsp2_ick",
 382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 383 };
 384
 385 /* l4_core -> msdi1 */
 386 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
 387         .master         = &omap2xxx_l4_core_hwmod,
 388         .slave          = &omap2420_msdi1_hwmod,
 389         .clk            = "mmc_ick",
 390         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 391 };
 392
 393 /* l4_core -> hdq1w interface */
 394 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
 395         .master         = &omap2xxx_l4_core_hwmod,
 396         .slave          = &omap2420_hdq1w_hwmod,
 397         .clk            = "hdq_ick",
 398         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 399         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 400 };
 401
 402
 403 /* l4_wkup -> 32ksync_counter */
 404 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
 405         .master         = &omap2xxx_l4_wkup_hwmod,
 406         .slave          = &omap2xxx_counter_32k_hwmod,
 407         .clk            = "sync_32k_ick",
 408         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 409 };
 410
 411 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
 412         .master         = &omap2xxx_l3_main_hwmod,
 413         .slave          = &omap2xxx_gpmc_hwmod,
 414         .clk            = "core_l3_ck",
 415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 416 };
 417
 418 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 419         &omap2xxx_l3_main__l4_core,
 420         &omap2xxx_mpu__l3_main,
 421         &omap2xxx_dss__l3,
 422         &omap2xxx_l4_core__mcspi1,
 423         &omap2xxx_l4_core__mcspi2,
 424         &omap2xxx_l4_core__l4_wkup,
 425         &omap2_l4_core__uart1,
 426         &omap2_l4_core__uart2,
 427         &omap2_l4_core__uart3,
 428         &omap2420_l4_core__i2c1,
 429         &omap2420_l4_core__i2c2,
 430         &omap2420_l3__iva,
 431         &omap2420_l3__dsp,
 432         &omap2420_l4_wkup__timer1,
 433         &omap2xxx_l4_core__timer2,
 434         &omap2xxx_l4_core__timer3,
 435         &omap2xxx_l4_core__timer4,
 436         &omap2xxx_l4_core__timer5,
 437         &omap2xxx_l4_core__timer6,
 438         &omap2xxx_l4_core__timer7,
 439         &omap2xxx_l4_core__timer8,
 440         &omap2xxx_l4_core__timer9,
 441         &omap2xxx_l4_core__timer10,
 442         &omap2xxx_l4_core__timer11,
 443         &omap2xxx_l4_core__timer12,
 444         &omap2420_l4_wkup__wd_timer2,
 445         &omap2xxx_l4_core__dss,
 446         &omap2xxx_l4_core__dss_dispc,
 447         &omap2xxx_l4_core__dss_rfbi,
 448         &omap2xxx_l4_core__dss_venc,
 449         &omap2420_l4_wkup__gpio1,
 450         &omap2420_l4_wkup__gpio2,
 451         &omap2420_l4_wkup__gpio3,
 452         &omap2420_l4_wkup__gpio4,
 453         &omap2420_dma_system__l3,
 454         &omap2420_l4_core__dma_system,
 455         &omap2420_l4_core__mailbox,
 456         &omap2420_l4_core__mcbsp1,
 457         &omap2420_l4_core__mcbsp2,
 458         &omap2420_l4_core__msdi1,
 459         &omap2xxx_l4_core__rng,
 460         &omap2xxx_l4_core__sham,
 461         &omap2xxx_l4_core__aes,
 462         &omap2420_l4_core__hdq1w,
 463         &omap2420_l4_wkup__counter_32k,
 464         &omap2420_l3__gpmc,
 465         NULL,
 466 };
 467
 468 int __init omap2420_hwmod_init(void)
 469 {
 470         omap_hwmod_init();
 471         return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
 472 }