arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/platform_data/gpio-omap.h>
  13 #include <linux/omap-dma.h>
  14 #include <plat/dmtimer.h>
  15 #include <linux/platform_data/spi-omap2-mcspi.h>
  16
  17 #include "omap_hwmod.h"
  18 #include "omap_hwmod_common_data.h"
  19 #include "cm-regbits-24xx.h"
  20 #include "prm-regbits-24xx.h"
  21 #include "wd_timer.h"
  22
  23 /*
  24  * 'dispc' class
  25  * display controller
  26  */
  27
  28 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  29         .rev_offs       = 0x0000,
  30         .sysc_offs      = 0x0010,
  31         .syss_offs      = 0x0014,
  32         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  33                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  34         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  35                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  36         .sysc_fields    = &omap_hwmod_sysc_type1,
  37 };
  38
  39 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  40         .name   = "dispc",
  41         .sysc   = &omap2_dispc_sysc,
  42 };
  43
  44 /* OMAP2xxx Timer Common */
  45 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  46         .rev_offs       = 0x0000,
  47         .sysc_offs      = 0x0010,
  48         .syss_offs      = 0x0014,
  49         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  50                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  51                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  52         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  53         .sysc_fields    = &omap_hwmod_sysc_type1,
  54 };
  55
  56 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  57         .name   = "timer",
  58         .sysc   = &omap2xxx_timer_sysc,
  59 };
  60
  61 /*
  62  * 'wd_timer' class
  63  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  64  * overflow condition
  65  */
  66
  67 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  68         .rev_offs       = 0x0000,
  69         .sysc_offs      = 0x0010,
  70         .syss_offs      = 0x0014,
  71         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  72                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  73         .sysc_fields    = &omap_hwmod_sysc_type1,
  74 };
  75
  76 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  77         .name           = "wd_timer",
  78         .sysc           = &omap2xxx_wd_timer_sysc,
  79         .pre_shutdown   = &omap2_wd_timer_disable,
  80         .reset          = &omap2_wd_timer_reset,
  81 };
  82
  83 /*
  84  * 'gpio' class
  85  * general purpose io module
  86  */
  87 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
  88         .rev_offs       = 0x0000,
  89         .sysc_offs      = 0x0010,
  90         .syss_offs      = 0x0014,
  91         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  92                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  93                            SYSS_HAS_RESET_STATUS),
  94         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  95         .sysc_fields    = &omap_hwmod_sysc_type1,
  96 };
  97
  98 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
  99         .name = "gpio",
 100         .sysc = &omap2xxx_gpio_sysc,
 101         .rev = 0,
 102 };
 103
 104 /* system dma */
 105 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
 106         .rev_offs       = 0x0000,
 107         .sysc_offs      = 0x002c,
 108         .syss_offs      = 0x0028,
 109         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 110                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 111                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 112         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 113         .sysc_fields    = &omap_hwmod_sysc_type1,
 114 };
 115
 116 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
 117         .name   = "dma",
 118         .sysc   = &omap2xxx_dma_sysc,
 119 };
 120
 121 /*
 122  * 'mailbox' class
 123  * mailbox module allowing communication between the on-chip processors
 124  * using a queued mailbox-interrupt mechanism.
 125  */
 126
 127 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 128         .rev_offs       = 0x000,
 129         .sysc_offs      = 0x010,
 130         .syss_offs      = 0x014,
 131         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 132                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 133         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 134         .sysc_fields    = &omap_hwmod_sysc_type1,
 135 };
 136
 137 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 138         .name   = "mailbox",
 139         .sysc   = &omap2xxx_mailbox_sysc,
 140 };
 141
 142 /*
 143  * 'mcspi' class
 144  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 145  * bus
 146  */
 147
 148 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 149         .rev_offs       = 0x0000,
 150         .sysc_offs      = 0x0010,
 151         .syss_offs      = 0x0014,
 152         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 153                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 154                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 155         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 156         .sysc_fields    = &omap_hwmod_sysc_type1,
 157 };
 158
 159 struct omap_hwmod_class omap2xxx_mcspi_class = {
 160         .name   = "mcspi",
 161         .sysc   = &omap2xxx_mcspi_sysc,
 162         .rev    = OMAP2_MCSPI_REV,
 163 };
 164
 165 /*
 166  * 'gpmc' class
 167  * general purpose memory controller
 168  */
 169
 170 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
 171         .rev_offs       = 0x0000,
 172         .sysc_offs      = 0x0010,
 173         .syss_offs      = 0x0014,
 174         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 175                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 176         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 177         .sysc_fields    = &omap_hwmod_sysc_type1,
 178 };
 179
 180 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
 181         .name   = "gpmc",
 182         .sysc   = &omap2xxx_gpmc_sysc,
 183 };
 184
 185 /*
 186  * IP blocks
 187  */
 188
 189 /* L3 */
 190 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 191         .name           = "l3_main",
 192         .class          = &l3_hwmod_class,
 193         .flags          = HWMOD_NO_IDLEST,
 194 };
 195
 196 /* L4 CORE */
 197 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 198         .name           = "l4_core",
 199         .class          = &l4_hwmod_class,
 200         .flags          = HWMOD_NO_IDLEST,
 201 };
 202
 203 /* L4 WKUP */
 204 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 205         .name           = "l4_wkup",
 206         .class          = &l4_hwmod_class,
 207         .flags          = HWMOD_NO_IDLEST,
 208 };
 209
 210 /* MPU */
 211 struct omap_hwmod omap2xxx_mpu_hwmod = {
 212         .name           = "mpu",
 213         .class          = &mpu_hwmod_class,
 214         .main_clk       = "mpu_ck",
 215 };
 216
 217 /* IVA2 */
 218 struct omap_hwmod omap2xxx_iva_hwmod = {
 219         .name           = "iva",
 220         .class          = &iva_hwmod_class,
 221 };
 222
 223 /* always-on timers dev attribute */
 224 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 225         .timer_capability       = OMAP_TIMER_ALWON,
 226 };
 227
 228 /* pwm timers dev attribute */
 229 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 230         .timer_capability       = OMAP_TIMER_HAS_PWM,
 231 };
 232
 233 /* timers with DSP interrupt dev attribute */
 234 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 235         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 236 };
 237
 238 /* timer1 */
 239
 240 struct omap_hwmod omap2xxx_timer1_hwmod = {
 241         .name           = "timer1",
 242         .main_clk       = "gpt1_fck",
 243         .prcm           = {
 244                 .omap2 = {
 245                         .module_offs = WKUP_MOD,
 246                         .idlest_reg_id = 1,
 247                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 248                 },
 249         },
 250         .dev_attr       = &capability_alwon_dev_attr,
 251         .class          = &omap2xxx_timer_hwmod_class,
 252         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 253 };
 254
 255 /* timer2 */
 256
 257 struct omap_hwmod omap2xxx_timer2_hwmod = {
 258         .name           = "timer2",
 259         .main_clk       = "gpt2_fck",
 260         .prcm           = {
 261                 .omap2 = {
 262                         .module_offs = CORE_MOD,
 263                         .idlest_reg_id = 1,
 264                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 265                 },
 266         },
 267         .class          = &omap2xxx_timer_hwmod_class,
 268         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 269 };
 270
 271 /* timer3 */
 272
 273 struct omap_hwmod omap2xxx_timer3_hwmod = {
 274         .name           = "timer3",
 275         .main_clk       = "gpt3_fck",
 276         .prcm           = {
 277                 .omap2 = {
 278                         .module_offs = CORE_MOD,
 279                         .idlest_reg_id = 1,
 280                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 281                 },
 282         },
 283         .class          = &omap2xxx_timer_hwmod_class,
 284         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 285 };
 286
 287 /* timer4 */
 288
 289 struct omap_hwmod omap2xxx_timer4_hwmod = {
 290         .name           = "timer4",
 291         .main_clk       = "gpt4_fck",
 292         .prcm           = {
 293                 .omap2 = {
 294                         .module_offs = CORE_MOD,
 295                         .idlest_reg_id = 1,
 296                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 297                 },
 298         },
 299         .class          = &omap2xxx_timer_hwmod_class,
 300         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 301 };
 302
 303 /* timer5 */
 304
 305 struct omap_hwmod omap2xxx_timer5_hwmod = {
 306         .name           = "timer5",
 307         .main_clk       = "gpt5_fck",
 308         .prcm           = {
 309                 .omap2 = {
 310                         .module_offs = CORE_MOD,
 311                         .idlest_reg_id = 1,
 312                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 313                 },
 314         },
 315         .dev_attr       = &capability_dsp_dev_attr,
 316         .class          = &omap2xxx_timer_hwmod_class,
 317         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 318 };
 319
 320 /* timer6 */
 321
 322 struct omap_hwmod omap2xxx_timer6_hwmod = {
 323         .name           = "timer6",
 324         .main_clk       = "gpt6_fck",
 325         .prcm           = {
 326                 .omap2 = {
 327                         .module_offs = CORE_MOD,
 328                         .idlest_reg_id = 1,
 329                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 330                 },
 331         },
 332         .dev_attr       = &capability_dsp_dev_attr,
 333         .class          = &omap2xxx_timer_hwmod_class,
 334         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 335 };
 336
 337 /* timer7 */
 338
 339 struct omap_hwmod omap2xxx_timer7_hwmod = {
 340         .name           = "timer7",
 341         .main_clk       = "gpt7_fck",
 342         .prcm           = {
 343                 .omap2 = {
 344                         .module_offs = CORE_MOD,
 345                         .idlest_reg_id = 1,
 346                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 347                 },
 348         },
 349         .dev_attr       = &capability_dsp_dev_attr,
 350         .class          = &omap2xxx_timer_hwmod_class,
 351         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 352 };
 353
 354 /* timer8 */
 355
 356 struct omap_hwmod omap2xxx_timer8_hwmod = {
 357         .name           = "timer8",
 358         .main_clk       = "gpt8_fck",
 359         .prcm           = {
 360                 .omap2 = {
 361                         .module_offs = CORE_MOD,
 362                         .idlest_reg_id = 1,
 363                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 364                 },
 365         },
 366         .dev_attr       = &capability_dsp_dev_attr,
 367         .class          = &omap2xxx_timer_hwmod_class,
 368         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 369 };
 370
 371 /* timer9 */
 372
 373 struct omap_hwmod omap2xxx_timer9_hwmod = {
 374         .name           = "timer9",
 375         .main_clk       = "gpt9_fck",
 376         .prcm           = {
 377                 .omap2 = {
 378                         .module_offs = CORE_MOD,
 379                         .idlest_reg_id = 1,
 380                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 381                 },
 382         },
 383         .dev_attr       = &capability_pwm_dev_attr,
 384         .class          = &omap2xxx_timer_hwmod_class,
 385         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 386 };
 387
 388 /* timer10 */
 389
 390 struct omap_hwmod omap2xxx_timer10_hwmod = {
 391         .name           = "timer10",
 392         .main_clk       = "gpt10_fck",
 393         .prcm           = {
 394                 .omap2 = {
 395                         .module_offs = CORE_MOD,
 396                         .idlest_reg_id = 1,
 397                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 398                 },
 399         },
 400         .dev_attr       = &capability_pwm_dev_attr,
 401         .class          = &omap2xxx_timer_hwmod_class,
 402         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 403 };
 404
 405 /* timer11 */
 406
 407 struct omap_hwmod omap2xxx_timer11_hwmod = {
 408         .name           = "timer11",
 409         .main_clk       = "gpt11_fck",
 410         .prcm           = {
 411                 .omap2 = {
 412                         .module_offs = CORE_MOD,
 413                         .idlest_reg_id = 1,
 414                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 415                 },
 416         },
 417         .dev_attr       = &capability_pwm_dev_attr,
 418         .class          = &omap2xxx_timer_hwmod_class,
 419         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 420 };
 421
 422 /* timer12 */
 423
 424 struct omap_hwmod omap2xxx_timer12_hwmod = {
 425         .name           = "timer12",
 426         .main_clk       = "gpt12_fck",
 427         .prcm           = {
 428                 .omap2 = {
 429                         .module_offs = CORE_MOD,
 430                         .idlest_reg_id = 1,
 431                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 432                 },
 433         },
 434         .dev_attr       = &capability_pwm_dev_attr,
 435         .class          = &omap2xxx_timer_hwmod_class,
 436         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 437 };
 438
 439 /* wd_timer2 */
 440 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 441         .name           = "wd_timer2",
 442         .class          = &omap2xxx_wd_timer_hwmod_class,
 443         .main_clk       = "mpu_wdt_fck",
 444         .prcm           = {
 445                 .omap2 = {
 446                         .module_offs = WKUP_MOD,
 447                         .idlest_reg_id = 1,
 448                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 449                 },
 450         },
 451 };
 452
 453 /* UART1 */
 454
 455 struct omap_hwmod omap2xxx_uart1_hwmod = {
 456         .name           = "uart1",
 457         .main_clk       = "uart1_fck",
 458         .flags          = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 459         .prcm           = {
 460                 .omap2 = {
 461                         .module_offs = CORE_MOD,
 462                         .idlest_reg_id = 1,
 463                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 464                 },
 465         },
 466         .class          = &omap2_uart_class,
 467 };
 468
 469 /* UART2 */
 470
 471 struct omap_hwmod omap2xxx_uart2_hwmod = {
 472         .name           = "uart2",
 473         .main_clk       = "uart2_fck",
 474         .flags          = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 475         .prcm           = {
 476                 .omap2 = {
 477                         .module_offs = CORE_MOD,
 478                         .idlest_reg_id = 1,
 479                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 480                 },
 481         },
 482         .class          = &omap2_uart_class,
 483 };
 484
 485 /* UART3 */
 486
 487 struct omap_hwmod omap2xxx_uart3_hwmod = {
 488         .name           = "uart3",
 489         .main_clk       = "uart3_fck",
 490         .flags          = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 491         .prcm           = {
 492                 .omap2 = {
 493                         .module_offs = CORE_MOD,
 494                         .idlest_reg_id = 2,
 495                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 496                 },
 497         },
 498         .class          = &omap2_uart_class,
 499 };
 500
 501 /* dss */
 502
 503 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 504         /*
 505          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 506          * driver does not use these clocks.
 507          */
 508         { .role = "tv_clk", .clk = "dss_54m_fck" },
 509         { .role = "sys_clk", .clk = "dss2_fck" },
 510 };
 511
 512 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 513         .name           = "dss_core",
 514         .class          = &omap2_dss_hwmod_class,
 515         .main_clk       = "dss1_fck", /* instead of dss_fck */
 516         .prcm           = {
 517                 .omap2 = {
 518                         .module_offs = CORE_MOD,
 519                         .idlest_reg_id = 1,
 520                 },
 521         },
 522         .opt_clks       = dss_opt_clks,
 523         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 524         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 525 };
 526
 527 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 528         .name           = "dss_dispc",
 529         .class          = &omap2_dispc_hwmod_class,
 530         .main_clk       = "dss1_fck",
 531         .prcm           = {
 532                 .omap2 = {
 533                         .module_offs = CORE_MOD,
 534                         .idlest_reg_id = 1,
 535                 },
 536         },
 537         .flags          = HWMOD_NO_IDLEST,
 538         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 539 };
 540
 541 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 542         { .role = "ick", .clk = "dss_ick" },
 543 };
 544
 545 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 546         .name           = "dss_rfbi",
 547         .class          = &omap2_rfbi_hwmod_class,
 548         .main_clk       = "dss1_fck",
 549         .prcm           = {
 550                 .omap2 = {
 551                         .module_offs = CORE_MOD,
 552                 },
 553         },
 554         .opt_clks       = dss_rfbi_opt_clks,
 555         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 556         .flags          = HWMOD_NO_IDLEST,
 557 };
 558
 559 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 560         .name           = "dss_venc",
 561         .class          = &omap2_venc_hwmod_class,
 562         .main_clk       = "dss_54m_fck",
 563         .prcm           = {
 564                 .omap2 = {
 565                         .module_offs = CORE_MOD,
 566                 },
 567         },
 568         .flags          = HWMOD_NO_IDLEST,
 569 };
 570
 571 /* gpio dev_attr */
 572 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
 573         .bank_width = 32,
 574         .dbck_flag = false,
 575 };
 576
 577 /* gpio1 */
 578 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 579         .name           = "gpio1",
 580         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 581         .main_clk       = "gpios_fck",
 582         .prcm           = {
 583                 .omap2 = {
 584                         .module_offs = WKUP_MOD,
 585                         .idlest_reg_id = 1,
 586                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 587                 },
 588         },
 589         .class          = &omap2xxx_gpio_hwmod_class,
 590         .dev_attr       = &omap2xxx_gpio_dev_attr,
 591 };
 592
 593 /* gpio2 */
 594 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 595         .name           = "gpio2",
 596         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 597         .main_clk       = "gpios_fck",
 598         .prcm           = {
 599                 .omap2 = {
 600                         .module_offs = WKUP_MOD,
 601                         .idlest_reg_id = 1,
 602                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 603                 },
 604         },
 605         .class          = &omap2xxx_gpio_hwmod_class,
 606         .dev_attr       = &omap2xxx_gpio_dev_attr,
 607 };
 608
 609 /* gpio3 */
 610 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 611         .name           = "gpio3",
 612         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 613         .main_clk       = "gpios_fck",
 614         .prcm           = {
 615                 .omap2 = {
 616                         .module_offs = WKUP_MOD,
 617                         .idlest_reg_id = 1,
 618                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 619                 },
 620         },
 621         .class          = &omap2xxx_gpio_hwmod_class,
 622         .dev_attr       = &omap2xxx_gpio_dev_attr,
 623 };
 624
 625 /* gpio4 */
 626 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 627         .name           = "gpio4",
 628         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 629         .main_clk       = "gpios_fck",
 630         .prcm           = {
 631                 .omap2 = {
 632                         .module_offs = WKUP_MOD,
 633                         .idlest_reg_id = 1,
 634                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 635                 },
 636         },
 637         .class          = &omap2xxx_gpio_hwmod_class,
 638         .dev_attr       = &omap2xxx_gpio_dev_attr,
 639 };
 640
 641 /* mcspi1 */
 642 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 643         .num_chipselect = 4,
 644 };
 645
 646 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 647         .name           = "mcspi1",
 648         .main_clk       = "mcspi1_fck",
 649         .prcm           = {
 650                 .omap2 = {
 651                         .module_offs = CORE_MOD,
 652                         .idlest_reg_id = 1,
 653                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 654                 },
 655         },
 656         .class          = &omap2xxx_mcspi_class,
 657         .dev_attr       = &omap_mcspi1_dev_attr,
 658 };
 659
 660 /* mcspi2 */
 661 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 662         .num_chipselect = 2,
 663 };
 664
 665 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 666         .name           = "mcspi2",
 667         .main_clk       = "mcspi2_fck",
 668         .prcm           = {
 669                 .omap2 = {
 670                         .module_offs = CORE_MOD,
 671                         .idlest_reg_id = 1,
 672                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 673                 },
 674         },
 675         .class          = &omap2xxx_mcspi_class,
 676         .dev_attr       = &omap_mcspi2_dev_attr,
 677 };
 678
 679 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 680         .name   = "counter",
 681 };
 682
 683 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 684         .name           = "counter_32k",
 685         .main_clk       = "func_32k_ck",
 686         .prcm           = {
 687                 .omap2  = {
 688                         .module_offs = WKUP_MOD,
 689                         .idlest_reg_id = 1,
 690                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 691                 },
 692         },
 693         .class          = &omap2xxx_counter_hwmod_class,
 694 };
 695
 696 /* gpmc */
 697 struct omap_hwmod omap2xxx_gpmc_hwmod = {
 698         .name           = "gpmc",
 699         .class          = &omap2xxx_gpmc_hwmod_class,
 700         .main_clk       = "gpmc_fck",
 701         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 702         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 703         .prcm           = {
 704                 .omap2  = {
 705                         .module_offs = CORE_MOD,
 706                 },
 707         },
 708 };
 709
 710 /* RNG */
 711
 712 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
 713         .rev_offs       = 0x3c,
 714         .sysc_offs      = 0x40,
 715         .syss_offs      = 0x44,
 716         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 717                            SYSS_HAS_RESET_STATUS),
 718         .sysc_fields    = &omap_hwmod_sysc_type1,
 719 };
 720
 721 static struct omap_hwmod_class omap2_rng_hwmod_class = {
 722         .name           = "rng",
 723         .sysc           = &omap2_rng_sysc,
 724 };
 725
 726 struct omap_hwmod omap2xxx_rng_hwmod = {
 727         .name           = "rng",
 728         .main_clk       = "l4_ck",
 729         .prcm           = {
 730                 .omap2 = {
 731                         .module_offs = CORE_MOD,
 732                         .idlest_reg_id = 4,
 733                         .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
 734                 },
 735         },
 736         /*
 737          * XXX The first read from the SYSSTATUS register of the RNG
 738          * after the SYSCONFIG SOFTRESET bit is set triggers an
 739          * imprecise external abort.  It's unclear why this happens.
 740          * Until this is analyzed, skip the IP block reset.
 741          */
 742         .flags          = HWMOD_INIT_NO_RESET,
 743         .class          = &omap2_rng_hwmod_class,
 744 };
 745
 746 /* SHAM */
 747
 748 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
 749         .rev_offs       = 0x5c,
 750         .sysc_offs      = 0x60,
 751         .syss_offs      = 0x64,
 752         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 753                            SYSS_HAS_RESET_STATUS),
 754         .sysc_fields    = &omap_hwmod_sysc_type1,
 755 };
 756
 757 static struct omap_hwmod_class omap2xxx_sham_class = {
 758         .name   = "sham",
 759         .sysc   = &omap2_sham_sysc,
 760 };
 761
 762 struct omap_hwmod omap2xxx_sham_hwmod = {
 763         .name           = "sham",
 764         .main_clk       = "l4_ck",
 765         .prcm           = {
 766                 .omap2 = {
 767                         .module_offs = CORE_MOD,
 768                         .idlest_reg_id = 4,
 769                         .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
 770                 },
 771         },
 772         .class          = &omap2xxx_sham_class,
 773 };
 774
 775 /* AES */
 776
 777 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
 778         .rev_offs       = 0x44,
 779         .sysc_offs      = 0x48,
 780         .syss_offs      = 0x4c,
 781         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 782                            SYSS_HAS_RESET_STATUS),
 783         .sysc_fields    = &omap_hwmod_sysc_type1,
 784 };
 785
 786 static struct omap_hwmod_class omap2xxx_aes_class = {
 787         .name   = "aes",
 788         .sysc   = &omap2_aes_sysc,
 789 };
 790
 791 struct omap_hwmod omap2xxx_aes_hwmod = {
 792         .name           = "aes",
 793         .main_clk       = "l4_ck",
 794         .prcm           = {
 795                 .omap2 = {
 796                         .module_offs = CORE_MOD,
 797                         .idlest_reg_id = 4,
 798                         .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
 799                 },
 800         },
 801         .class          = &omap2xxx_aes_class,
 802 };