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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
bloba1901c22a0f07231293a7caf1f905ef973dc9a75
1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 * Note that this file is currently not in sync with autogeneration scripts.
16 * The above note to be removed, once it is synced up.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23 #include <linux/io.h>
24 #include <linux/platform_data/gpio-omap.h>
25 #include <linux/platform_data/hsmmc-omap.h>
26 #include <linux/power/smartreflex.h>
27 #include <linux/i2c-omap.h>
28
29 #include <linux/omap-dma.h>
30
31 #include <linux/platform_data/spi-omap2-mcspi.h>
32 #include <linux/platform_data/asoc-ti-mcbsp.h>
33 #include <plat/dmtimer.h>
34
35 #include "omap_hwmod.h"
36 #include "omap_hwmod_common_data.h"
37 #include "cm1_44xx.h"
38 #include "cm2_44xx.h"
39 #include "prm44xx.h"
40 #include "prm-regbits-44xx.h"
41 #include "i2c.h"
42 #include "wd_timer.h"
43
44 /* Base offset for all OMAP4 interrupts external to MPUSS */
45 #define OMAP44XX_IRQ_GIC_START 32
46
47 /* Base offset for all OMAP4 dma requests */
48 #define OMAP44XX_DMA_REQ_START 1
49
50 /*
51 * IP blocks
52 */
53
54 /*
55 * 'dmm' class
56 * instance(s): dmm
57 */
58 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
59 .name = "dmm",
60 };
61
62 /* dmm */
63 static struct omap_hwmod omap44xx_dmm_hwmod = {
64 .name = "dmm",
65 .class = &omap44xx_dmm_hwmod_class,
66 .clkdm_name = "l3_emif_clkdm",
67 .prcm = {
68 .omap4 = {
69 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
70 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
71 },
72 },
73 };
74
75 /*
76 * 'l3' class
77 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
78 */
79 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
80 .name = "l3",
81 };
82
83 /* l3_instr */
84 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
85 .name = "l3_instr",
86 .class = &omap44xx_l3_hwmod_class,
87 .clkdm_name = "l3_instr_clkdm",
88 .prcm = {
89 .omap4 = {
90 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
91 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
92 .modulemode = MODULEMODE_HWCTRL,
93 },
94 },
95 };
96
97 /* l3_main_1 */
98 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
99 .name = "l3_main_1",
100 .class = &omap44xx_l3_hwmod_class,
101 .clkdm_name = "l3_1_clkdm",
102 .prcm = {
103 .omap4 = {
104 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
105 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
106 },
107 },
108 };
109
110 /* l3_main_2 */
111 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
112 .name = "l3_main_2",
113 .class = &omap44xx_l3_hwmod_class,
114 .clkdm_name = "l3_2_clkdm",
115 .prcm = {
116 .omap4 = {
117 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
118 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
119 },
120 },
121 };
122
123 /* l3_main_3 */
124 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
125 .name = "l3_main_3",
126 .class = &omap44xx_l3_hwmod_class,
127 .clkdm_name = "l3_instr_clkdm",
128 .prcm = {
129 .omap4 = {
130 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
131 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
132 .modulemode = MODULEMODE_HWCTRL,
133 },
134 },
135 };
136
137 /*
138 * 'l4' class
139 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
140 */
141 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
142 .name = "l4",
143 };
144
145 /* l4_abe */
146 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
147 .name = "l4_abe",
148 .class = &omap44xx_l4_hwmod_class,
149 .clkdm_name = "abe_clkdm",
150 .prcm = {
151 .omap4 = {
152 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
153 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
154 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
155 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
156 },
157 },
158 };
159
160 /* l4_cfg */
161 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
162 .name = "l4_cfg",
163 .class = &omap44xx_l4_hwmod_class,
164 .clkdm_name = "l4_cfg_clkdm",
165 .prcm = {
166 .omap4 = {
167 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
168 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
169 },
170 },
171 };
172
173 /* l4_per */
174 static struct omap_hwmod omap44xx_l4_per_hwmod = {
175 .name = "l4_per",
176 .class = &omap44xx_l4_hwmod_class,
177 .clkdm_name = "l4_per_clkdm",
178 .prcm = {
179 .omap4 = {
180 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
181 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
182 },
183 },
184 };
185
186 /* l4_wkup */
187 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
188 .name = "l4_wkup",
189 .class = &omap44xx_l4_hwmod_class,
190 .clkdm_name = "l4_wkup_clkdm",
191 .prcm = {
192 .omap4 = {
193 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
194 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
195 },
196 },
197 };
198
199 /*
200 * 'mpu_bus' class
201 * instance(s): mpu_private
202 */
203 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
204 .name = "mpu_bus",
205 };
206
207 /* mpu_private */
208 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
209 .name = "mpu_private",
210 .class = &omap44xx_mpu_bus_hwmod_class,
211 .clkdm_name = "mpuss_clkdm",
212 .prcm = {
213 .omap4 = {
214 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
215 },
216 },
217 };
218
219 /*
220 * 'ocp_wp_noc' class
221 * instance(s): ocp_wp_noc
222 */
223 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
224 .name = "ocp_wp_noc",
225 };
226
227 /* ocp_wp_noc */
228 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
229 .name = "ocp_wp_noc",
230 .class = &omap44xx_ocp_wp_noc_hwmod_class,
231 .clkdm_name = "l3_instr_clkdm",
232 .prcm = {
233 .omap4 = {
234 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
235 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
236 .modulemode = MODULEMODE_HWCTRL,
237 },
238 },
239 };
240
241 /*
242 * Modules omap_hwmod structures
243 *
244 * The following IPs are excluded for the moment because:
245 * - They do not need an explicit SW control using omap_hwmod API.
246 * - They still need to be validated with the driver
247 * properly adapted to omap_hwmod / omap_device
248 *
249 * usim
250 */
251
252 /*
253 * 'aess' class
254 * audio engine sub system
255 */
256
257 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
258 .rev_offs = 0x0000,
259 .sysc_offs = 0x0010,
260 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
261 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
262 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
263 MSTANDBY_SMART_WKUP),
264 .sysc_fields = &omap_hwmod_sysc_type2,
265 };
266
267 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
268 .name = "aess",
269 .sysc = &omap44xx_aess_sysc,
270 .enable_preprogram = omap_hwmod_aess_preprogram,
271 };
272
273 /* aess */
274 static struct omap_hwmod omap44xx_aess_hwmod = {
275 .name = "aess",
276 .class = &omap44xx_aess_hwmod_class,
277 .clkdm_name = "abe_clkdm",
278 .main_clk = "aess_fclk",
279 .prcm = {
280 .omap4 = {
281 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
282 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
283 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
284 .modulemode = MODULEMODE_SWCTRL,
285 },
286 },
287 };
288
289 /*
290 * 'c2c' class
291 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
292 * soc
293 */
294
295 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
296 .name = "c2c",
297 };
298
299 /* c2c */
300 static struct omap_hwmod omap44xx_c2c_hwmod = {
301 .name = "c2c",
302 .class = &omap44xx_c2c_hwmod_class,
303 .clkdm_name = "d2d_clkdm",
304 .prcm = {
305 .omap4 = {
306 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
307 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
308 },
309 },
310 };
311
312 /*
313 * 'counter' class
314 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
315 */
316
317 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
318 .rev_offs = 0x0000,
319 .sysc_offs = 0x0004,
320 .sysc_flags = SYSC_HAS_SIDLEMODE,
321 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
322 .sysc_fields = &omap_hwmod_sysc_type1,
323 };
324
325 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
326 .name = "counter",
327 .sysc = &omap44xx_counter_sysc,
328 };
329
330 /* counter_32k */
331 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
332 .name = "counter_32k",
333 .class = &omap44xx_counter_hwmod_class,
334 .clkdm_name = "l4_wkup_clkdm",
335 .flags = HWMOD_SWSUP_SIDLE,
336 .main_clk = "sys_32k_ck",
337 .prcm = {
338 .omap4 = {
339 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
340 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
341 },
342 },
343 };
344
345 /*
346 * 'ctrl_module' class
347 * attila core control module + core pad control module + wkup pad control
348 * module + attila wkup control module
349 */
350
351 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
352 .rev_offs = 0x0000,
353 .sysc_offs = 0x0010,
354 .sysc_flags = SYSC_HAS_SIDLEMODE,
355 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
356 SIDLE_SMART_WKUP),
357 .sysc_fields = &omap_hwmod_sysc_type2,
358 };
359
360 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
361 .name = "ctrl_module",
362 .sysc = &omap44xx_ctrl_module_sysc,
363 };
364
365 /* ctrl_module_core */
366 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
367 .name = "ctrl_module_core",
368 .class = &omap44xx_ctrl_module_hwmod_class,
369 .clkdm_name = "l4_cfg_clkdm",
370 .prcm = {
371 .omap4 = {
372 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
373 },
374 },
375 };
376
377 /* ctrl_module_pad_core */
378 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
379 .name = "ctrl_module_pad_core",
380 .class = &omap44xx_ctrl_module_hwmod_class,
381 .clkdm_name = "l4_cfg_clkdm",
382 .prcm = {
383 .omap4 = {
384 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
385 },
386 },
387 };
388
389 /* ctrl_module_wkup */
390 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
391 .name = "ctrl_module_wkup",
392 .class = &omap44xx_ctrl_module_hwmod_class,
393 .clkdm_name = "l4_wkup_clkdm",
394 .prcm = {
395 .omap4 = {
396 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
397 },
398 },
399 };
400
401 /* ctrl_module_pad_wkup */
402 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
403 .name = "ctrl_module_pad_wkup",
404 .class = &omap44xx_ctrl_module_hwmod_class,
405 .clkdm_name = "l4_wkup_clkdm",
406 .prcm = {
407 .omap4 = {
408 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
409 },
410 },
411 };
412
413 /*
414 * 'debugss' class
415 * debug and emulation sub system
416 */
417
418 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
419 .name = "debugss",
420 };
421
422 /* debugss */
423 static struct omap_hwmod omap44xx_debugss_hwmod = {
424 .name = "debugss",
425 .class = &omap44xx_debugss_hwmod_class,
426 .clkdm_name = "emu_sys_clkdm",
427 .main_clk = "trace_clk_div_ck",
428 .prcm = {
429 .omap4 = {
430 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
431 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
432 },
433 },
434 };
435
436 /*
437 * 'dma' class
438 * dma controller for data exchange between memory to memory (i.e. internal or
439 * external memory) and gp peripherals to memory or memory to gp peripherals
440 */
441
442 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
443 .rev_offs = 0x0000,
444 .sysc_offs = 0x002c,
445 .syss_offs = 0x0028,
446 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
447 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
448 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
449 SYSS_HAS_RESET_STATUS),
450 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
451 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
452 .sysc_fields = &omap_hwmod_sysc_type1,
453 };
454
455 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
456 .name = "dma",
457 .sysc = &omap44xx_dma_sysc,
458 };
459
460 /* dma dev_attr */
461 static struct omap_dma_dev_attr dma_dev_attr = {
462 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
463 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
464 .lch_count = 32,
465 };
466
467 /* dma_system */
468 static struct omap_hwmod omap44xx_dma_system_hwmod = {
469 .name = "dma_system",
470 .class = &omap44xx_dma_hwmod_class,
471 .clkdm_name = "l3_dma_clkdm",
472 .main_clk = "l3_div_ck",
473 .prcm = {
474 .omap4 = {
475 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
476 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
477 },
478 },
479 .dev_attr = &dma_dev_attr,
480 };
481
482 /*
483 * 'dmic' class
484 * digital microphone controller
485 */
486
487 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
488 .rev_offs = 0x0000,
489 .sysc_offs = 0x0010,
490 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
491 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
492 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
493 SIDLE_SMART_WKUP),
494 .sysc_fields = &omap_hwmod_sysc_type2,
495 };
496
497 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
498 .name = "dmic",
499 .sysc = &omap44xx_dmic_sysc,
500 };
501
502 /* dmic */
503 static struct omap_hwmod omap44xx_dmic_hwmod = {
504 .name = "dmic",
505 .class = &omap44xx_dmic_hwmod_class,
506 .clkdm_name = "abe_clkdm",
507 .main_clk = "func_dmic_abe_gfclk",
508 .prcm = {
509 .omap4 = {
510 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
511 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
512 .modulemode = MODULEMODE_SWCTRL,
513 },
514 },
515 };
516
517 /*
518 * 'dsp' class
519 * dsp sub-system
520 */
521
522 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
523 .name = "dsp",
524 };
525
526 /* dsp */
527 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
528 { .name = "dsp", .rst_shift = 0 },
529 };
530
531 static struct omap_hwmod omap44xx_dsp_hwmod = {
532 .name = "dsp",
533 .class = &omap44xx_dsp_hwmod_class,
534 .clkdm_name = "tesla_clkdm",
535 .rst_lines = omap44xx_dsp_resets,
536 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
537 .main_clk = "dpll_iva_m4x2_ck",
538 .prcm = {
539 .omap4 = {
540 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
541 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
542 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
543 .modulemode = MODULEMODE_HWCTRL,
544 },
545 },
546 };
547
548 /*
549 * 'dss' class
550 * display sub-system
551 */
552
553 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
554 .rev_offs = 0x0000,
555 .syss_offs = 0x0014,
556 .sysc_flags = SYSS_HAS_RESET_STATUS,
557 };
558
559 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
560 .name = "dss",
561 .sysc = &omap44xx_dss_sysc,
562 .reset = omap_dss_reset,
563 };
564
565 /* dss */
566 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
567 { .role = "sys_clk", .clk = "dss_sys_clk" },
568 { .role = "tv_clk", .clk = "dss_tv_clk" },
569 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
570 };
571
572 static struct omap_hwmod omap44xx_dss_hwmod = {
573 .name = "dss_core",
574 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
575 .class = &omap44xx_dss_hwmod_class,
576 .clkdm_name = "l3_dss_clkdm",
577 .main_clk = "dss_dss_clk",
578 .prcm = {
579 .omap4 = {
580 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
581 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
582 .modulemode = MODULEMODE_SWCTRL,
583 },
584 },
585 .opt_clks = dss_opt_clks,
586 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
587 };
588
589 /*
590 * 'dispc' class
591 * display controller
592 */
593
594 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
595 .rev_offs = 0x0000,
596 .sysc_offs = 0x0010,
597 .syss_offs = 0x0014,
598 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
599 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
600 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
601 SYSS_HAS_RESET_STATUS),
602 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
603 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
604 .sysc_fields = &omap_hwmod_sysc_type1,
605 };
606
607 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
608 .name = "dispc",
609 .sysc = &omap44xx_dispc_sysc,
610 };
611
612 /* dss_dispc */
613 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
614 .manager_count = 3,
615 .has_framedonetv_irq = 1
616 };
617
618 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
619 .name = "dss_dispc",
620 .class = &omap44xx_dispc_hwmod_class,
621 .clkdm_name = "l3_dss_clkdm",
622 .main_clk = "dss_dss_clk",
623 .prcm = {
624 .omap4 = {
625 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
626 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
627 },
628 },
629 .dev_attr = &omap44xx_dss_dispc_dev_attr,
630 .parent_hwmod = &omap44xx_dss_hwmod,
631 };
632
633 /*
634 * 'dsi' class
635 * display serial interface controller
636 */
637
638 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
639 .rev_offs = 0x0000,
640 .sysc_offs = 0x0010,
641 .syss_offs = 0x0014,
642 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
643 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
644 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
645 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
646 .sysc_fields = &omap_hwmod_sysc_type1,
647 };
648
649 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
650 .name = "dsi",
651 .sysc = &omap44xx_dsi_sysc,
652 };
653
654 /* dss_dsi1 */
655 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
656 { .role = "sys_clk", .clk = "dss_sys_clk" },
657 };
658
659 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
660 .name = "dss_dsi1",
661 .class = &omap44xx_dsi_hwmod_class,
662 .clkdm_name = "l3_dss_clkdm",
663 .main_clk = "dss_dss_clk",
664 .prcm = {
665 .omap4 = {
666 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
667 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
668 },
669 },
670 .opt_clks = dss_dsi1_opt_clks,
671 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
672 .parent_hwmod = &omap44xx_dss_hwmod,
673 };
674
675 /* dss_dsi2 */
676 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
677 { .role = "sys_clk", .clk = "dss_sys_clk" },
678 };
679
680 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
681 .name = "dss_dsi2",
682 .class = &omap44xx_dsi_hwmod_class,
683 .clkdm_name = "l3_dss_clkdm",
684 .main_clk = "dss_dss_clk",
685 .prcm = {
686 .omap4 = {
687 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
688 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
689 },
690 },
691 .opt_clks = dss_dsi2_opt_clks,
692 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
693 .parent_hwmod = &omap44xx_dss_hwmod,
694 };
695
696 /*
697 * 'hdmi' class
698 * hdmi controller
699 */
700
701 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
702 .rev_offs = 0x0000,
703 .sysc_offs = 0x0010,
704 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
705 SYSC_HAS_SOFTRESET),
706 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
707 SIDLE_SMART_WKUP),
708 .sysc_fields = &omap_hwmod_sysc_type2,
709 };
710
711 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
712 .name = "hdmi",
713 .sysc = &omap44xx_hdmi_sysc,
714 };
715
716 /* dss_hdmi */
717 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
718 { .role = "sys_clk", .clk = "dss_sys_clk" },
719 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
720 };
721
722 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
723 .name = "dss_hdmi",
724 .class = &omap44xx_hdmi_hwmod_class,
725 .clkdm_name = "l3_dss_clkdm",
726 /*
727 * HDMI audio requires to use no-idle mode. Hence,
728 * set idle mode by software.
729 */
730 .flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
731 .main_clk = "dss_48mhz_clk",
732 .prcm = {
733 .omap4 = {
734 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
735 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
736 },
737 },
738 .opt_clks = dss_hdmi_opt_clks,
739 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
740 .parent_hwmod = &omap44xx_dss_hwmod,
741 };
742
743 /*
744 * 'rfbi' class
745 * remote frame buffer interface
746 */
747
748 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
749 .rev_offs = 0x0000,
750 .sysc_offs = 0x0010,
751 .syss_offs = 0x0014,
752 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
753 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
754 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
755 .sysc_fields = &omap_hwmod_sysc_type1,
756 };
757
758 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
759 .name = "rfbi",
760 .sysc = &omap44xx_rfbi_sysc,
761 };
762
763 /* dss_rfbi */
764 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
765 { .role = "ick", .clk = "l3_div_ck" },
766 };
767
768 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
769 .name = "dss_rfbi",
770 .class = &omap44xx_rfbi_hwmod_class,
771 .clkdm_name = "l3_dss_clkdm",
772 .main_clk = "dss_dss_clk",
773 .prcm = {
774 .omap4 = {
775 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
776 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
777 },
778 },
779 .opt_clks = dss_rfbi_opt_clks,
780 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
781 .parent_hwmod = &omap44xx_dss_hwmod,
782 };
783
784 /*
785 * 'venc' class
786 * video encoder
787 */
788
789 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
790 .name = "venc",
791 };
792
793 /* dss_venc */
794 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
795 { .role = "tv_clk", .clk = "dss_tv_clk" },
796 };
797
798 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
799 .name = "dss_venc",
800 .class = &omap44xx_venc_hwmod_class,
801 .clkdm_name = "l3_dss_clkdm",
802 .main_clk = "dss_tv_clk",
803 .flags = HWMOD_OPT_CLKS_NEEDED,
804 .prcm = {
805 .omap4 = {
806 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
807 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
808 },
809 },
810 .parent_hwmod = &omap44xx_dss_hwmod,
811 .opt_clks = dss_venc_opt_clks,
812 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
813 };
814
815 /* sha0 HIB2 (the 'P' (public) device) */
816 static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
817 .rev_offs = 0x100,
818 .sysc_offs = 0x110,
819 .syss_offs = 0x114,
820 .sysc_flags = SYSS_HAS_RESET_STATUS,
821 };
822
823 static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
824 .name = "sham",
825 .sysc = &omap44xx_sha0_sysc,
826 };
827
828 struct omap_hwmod omap44xx_sha0_hwmod = {
829 .name = "sham",
830 .class = &omap44xx_sha0_hwmod_class,
831 .clkdm_name = "l4_secure_clkdm",
832 .main_clk = "l3_div_ck",
833 .prcm = {
834 .omap4 = {
835 .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
836 .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
837 .modulemode = MODULEMODE_SWCTRL,
838 },
839 },
840 };
841
842 /*
843 * 'elm' class
844 * bch error location module
845 */
846
847 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
848 .rev_offs = 0x0000,
849 .sysc_offs = 0x0010,
850 .syss_offs = 0x0014,
851 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
852 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
853 SYSS_HAS_RESET_STATUS),
854 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
855 .sysc_fields = &omap_hwmod_sysc_type1,
856 };
857
858 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
859 .name = "elm",
860 .sysc = &omap44xx_elm_sysc,
861 };
862
863 /* elm */
864 static struct omap_hwmod omap44xx_elm_hwmod = {
865 .name = "elm",
866 .class = &omap44xx_elm_hwmod_class,
867 .clkdm_name = "l4_per_clkdm",
868 .prcm = {
869 .omap4 = {
870 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
871 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
872 },
873 },
874 };
875
876 /*
877 * 'emif' class
878 * external memory interface no1
879 */
880
881 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
882 .rev_offs = 0x0000,
883 };
884
885 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
886 .name = "emif",
887 .sysc = &omap44xx_emif_sysc,
888 };
889
890 /* emif1 */
891 static struct omap_hwmod omap44xx_emif1_hwmod = {
892 .name = "emif1",
893 .class = &omap44xx_emif_hwmod_class,
894 .clkdm_name = "l3_emif_clkdm",
895 .flags = HWMOD_INIT_NO_IDLE,
896 .main_clk = "ddrphy_ck",
897 .prcm = {
898 .omap4 = {
899 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
900 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
901 .modulemode = MODULEMODE_HWCTRL,
902 },
903 },
904 };
905
906 /* emif2 */
907 static struct omap_hwmod omap44xx_emif2_hwmod = {
908 .name = "emif2",
909 .class = &omap44xx_emif_hwmod_class,
910 .clkdm_name = "l3_emif_clkdm",
911 .flags = HWMOD_INIT_NO_IDLE,
912 .main_clk = "ddrphy_ck",
913 .prcm = {
914 .omap4 = {
915 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
916 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
917 .modulemode = MODULEMODE_HWCTRL,
918 },
919 },
920 };
921
922 /*
923 Crypto modules AES0/1 belong to:
924 PD_L4_PER power domain
925 CD_L4_SEC clock domain
926 On the L3, the AES modules are mapped to
927 L3_CLK2: Peripherals and multimedia sub clock domain
928 */
929 static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
930 .rev_offs = 0x80,
931 .sysc_offs = 0x84,
932 .syss_offs = 0x88,
933 .sysc_flags = SYSS_HAS_RESET_STATUS,
934 };
935
936 static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
937 .name = "aes",
938 .sysc = &omap44xx_aes_sysc,
939 };
940
941 static struct omap_hwmod omap44xx_aes1_hwmod = {
942 .name = "aes1",
943 .class = &omap44xx_aes_hwmod_class,
944 .clkdm_name = "l4_secure_clkdm",
945 .main_clk = "l3_div_ck",
946 .prcm = {
947 .omap4 = {
948 .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
949 .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
950 .modulemode = MODULEMODE_SWCTRL,
951 },
952 },
953 };
954
955 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
956 .master = &omap44xx_l4_per_hwmod,
957 .slave = &omap44xx_aes1_hwmod,
958 .clk = "l3_div_ck",
959 .user = OCP_USER_MPU | OCP_USER_SDMA,
960 };
961
962 static struct omap_hwmod omap44xx_aes2_hwmod = {
963 .name = "aes2",
964 .class = &omap44xx_aes_hwmod_class,
965 .clkdm_name = "l4_secure_clkdm",
966 .main_clk = "l3_div_ck",
967 .prcm = {
968 .omap4 = {
969 .context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
970 .clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
971 .modulemode = MODULEMODE_SWCTRL,
972 },
973 },
974 };
975
976 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
977 .master = &omap44xx_l4_per_hwmod,
978 .slave = &omap44xx_aes2_hwmod,
979 .clk = "l3_div_ck",
980 .user = OCP_USER_MPU | OCP_USER_SDMA,
981 };
982
983 /*
984 * 'des' class for DES3DES module
985 */
986 static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
987 .rev_offs = 0x30,
988 .sysc_offs = 0x34,
989 .syss_offs = 0x38,
990 .sysc_flags = SYSS_HAS_RESET_STATUS,
991 };
992
993 static struct omap_hwmod_class omap44xx_des_hwmod_class = {
994 .name = "des",
995 .sysc = &omap44xx_des_sysc,
996 };
997
998 static struct omap_hwmod omap44xx_des_hwmod = {
999 .name = "des",
1000 .class = &omap44xx_des_hwmod_class,
1001 .clkdm_name = "l4_secure_clkdm",
1002 .main_clk = "l3_div_ck",
1003 .prcm = {
1004 .omap4 = {
1005 .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
1006 .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
1007 .modulemode = MODULEMODE_SWCTRL,
1008 },
1009 },
1010 };
1011
1012 struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
1013 .master = &omap44xx_l3_main_2_hwmod,
1014 .slave = &omap44xx_des_hwmod,
1015 .clk = "l3_div_ck",
1016 .user = OCP_USER_MPU | OCP_USER_SDMA,
1017 };
1018
1019 /*
1020 * 'fdif' class
1021 * face detection hw accelerator module
1022 */
1023
1024 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1025 .rev_offs = 0x0000,
1026 .sysc_offs = 0x0010,
1027 /*
1028 * FDIF needs 100 OCP clk cycles delay after a softreset before
1029 * accessing sysconfig again.
1030 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1031 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1032 *
1033 * TODO: Indicate errata when available.
1034 */
1035 .srst_udelay = 2,
1036 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1037 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1038 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1039 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1040 .sysc_fields = &omap_hwmod_sysc_type2,
1041 };
1042
1043 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1044 .name = "fdif",
1045 .sysc = &omap44xx_fdif_sysc,
1046 };
1047
1048 /* fdif */
1049 static struct omap_hwmod omap44xx_fdif_hwmod = {
1050 .name = "fdif",
1051 .class = &omap44xx_fdif_hwmod_class,
1052 .clkdm_name = "iss_clkdm",
1053 .main_clk = "fdif_fck",
1054 .prcm = {
1055 .omap4 = {
1056 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1057 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1058 .modulemode = MODULEMODE_SWCTRL,
1059 },
1060 },
1061 };
1062
1063 /*
1064 * 'gpio' class
1065 * general purpose io module
1066 */
1067
1068 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1069 .rev_offs = 0x0000,
1070 .sysc_offs = 0x0010,
1071 .syss_offs = 0x0114,
1072 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1073 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1074 SYSS_HAS_RESET_STATUS),
1075 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1076 SIDLE_SMART_WKUP),
1077 .sysc_fields = &omap_hwmod_sysc_type1,
1078 };
1079
1080 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1081 .name = "gpio",
1082 .sysc = &omap44xx_gpio_sysc,
1083 .rev = 2,
1084 };
1085
1086 /* gpio dev_attr */
1087 static struct omap_gpio_dev_attr gpio_dev_attr = {
1088 .bank_width = 32,
1089 .dbck_flag = true,
1090 };
1091
1092 /* gpio1 */
1093 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1094 { .role = "dbclk", .clk = "gpio1_dbclk" },
1095 };
1096
1097 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1098 .name = "gpio1",
1099 .class = &omap44xx_gpio_hwmod_class,
1100 .clkdm_name = "l4_wkup_clkdm",
1101 .main_clk = "l4_wkup_clk_mux_ck",
1102 .prcm = {
1103 .omap4 = {
1104 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1105 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1106 .modulemode = MODULEMODE_HWCTRL,
1107 },
1108 },
1109 .opt_clks = gpio1_opt_clks,
1110 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1111 .dev_attr = &gpio_dev_attr,
1112 };
1113
1114 /* gpio2 */
1115 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1116 { .role = "dbclk", .clk = "gpio2_dbclk" },
1117 };
1118
1119 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1120 .name = "gpio2",
1121 .class = &omap44xx_gpio_hwmod_class,
1122 .clkdm_name = "l4_per_clkdm",
1123 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1124 .main_clk = "l4_div_ck",
1125 .prcm = {
1126 .omap4 = {
1127 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1128 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1129 .modulemode = MODULEMODE_HWCTRL,
1130 },
1131 },
1132 .opt_clks = gpio2_opt_clks,
1133 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1134 .dev_attr = &gpio_dev_attr,
1135 };
1136
1137 /* gpio3 */
1138 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1139 { .role = "dbclk", .clk = "gpio3_dbclk" },
1140 };
1141
1142 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1143 .name = "gpio3",
1144 .class = &omap44xx_gpio_hwmod_class,
1145 .clkdm_name = "l4_per_clkdm",
1146 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1147 .main_clk = "l4_div_ck",
1148 .prcm = {
1149 .omap4 = {
1150 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1151 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1152 .modulemode = MODULEMODE_HWCTRL,
1153 },
1154 },
1155 .opt_clks = gpio3_opt_clks,
1156 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1157 .dev_attr = &gpio_dev_attr,
1158 };
1159
1160 /* gpio4 */
1161 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1162 { .role = "dbclk", .clk = "gpio4_dbclk" },
1163 };
1164
1165 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1166 .name = "gpio4",
1167 .class = &omap44xx_gpio_hwmod_class,
1168 .clkdm_name = "l4_per_clkdm",
1169 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1170 .main_clk = "l4_div_ck",
1171 .prcm = {
1172 .omap4 = {
1173 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1174 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1175 .modulemode = MODULEMODE_HWCTRL,
1176 },
1177 },
1178 .opt_clks = gpio4_opt_clks,
1179 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1180 .dev_attr = &gpio_dev_attr,
1181 };
1182
1183 /* gpio5 */
1184 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1185 { .role = "dbclk", .clk = "gpio5_dbclk" },
1186 };
1187
1188 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1189 .name = "gpio5",
1190 .class = &omap44xx_gpio_hwmod_class,
1191 .clkdm_name = "l4_per_clkdm",
1192 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1193 .main_clk = "l4_div_ck",
1194 .prcm = {
1195 .omap4 = {
1196 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1197 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1198 .modulemode = MODULEMODE_HWCTRL,
1199 },
1200 },
1201 .opt_clks = gpio5_opt_clks,
1202 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1203 .dev_attr = &gpio_dev_attr,
1204 };
1205
1206 /* gpio6 */
1207 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1208 { .role = "dbclk", .clk = "gpio6_dbclk" },
1209 };
1210
1211 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1212 .name = "gpio6",
1213 .class = &omap44xx_gpio_hwmod_class,
1214 .clkdm_name = "l4_per_clkdm",
1215 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1216 .main_clk = "l4_div_ck",
1217 .prcm = {
1218 .omap4 = {
1219 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1220 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1221 .modulemode = MODULEMODE_HWCTRL,
1222 },
1223 },
1224 .opt_clks = gpio6_opt_clks,
1225 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1226 .dev_attr = &gpio_dev_attr,
1227 };
1228
1229 /*
1230 * 'gpmc' class
1231 * general purpose memory controller
1232 */
1233
1234 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1235 .rev_offs = 0x0000,
1236 .sysc_offs = 0x0010,
1237 .syss_offs = 0x0014,
1238 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1239 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1240 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1241 .sysc_fields = &omap_hwmod_sysc_type1,
1242 };
1243
1244 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1245 .name = "gpmc",
1246 .sysc = &omap44xx_gpmc_sysc,
1247 };
1248
1249 /* gpmc */
1250 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1251 .name = "gpmc",
1252 .class = &omap44xx_gpmc_hwmod_class,
1253 .clkdm_name = "l3_2_clkdm",
1254 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1255 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1256 .prcm = {
1257 .omap4 = {
1258 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1259 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1260 .modulemode = MODULEMODE_HWCTRL,
1261 },
1262 },
1263 };
1264
1265 /*
1266 * 'gpu' class
1267 * 2d/3d graphics accelerator
1268 */
1269
1270 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1271 .rev_offs = 0x1fc00,
1272 .sysc_offs = 0x1fc10,
1273 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1274 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1275 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1276 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1277 .sysc_fields = &omap_hwmod_sysc_type2,
1278 };
1279
1280 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1281 .name = "gpu",
1282 .sysc = &omap44xx_gpu_sysc,
1283 };
1284
1285 /* gpu */
1286 static struct omap_hwmod omap44xx_gpu_hwmod = {
1287 .name = "gpu",
1288 .class = &omap44xx_gpu_hwmod_class,
1289 .clkdm_name = "l3_gfx_clkdm",
1290 .main_clk = "sgx_clk_mux",
1291 .prcm = {
1292 .omap4 = {
1293 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1294 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1295 .modulemode = MODULEMODE_SWCTRL,
1296 },
1297 },
1298 };
1299
1300 /*
1301 * 'hdq1w' class
1302 * hdq / 1-wire serial interface controller
1303 */
1304
1305 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1306 .rev_offs = 0x0000,
1307 .sysc_offs = 0x0014,
1308 .syss_offs = 0x0018,
1309 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1310 SYSS_HAS_RESET_STATUS),
1311 .sysc_fields = &omap_hwmod_sysc_type1,
1312 };
1313
1314 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1315 .name = "hdq1w",
1316 .sysc = &omap44xx_hdq1w_sysc,
1317 };
1318
1319 /* hdq1w */
1320 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1321 .name = "hdq1w",
1322 .class = &omap44xx_hdq1w_hwmod_class,
1323 .clkdm_name = "l4_per_clkdm",
1324 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1325 .main_clk = "func_12m_fclk",
1326 .prcm = {
1327 .omap4 = {
1328 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1329 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1330 .modulemode = MODULEMODE_SWCTRL,
1331 },
1332 },
1333 };
1334
1335 /*
1336 * 'hsi' class
1337 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1338 * serial if)
1339 */
1340
1341 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1342 .rev_offs = 0x0000,
1343 .sysc_offs = 0x0010,
1344 .syss_offs = 0x0014,
1345 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1346 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1347 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1348 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1349 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1350 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1351 .sysc_fields = &omap_hwmod_sysc_type1,
1352 };
1353
1354 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1355 .name = "hsi",
1356 .sysc = &omap44xx_hsi_sysc,
1357 };
1358
1359 /* hsi */
1360 static struct omap_hwmod omap44xx_hsi_hwmod = {
1361 .name = "hsi",
1362 .class = &omap44xx_hsi_hwmod_class,
1363 .clkdm_name = "l3_init_clkdm",
1364 .main_clk = "hsi_fck",
1365 .prcm = {
1366 .omap4 = {
1367 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1368 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1369 .modulemode = MODULEMODE_HWCTRL,
1370 },
1371 },
1372 };
1373
1374 /*
1375 * 'i2c' class
1376 * multimaster high-speed i2c controller
1377 */
1378
1379 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1380 .sysc_offs = 0x0010,
1381 .syss_offs = 0x0090,
1382 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1383 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1384 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1385 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1386 SIDLE_SMART_WKUP),
1387 .sysc_fields = &omap_hwmod_sysc_type1,
1388 };
1389
1390 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1391 .name = "i2c",
1392 .sysc = &omap44xx_i2c_sysc,
1393 .rev = OMAP_I2C_IP_VERSION_2,
1394 .reset = &omap_i2c_reset,
1395 };
1396
1397 static struct omap_i2c_dev_attr i2c_dev_attr = {
1398 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1399 };
1400
1401 /* i2c1 */
1402 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1403 .name = "i2c1",
1404 .class = &omap44xx_i2c_hwmod_class,
1405 .clkdm_name = "l4_per_clkdm",
1406 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1407 .main_clk = "func_96m_fclk",
1408 .prcm = {
1409 .omap4 = {
1410 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1411 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1412 .modulemode = MODULEMODE_SWCTRL,
1413 },
1414 },
1415 .dev_attr = &i2c_dev_attr,
1416 };
1417
1418 /* i2c2 */
1419 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1420 .name = "i2c2",
1421 .class = &omap44xx_i2c_hwmod_class,
1422 .clkdm_name = "l4_per_clkdm",
1423 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1424 .main_clk = "func_96m_fclk",
1425 .prcm = {
1426 .omap4 = {
1427 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1428 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1429 .modulemode = MODULEMODE_SWCTRL,
1430 },
1431 },
1432 .dev_attr = &i2c_dev_attr,
1433 };
1434
1435 /* i2c3 */
1436 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1437 .name = "i2c3",
1438 .class = &omap44xx_i2c_hwmod_class,
1439 .clkdm_name = "l4_per_clkdm",
1440 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1441 .main_clk = "func_96m_fclk",
1442 .prcm = {
1443 .omap4 = {
1444 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1445 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1446 .modulemode = MODULEMODE_SWCTRL,
1447 },
1448 },
1449 .dev_attr = &i2c_dev_attr,
1450 };
1451
1452 /* i2c4 */
1453 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1454 .name = "i2c4",
1455 .class = &omap44xx_i2c_hwmod_class,
1456 .clkdm_name = "l4_per_clkdm",
1457 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1458 .main_clk = "func_96m_fclk",
1459 .prcm = {
1460 .omap4 = {
1461 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1462 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1463 .modulemode = MODULEMODE_SWCTRL,
1464 },
1465 },
1466 .dev_attr = &i2c_dev_attr,
1467 };
1468
1469 /*
1470 * 'ipu' class
1471 * imaging processor unit
1472 */
1473
1474 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1475 .name = "ipu",
1476 };
1477
1478 /* ipu */
1479 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1480 { .name = "cpu0", .rst_shift = 0 },
1481 { .name = "cpu1", .rst_shift = 1 },
1482 };
1483
1484 static struct omap_hwmod omap44xx_ipu_hwmod = {
1485 .name = "ipu",
1486 .class = &omap44xx_ipu_hwmod_class,
1487 .clkdm_name = "ducati_clkdm",
1488 .rst_lines = omap44xx_ipu_resets,
1489 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1490 .main_clk = "ducati_clk_mux_ck",
1491 .prcm = {
1492 .omap4 = {
1493 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1494 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1495 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1496 .modulemode = MODULEMODE_HWCTRL,
1497 },
1498 },
1499 };
1500
1501 /*
1502 * 'iss' class
1503 * external images sensor pixel data processor
1504 */
1505
1506 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1507 .rev_offs = 0x0000,
1508 .sysc_offs = 0x0010,
1509 /*
1510 * ISS needs 100 OCP clk cycles delay after a softreset before
1511 * accessing sysconfig again.
1512 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1513 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1514 *
1515 * TODO: Indicate errata when available.
1516 */
1517 .srst_udelay = 2,
1518 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1519 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1520 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1521 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1522 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1523 .sysc_fields = &omap_hwmod_sysc_type2,
1524 };
1525
1526 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1527 .name = "iss",
1528 .sysc = &omap44xx_iss_sysc,
1529 };
1530
1531 /* iss */
1532 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1533 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1534 };
1535
1536 static struct omap_hwmod omap44xx_iss_hwmod = {
1537 .name = "iss",
1538 .class = &omap44xx_iss_hwmod_class,
1539 .clkdm_name = "iss_clkdm",
1540 .main_clk = "ducati_clk_mux_ck",
1541 .prcm = {
1542 .omap4 = {
1543 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1544 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1545 .modulemode = MODULEMODE_SWCTRL,
1546 },
1547 },
1548 .opt_clks = iss_opt_clks,
1549 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1550 };
1551
1552 /*
1553 * 'iva' class
1554 * multi-standard video encoder/decoder hardware accelerator
1555 */
1556
1557 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1558 .name = "iva",
1559 };
1560
1561 /* iva */
1562 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1563 { .name = "seq0", .rst_shift = 0 },
1564 { .name = "seq1", .rst_shift = 1 },
1565 { .name = "logic", .rst_shift = 2 },
1566 };
1567
1568 static struct omap_hwmod omap44xx_iva_hwmod = {
1569 .name = "iva",
1570 .class = &omap44xx_iva_hwmod_class,
1571 .clkdm_name = "ivahd_clkdm",
1572 .rst_lines = omap44xx_iva_resets,
1573 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1574 .main_clk = "dpll_iva_m5x2_ck",
1575 .prcm = {
1576 .omap4 = {
1577 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1578 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1579 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1580 .modulemode = MODULEMODE_HWCTRL,
1581 },
1582 },
1583 };
1584
1585 /*
1586 * 'kbd' class
1587 * keyboard controller
1588 */
1589
1590 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1591 .rev_offs = 0x0000,
1592 .sysc_offs = 0x0010,
1593 .syss_offs = 0x0014,
1594 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1595 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1596 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1597 SYSS_HAS_RESET_STATUS),
1598 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1599 .sysc_fields = &omap_hwmod_sysc_type1,
1600 };
1601
1602 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1603 .name = "kbd",
1604 .sysc = &omap44xx_kbd_sysc,
1605 };
1606
1607 /* kbd */
1608 static struct omap_hwmod omap44xx_kbd_hwmod = {
1609 .name = "kbd",
1610 .class = &omap44xx_kbd_hwmod_class,
1611 .clkdm_name = "l4_wkup_clkdm",
1612 .main_clk = "sys_32k_ck",
1613 .prcm = {
1614 .omap4 = {
1615 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1616 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1617 .modulemode = MODULEMODE_SWCTRL,
1618 },
1619 },
1620 };
1621
1622 /*
1623 * 'mailbox' class
1624 * mailbox module allowing communication between the on-chip processors using a
1625 * queued mailbox-interrupt mechanism.
1626 */
1627
1628 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1629 .rev_offs = 0x0000,
1630 .sysc_offs = 0x0010,
1631 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1632 SYSC_HAS_SOFTRESET),
1633 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1634 .sysc_fields = &omap_hwmod_sysc_type2,
1635 };
1636
1637 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1638 .name = "mailbox",
1639 .sysc = &omap44xx_mailbox_sysc,
1640 };
1641
1642 /* mailbox */
1643 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1644 .name = "mailbox",
1645 .class = &omap44xx_mailbox_hwmod_class,
1646 .clkdm_name = "l4_cfg_clkdm",
1647 .prcm = {
1648 .omap4 = {
1649 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1650 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1651 },
1652 },
1653 };
1654
1655 /*
1656 * 'mcasp' class
1657 * multi-channel audio serial port controller
1658 */
1659
1660 /* The IP is not compliant to type1 / type2 scheme */
1661 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1662 .sysc_offs = 0x0004,
1663 .sysc_flags = SYSC_HAS_SIDLEMODE,
1664 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1665 SIDLE_SMART_WKUP),
1666 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1667 };
1668
1669 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1670 .name = "mcasp",
1671 .sysc = &omap44xx_mcasp_sysc,
1672 };
1673
1674 /* mcasp */
1675 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1676 .name = "mcasp",
1677 .class = &omap44xx_mcasp_hwmod_class,
1678 .clkdm_name = "abe_clkdm",
1679 .main_clk = "func_mcasp_abe_gfclk",
1680 .prcm = {
1681 .omap4 = {
1682 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1683 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1684 .modulemode = MODULEMODE_SWCTRL,
1685 },
1686 },
1687 };
1688
1689 /*
1690 * 'mcbsp' class
1691 * multi channel buffered serial port controller
1692 */
1693
1694 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1695 .sysc_offs = 0x008c,
1696 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1697 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1698 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1699 .sysc_fields = &omap_hwmod_sysc_type1,
1700 };
1701
1702 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1703 .name = "mcbsp",
1704 .sysc = &omap44xx_mcbsp_sysc,
1705 .rev = MCBSP_CONFIG_TYPE4,
1706 };
1707
1708 /* mcbsp1 */
1709 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1710 { .role = "pad_fck", .clk = "pad_clks_ck" },
1711 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1712 };
1713
1714 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1715 .name = "mcbsp1",
1716 .class = &omap44xx_mcbsp_hwmod_class,
1717 .clkdm_name = "abe_clkdm",
1718 .main_clk = "func_mcbsp1_gfclk",
1719 .prcm = {
1720 .omap4 = {
1721 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1722 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1723 .modulemode = MODULEMODE_SWCTRL,
1724 },
1725 },
1726 .opt_clks = mcbsp1_opt_clks,
1727 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1728 };
1729
1730 /* mcbsp2 */
1731 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1732 { .role = "pad_fck", .clk = "pad_clks_ck" },
1733 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1734 };
1735
1736 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1737 .name = "mcbsp2",
1738 .class = &omap44xx_mcbsp_hwmod_class,
1739 .clkdm_name = "abe_clkdm",
1740 .main_clk = "func_mcbsp2_gfclk",
1741 .prcm = {
1742 .omap4 = {
1743 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1744 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1745 .modulemode = MODULEMODE_SWCTRL,
1746 },
1747 },
1748 .opt_clks = mcbsp2_opt_clks,
1749 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1750 };
1751
1752 /* mcbsp3 */
1753 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1754 { .role = "pad_fck", .clk = "pad_clks_ck" },
1755 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1756 };
1757
1758 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1759 .name = "mcbsp3",
1760 .class = &omap44xx_mcbsp_hwmod_class,
1761 .clkdm_name = "abe_clkdm",
1762 .main_clk = "func_mcbsp3_gfclk",
1763 .prcm = {
1764 .omap4 = {
1765 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1766 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1767 .modulemode = MODULEMODE_SWCTRL,
1768 },
1769 },
1770 .opt_clks = mcbsp3_opt_clks,
1771 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
1772 };
1773
1774 /* mcbsp4 */
1775 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1776 { .role = "pad_fck", .clk = "pad_clks_ck" },
1777 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1778 };
1779
1780 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1781 .name = "mcbsp4",
1782 .class = &omap44xx_mcbsp_hwmod_class,
1783 .clkdm_name = "l4_per_clkdm",
1784 .main_clk = "per_mcbsp4_gfclk",
1785 .prcm = {
1786 .omap4 = {
1787 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1788 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1789 .modulemode = MODULEMODE_SWCTRL,
1790 },
1791 },
1792 .opt_clks = mcbsp4_opt_clks,
1793 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
1794 };
1795
1796 /*
1797 * 'mcpdm' class
1798 * multi channel pdm controller (proprietary interface with phoenix power
1799 * ic)
1800 */
1801
1802 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1803 .rev_offs = 0x0000,
1804 .sysc_offs = 0x0010,
1805 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1806 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1807 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1808 SIDLE_SMART_WKUP),
1809 .sysc_fields = &omap_hwmod_sysc_type2,
1810 };
1811
1812 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1813 .name = "mcpdm",
1814 .sysc = &omap44xx_mcpdm_sysc,
1815 };
1816
1817 /* mcpdm */
1818 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1819 .name = "mcpdm",
1820 .class = &omap44xx_mcpdm_hwmod_class,
1821 .clkdm_name = "abe_clkdm",
1822 /*
1823 * It's suspected that the McPDM requires an off-chip main
1824 * functional clock, controlled via I2C. This IP block is
1825 * currently reset very early during boot, before I2C is
1826 * available, so it doesn't seem that we have any choice in
1827 * the kernel other than to avoid resetting it.
1828 *
1829 * Also, McPDM needs to be configured to NO_IDLE mode when it
1830 * is in used otherwise vital clocks will be gated which
1831 * results 'slow motion' audio playback.
1832 */
1833 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1834 .main_clk = "pad_clks_ck",
1835 .prcm = {
1836 .omap4 = {
1837 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1838 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1839 .modulemode = MODULEMODE_SWCTRL,
1840 },
1841 },
1842 };
1843
1844 /*
1845 * 'mcspi' class
1846 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1847 * bus
1848 */
1849
1850 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1851 .rev_offs = 0x0000,
1852 .sysc_offs = 0x0010,
1853 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1854 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1855 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1856 SIDLE_SMART_WKUP),
1857 .sysc_fields = &omap_hwmod_sysc_type2,
1858 };
1859
1860 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1861 .name = "mcspi",
1862 .sysc = &omap44xx_mcspi_sysc,
1863 .rev = OMAP4_MCSPI_REV,
1864 };
1865
1866 /* mcspi1 */
1867 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1868 .num_chipselect = 4,
1869 };
1870
1871 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1872 .name = "mcspi1",
1873 .class = &omap44xx_mcspi_hwmod_class,
1874 .clkdm_name = "l4_per_clkdm",
1875 .main_clk = "func_48m_fclk",
1876 .prcm = {
1877 .omap4 = {
1878 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1879 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1880 .modulemode = MODULEMODE_SWCTRL,
1881 },
1882 },
1883 .dev_attr = &mcspi1_dev_attr,
1884 };
1885
1886 /* mcspi2 */
1887 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1888 .num_chipselect = 2,
1889 };
1890
1891 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1892 .name = "mcspi2",
1893 .class = &omap44xx_mcspi_hwmod_class,
1894 .clkdm_name = "l4_per_clkdm",
1895 .main_clk = "func_48m_fclk",
1896 .prcm = {
1897 .omap4 = {
1898 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1899 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1900 .modulemode = MODULEMODE_SWCTRL,
1901 },
1902 },
1903 .dev_attr = &mcspi2_dev_attr,
1904 };
1905
1906 /* mcspi3 */
1907 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1908 .num_chipselect = 2,
1909 };
1910
1911 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1912 .name = "mcspi3",
1913 .class = &omap44xx_mcspi_hwmod_class,
1914 .clkdm_name = "l4_per_clkdm",
1915 .main_clk = "func_48m_fclk",
1916 .prcm = {
1917 .omap4 = {
1918 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1919 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1920 .modulemode = MODULEMODE_SWCTRL,
1921 },
1922 },
1923 .dev_attr = &mcspi3_dev_attr,
1924 };
1925
1926 /* mcspi4 */
1927 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1928 .num_chipselect = 1,
1929 };
1930
1931 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1932 .name = "mcspi4",
1933 .class = &omap44xx_mcspi_hwmod_class,
1934 .clkdm_name = "l4_per_clkdm",
1935 .main_clk = "func_48m_fclk",
1936 .prcm = {
1937 .omap4 = {
1938 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1939 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1940 .modulemode = MODULEMODE_SWCTRL,
1941 },
1942 },
1943 .dev_attr = &mcspi4_dev_attr,
1944 };
1945
1946 /*
1947 * 'mmc' class
1948 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1949 */
1950
1951 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1952 .rev_offs = 0x0000,
1953 .sysc_offs = 0x0010,
1954 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1955 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1956 SYSC_HAS_SOFTRESET),
1957 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1958 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1959 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1960 .sysc_fields = &omap_hwmod_sysc_type2,
1961 };
1962
1963 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1964 .name = "mmc",
1965 .sysc = &omap44xx_mmc_sysc,
1966 };
1967
1968 /* mmc1 */
1969 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1970 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1971 };
1972
1973 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1974 .name = "mmc1",
1975 .class = &omap44xx_mmc_hwmod_class,
1976 .clkdm_name = "l3_init_clkdm",
1977 .main_clk = "hsmmc1_fclk",
1978 .prcm = {
1979 .omap4 = {
1980 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1981 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1982 .modulemode = MODULEMODE_SWCTRL,
1983 },
1984 },
1985 .dev_attr = &mmc1_dev_attr,
1986 };
1987
1988 /* mmc2 */
1989 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1990 .name = "mmc2",
1991 .class = &omap44xx_mmc_hwmod_class,
1992 .clkdm_name = "l3_init_clkdm",
1993 .main_clk = "hsmmc2_fclk",
1994 .prcm = {
1995 .omap4 = {
1996 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1997 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1998 .modulemode = MODULEMODE_SWCTRL,
1999 },
2000 },
2001 };
2002
2003 /* mmc3 */
2004 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2005 .name = "mmc3",
2006 .class = &omap44xx_mmc_hwmod_class,
2007 .clkdm_name = "l4_per_clkdm",
2008 .main_clk = "func_48m_fclk",
2009 .prcm = {
2010 .omap4 = {
2011 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2012 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2013 .modulemode = MODULEMODE_SWCTRL,
2014 },
2015 },
2016 };
2017
2018 /* mmc4 */
2019 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2020 .name = "mmc4",
2021 .class = &omap44xx_mmc_hwmod_class,
2022 .clkdm_name = "l4_per_clkdm",
2023 .main_clk = "func_48m_fclk",
2024 .prcm = {
2025 .omap4 = {
2026 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2027 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2028 .modulemode = MODULEMODE_SWCTRL,
2029 },
2030 },
2031 };
2032
2033 /* mmc5 */
2034 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2035 .name = "mmc5",
2036 .class = &omap44xx_mmc_hwmod_class,
2037 .clkdm_name = "l4_per_clkdm",
2038 .main_clk = "func_48m_fclk",
2039 .prcm = {
2040 .omap4 = {
2041 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2042 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2043 .modulemode = MODULEMODE_SWCTRL,
2044 },
2045 },
2046 };
2047
2048 /*
2049 * 'mmu' class
2050 * The memory management unit performs virtual to physical address translation
2051 * for its requestors.
2052 */
2053
2054 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2055 .rev_offs = 0x000,
2056 .sysc_offs = 0x010,
2057 .syss_offs = 0x014,
2058 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2059 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2060 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2061 .sysc_fields = &omap_hwmod_sysc_type1,
2062 };
2063
2064 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2065 .name = "mmu",
2066 .sysc = &mmu_sysc,
2067 };
2068
2069 /* mmu ipu */
2070
2071 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2072 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2073 { .name = "mmu_cache", .rst_shift = 2 },
2074 };
2075
2076 /* l3_main_2 -> mmu_ipu */
2077 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2078 .master = &omap44xx_l3_main_2_hwmod,
2079 .slave = &omap44xx_mmu_ipu_hwmod,
2080 .clk = "l3_div_ck",
2081 .user = OCP_USER_MPU | OCP_USER_SDMA,
2082 };
2083
2084 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2085 .name = "mmu_ipu",
2086 .class = &omap44xx_mmu_hwmod_class,
2087 .clkdm_name = "ducati_clkdm",
2088 .rst_lines = omap44xx_mmu_ipu_resets,
2089 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2090 .main_clk = "ducati_clk_mux_ck",
2091 .prcm = {
2092 .omap4 = {
2093 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2094 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2095 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2096 .modulemode = MODULEMODE_HWCTRL,
2097 },
2098 },
2099 };
2100
2101 /* mmu dsp */
2102
2103 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2104 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2105 { .name = "mmu_cache", .rst_shift = 1 },
2106 };
2107
2108 /* l4_cfg -> dsp */
2109 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2110 .master = &omap44xx_l4_cfg_hwmod,
2111 .slave = &omap44xx_mmu_dsp_hwmod,
2112 .clk = "l4_div_ck",
2113 .user = OCP_USER_MPU | OCP_USER_SDMA,
2114 };
2115
2116 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2117 .name = "mmu_dsp",
2118 .class = &omap44xx_mmu_hwmod_class,
2119 .clkdm_name = "tesla_clkdm",
2120 .rst_lines = omap44xx_mmu_dsp_resets,
2121 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2122 .main_clk = "dpll_iva_m4x2_ck",
2123 .prcm = {
2124 .omap4 = {
2125 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2126 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2127 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2128 .modulemode = MODULEMODE_HWCTRL,
2129 },
2130 },
2131 };
2132
2133 /*
2134 * 'mpu' class
2135 * mpu sub-system
2136 */
2137
2138 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2139 .name = "mpu",
2140 };
2141
2142 /* mpu */
2143 static struct omap_hwmod omap44xx_mpu_hwmod = {
2144 .name = "mpu",
2145 .class = &omap44xx_mpu_hwmod_class,
2146 .clkdm_name = "mpuss_clkdm",
2147 .flags = HWMOD_INIT_NO_IDLE,
2148 .main_clk = "dpll_mpu_m2_ck",
2149 .prcm = {
2150 .omap4 = {
2151 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2152 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2153 },
2154 },
2155 };
2156
2157 /*
2158 * 'ocmc_ram' class
2159 * top-level core on-chip ram
2160 */
2161
2162 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2163 .name = "ocmc_ram",
2164 };
2165
2166 /* ocmc_ram */
2167 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2168 .name = "ocmc_ram",
2169 .class = &omap44xx_ocmc_ram_hwmod_class,
2170 .clkdm_name = "l3_2_clkdm",
2171 .prcm = {
2172 .omap4 = {
2173 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2174 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2175 },
2176 },
2177 };
2178
2179 /*
2180 * 'ocp2scp' class
2181 * bridge to transform ocp interface protocol to scp (serial control port)
2182 * protocol
2183 */
2184
2185 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2186 .rev_offs = 0x0000,
2187 .sysc_offs = 0x0010,
2188 .syss_offs = 0x0014,
2189 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2190 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2191 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2192 .sysc_fields = &omap_hwmod_sysc_type1,
2193 };
2194
2195 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2196 .name = "ocp2scp",
2197 .sysc = &omap44xx_ocp2scp_sysc,
2198 };
2199
2200 /* ocp2scp_usb_phy */
2201 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2202 .name = "ocp2scp_usb_phy",
2203 .class = &omap44xx_ocp2scp_hwmod_class,
2204 .clkdm_name = "l3_init_clkdm",
2205 /*
2206 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2207 * block as an "optional clock," and normally should never be
2208 * specified as the main_clk for an OMAP IP block. However it
2209 * turns out that this clock is actually the main clock for
2210 * the ocp2scp_usb_phy IP block:
2211 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2212 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2213 * to be the best workaround.
2214 */
2215 .main_clk = "ocp2scp_usb_phy_phy_48m",
2216 .prcm = {
2217 .omap4 = {
2218 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2219 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2220 .modulemode = MODULEMODE_HWCTRL,
2221 },
2222 },
2223 };
2224
2225 /*
2226 * 'prcm' class
2227 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2228 * + clock manager 1 (in always on power domain) + local prm in mpu
2229 */
2230
2231 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2232 .name = "prcm",
2233 };
2234
2235 /* prcm_mpu */
2236 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2237 .name = "prcm_mpu",
2238 .class = &omap44xx_prcm_hwmod_class,
2239 .clkdm_name = "l4_wkup_clkdm",
2240 .flags = HWMOD_NO_IDLEST,
2241 .prcm = {
2242 .omap4 = {
2243 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2244 },
2245 },
2246 };
2247
2248 /* cm_core_aon */
2249 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2250 .name = "cm_core_aon",
2251 .class = &omap44xx_prcm_hwmod_class,
2252 .flags = HWMOD_NO_IDLEST,
2253 .prcm = {
2254 .omap4 = {
2255 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2256 },
2257 },
2258 };
2259
2260 /* cm_core */
2261 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2262 .name = "cm_core",
2263 .class = &omap44xx_prcm_hwmod_class,
2264 .flags = HWMOD_NO_IDLEST,
2265 .prcm = {
2266 .omap4 = {
2267 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2268 },
2269 },
2270 };
2271
2272 /* prm */
2273 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2274 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2275 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2276 };
2277
2278 static struct omap_hwmod omap44xx_prm_hwmod = {
2279 .name = "prm",
2280 .class = &omap44xx_prcm_hwmod_class,
2281 .rst_lines = omap44xx_prm_resets,
2282 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2283 };
2284
2285 /*
2286 * 'scrm' class
2287 * system clock and reset manager
2288 */
2289
2290 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2291 .name = "scrm",
2292 };
2293
2294 /* scrm */
2295 static struct omap_hwmod omap44xx_scrm_hwmod = {
2296 .name = "scrm",
2297 .class = &omap44xx_scrm_hwmod_class,
2298 .clkdm_name = "l4_wkup_clkdm",
2299 .prcm = {
2300 .omap4 = {
2301 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2302 },
2303 },
2304 };
2305
2306 /*
2307 * 'sl2if' class
2308 * shared level 2 memory interface
2309 */
2310
2311 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2312 .name = "sl2if",
2313 };
2314
2315 /* sl2if */
2316 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2317 .name = "sl2if",
2318 .class = &omap44xx_sl2if_hwmod_class,
2319 .clkdm_name = "ivahd_clkdm",
2320 .prcm = {
2321 .omap4 = {
2322 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2323 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2324 .modulemode = MODULEMODE_HWCTRL,
2325 },
2326 },
2327 };
2328
2329 /*
2330 * 'slimbus' class
2331 * bidirectional, multi-drop, multi-channel two-line serial interface between
2332 * the device and external components
2333 */
2334
2335 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2336 .rev_offs = 0x0000,
2337 .sysc_offs = 0x0010,
2338 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2339 SYSC_HAS_SOFTRESET),
2340 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2341 SIDLE_SMART_WKUP),
2342 .sysc_fields = &omap_hwmod_sysc_type2,
2343 };
2344
2345 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2346 .name = "slimbus",
2347 .sysc = &omap44xx_slimbus_sysc,
2348 };
2349
2350 /* slimbus1 */
2351 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2352 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2353 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2354 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2355 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2356 };
2357
2358 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2359 .name = "slimbus1",
2360 .class = &omap44xx_slimbus_hwmod_class,
2361 .clkdm_name = "abe_clkdm",
2362 .prcm = {
2363 .omap4 = {
2364 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2365 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2366 .modulemode = MODULEMODE_SWCTRL,
2367 },
2368 },
2369 .opt_clks = slimbus1_opt_clks,
2370 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2371 };
2372
2373 /* slimbus2 */
2374 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2375 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2376 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2377 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2378 };
2379
2380 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2381 .name = "slimbus2",
2382 .class = &omap44xx_slimbus_hwmod_class,
2383 .clkdm_name = "l4_per_clkdm",
2384 .prcm = {
2385 .omap4 = {
2386 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2387 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2388 .modulemode = MODULEMODE_SWCTRL,
2389 },
2390 },
2391 .opt_clks = slimbus2_opt_clks,
2392 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2393 };
2394
2395 /*
2396 * 'smartreflex' class
2397 * smartreflex module (monitor silicon performance and outputs a measure of
2398 * performance error)
2399 */
2400
2401 /* The IP is not compliant to type1 / type2 scheme */
2402 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2403 .sysc_offs = 0x0038,
2404 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2405 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2406 SIDLE_SMART_WKUP),
2407 .sysc_fields = &omap36xx_sr_sysc_fields,
2408 };
2409
2410 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2411 .name = "smartreflex",
2412 .sysc = &omap44xx_smartreflex_sysc,
2413 .rev = 2,
2414 };
2415
2416 /* smartreflex_core */
2417 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2418 .sensor_voltdm_name = "core",
2419 };
2420
2421 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2422 .name = "smartreflex_core",
2423 .class = &omap44xx_smartreflex_hwmod_class,
2424 .clkdm_name = "l4_ao_clkdm",
2425
2426 .main_clk = "smartreflex_core_fck",
2427 .prcm = {
2428 .omap4 = {
2429 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2430 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2431 .modulemode = MODULEMODE_SWCTRL,
2432 },
2433 },
2434 .dev_attr = &smartreflex_core_dev_attr,
2435 };
2436
2437 /* smartreflex_iva */
2438 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2439 .sensor_voltdm_name = "iva",
2440 };
2441
2442 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2443 .name = "smartreflex_iva",
2444 .class = &omap44xx_smartreflex_hwmod_class,
2445 .clkdm_name = "l4_ao_clkdm",
2446 .main_clk = "smartreflex_iva_fck",
2447 .prcm = {
2448 .omap4 = {
2449 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2450 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2451 .modulemode = MODULEMODE_SWCTRL,
2452 },
2453 },
2454 .dev_attr = &smartreflex_iva_dev_attr,
2455 };
2456
2457 /* smartreflex_mpu */
2458 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2459 .sensor_voltdm_name = "mpu",
2460 };
2461
2462 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2463 .name = "smartreflex_mpu",
2464 .class = &omap44xx_smartreflex_hwmod_class,
2465 .clkdm_name = "l4_ao_clkdm",
2466 .main_clk = "smartreflex_mpu_fck",
2467 .prcm = {
2468 .omap4 = {
2469 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2470 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2471 .modulemode = MODULEMODE_SWCTRL,
2472 },
2473 },
2474 .dev_attr = &smartreflex_mpu_dev_attr,
2475 };
2476
2477 /*
2478 * 'spinlock' class
2479 * spinlock provides hardware assistance for synchronizing the processes
2480 * running on multiple processors
2481 */
2482
2483 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2484 .rev_offs = 0x0000,
2485 .sysc_offs = 0x0010,
2486 .syss_offs = 0x0014,
2487 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2488 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2489 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2490 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2491 .sysc_fields = &omap_hwmod_sysc_type1,
2492 };
2493
2494 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2495 .name = "spinlock",
2496 .sysc = &omap44xx_spinlock_sysc,
2497 };
2498
2499 /* spinlock */
2500 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2501 .name = "spinlock",
2502 .class = &omap44xx_spinlock_hwmod_class,
2503 .clkdm_name = "l4_cfg_clkdm",
2504 .prcm = {
2505 .omap4 = {
2506 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2507 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2508 },
2509 },
2510 };
2511
2512 /*
2513 * 'timer' class
2514 * general purpose timer module with accurate 1ms tick
2515 * This class contains several variants: ['timer_1ms', 'timer']
2516 */
2517
2518 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2519 .rev_offs = 0x0000,
2520 .sysc_offs = 0x0010,
2521 .syss_offs = 0x0014,
2522 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2523 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2524 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2525 SYSS_HAS_RESET_STATUS),
2526 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2527 .sysc_fields = &omap_hwmod_sysc_type1,
2528 };
2529
2530 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2531 .name = "timer",
2532 .sysc = &omap44xx_timer_1ms_sysc,
2533 };
2534
2535 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2536 .rev_offs = 0x0000,
2537 .sysc_offs = 0x0010,
2538 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2539 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2540 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2541 SIDLE_SMART_WKUP),
2542 .sysc_fields = &omap_hwmod_sysc_type2,
2543 };
2544
2545 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2546 .name = "timer",
2547 .sysc = &omap44xx_timer_sysc,
2548 };
2549
2550 /* always-on timers dev attribute */
2551 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2552 .timer_capability = OMAP_TIMER_ALWON,
2553 };
2554
2555 /* pwm timers dev attribute */
2556 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2557 .timer_capability = OMAP_TIMER_HAS_PWM,
2558 };
2559
2560 /* timers with DSP interrupt dev attribute */
2561 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2562 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
2563 };
2564
2565 /* pwm timers with DSP interrupt dev attribute */
2566 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2567 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2568 };
2569
2570 /* timer1 */
2571 static struct omap_hwmod omap44xx_timer1_hwmod = {
2572 .name = "timer1",
2573 .class = &omap44xx_timer_1ms_hwmod_class,
2574 .clkdm_name = "l4_wkup_clkdm",
2575 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2576 .main_clk = "dmt1_clk_mux",
2577 .prcm = {
2578 .omap4 = {
2579 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2580 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2581 .modulemode = MODULEMODE_SWCTRL,
2582 },
2583 },
2584 .dev_attr = &capability_alwon_dev_attr,
2585 };
2586
2587 /* timer2 */
2588 static struct omap_hwmod omap44xx_timer2_hwmod = {
2589 .name = "timer2",
2590 .class = &omap44xx_timer_1ms_hwmod_class,
2591 .clkdm_name = "l4_per_clkdm",
2592 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2593 .main_clk = "cm2_dm2_mux",
2594 .prcm = {
2595 .omap4 = {
2596 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2597 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2598 .modulemode = MODULEMODE_SWCTRL,
2599 },
2600 },
2601 };
2602
2603 /* timer3 */
2604 static struct omap_hwmod omap44xx_timer3_hwmod = {
2605 .name = "timer3",
2606 .class = &omap44xx_timer_hwmod_class,
2607 .clkdm_name = "l4_per_clkdm",
2608 .main_clk = "cm2_dm3_mux",
2609 .prcm = {
2610 .omap4 = {
2611 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2612 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2613 .modulemode = MODULEMODE_SWCTRL,
2614 },
2615 },
2616 };
2617
2618 /* timer4 */
2619 static struct omap_hwmod omap44xx_timer4_hwmod = {
2620 .name = "timer4",
2621 .class = &omap44xx_timer_hwmod_class,
2622 .clkdm_name = "l4_per_clkdm",
2623 .main_clk = "cm2_dm4_mux",
2624 .prcm = {
2625 .omap4 = {
2626 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2627 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2628 .modulemode = MODULEMODE_SWCTRL,
2629 },
2630 },
2631 };
2632
2633 /* timer5 */
2634 static struct omap_hwmod omap44xx_timer5_hwmod = {
2635 .name = "timer5",
2636 .class = &omap44xx_timer_hwmod_class,
2637 .clkdm_name = "abe_clkdm",
2638 .main_clk = "timer5_sync_mux",
2639 .prcm = {
2640 .omap4 = {
2641 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2642 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2643 .modulemode = MODULEMODE_SWCTRL,
2644 },
2645 },
2646 .dev_attr = &capability_dsp_dev_attr,
2647 };
2648
2649 /* timer6 */
2650 static struct omap_hwmod omap44xx_timer6_hwmod = {
2651 .name = "timer6",
2652 .class = &omap44xx_timer_hwmod_class,
2653 .clkdm_name = "abe_clkdm",
2654 .main_clk = "timer6_sync_mux",
2655 .prcm = {
2656 .omap4 = {
2657 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2658 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2659 .modulemode = MODULEMODE_SWCTRL,
2660 },
2661 },
2662 .dev_attr = &capability_dsp_dev_attr,
2663 };
2664
2665 /* timer7 */
2666 static struct omap_hwmod omap44xx_timer7_hwmod = {
2667 .name = "timer7",
2668 .class = &omap44xx_timer_hwmod_class,
2669 .clkdm_name = "abe_clkdm",
2670 .main_clk = "timer7_sync_mux",
2671 .prcm = {
2672 .omap4 = {
2673 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2674 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2675 .modulemode = MODULEMODE_SWCTRL,
2676 },
2677 },
2678 .dev_attr = &capability_dsp_dev_attr,
2679 };
2680
2681 /* timer8 */
2682 static struct omap_hwmod omap44xx_timer8_hwmod = {
2683 .name = "timer8",
2684 .class = &omap44xx_timer_hwmod_class,
2685 .clkdm_name = "abe_clkdm",
2686 .main_clk = "timer8_sync_mux",
2687 .prcm = {
2688 .omap4 = {
2689 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2690 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2691 .modulemode = MODULEMODE_SWCTRL,
2692 },
2693 },
2694 .dev_attr = &capability_dsp_pwm_dev_attr,
2695 };
2696
2697 /* timer9 */
2698 static struct omap_hwmod omap44xx_timer9_hwmod = {
2699 .name = "timer9",
2700 .class = &omap44xx_timer_hwmod_class,
2701 .clkdm_name = "l4_per_clkdm",
2702 .main_clk = "cm2_dm9_mux",
2703 .prcm = {
2704 .omap4 = {
2705 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2706 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2707 .modulemode = MODULEMODE_SWCTRL,
2708 },
2709 },
2710 .dev_attr = &capability_pwm_dev_attr,
2711 };
2712
2713 /* timer10 */
2714 static struct omap_hwmod omap44xx_timer10_hwmod = {
2715 .name = "timer10",
2716 .class = &omap44xx_timer_1ms_hwmod_class,
2717 .clkdm_name = "l4_per_clkdm",
2718 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2719 .main_clk = "cm2_dm10_mux",
2720 .prcm = {
2721 .omap4 = {
2722 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2723 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2724 .modulemode = MODULEMODE_SWCTRL,
2725 },
2726 },
2727 .dev_attr = &capability_pwm_dev_attr,
2728 };
2729
2730 /* timer11 */
2731 static struct omap_hwmod omap44xx_timer11_hwmod = {
2732 .name = "timer11",
2733 .class = &omap44xx_timer_hwmod_class,
2734 .clkdm_name = "l4_per_clkdm",
2735 .main_clk = "cm2_dm11_mux",
2736 .prcm = {
2737 .omap4 = {
2738 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2739 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2740 .modulemode = MODULEMODE_SWCTRL,
2741 },
2742 },
2743 .dev_attr = &capability_pwm_dev_attr,
2744 };
2745
2746 /*
2747 * 'uart' class
2748 * universal asynchronous receiver/transmitter (uart)
2749 */
2750
2751 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2752 .rev_offs = 0x0050,
2753 .sysc_offs = 0x0054,
2754 .syss_offs = 0x0058,
2755 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2756 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2757 SYSS_HAS_RESET_STATUS),
2758 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2759 SIDLE_SMART_WKUP),
2760 .sysc_fields = &omap_hwmod_sysc_type1,
2761 };
2762
2763 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2764 .name = "uart",
2765 .sysc = &omap44xx_uart_sysc,
2766 };
2767
2768 /* uart1 */
2769 static struct omap_hwmod omap44xx_uart1_hwmod = {
2770 .name = "uart1",
2771 .class = &omap44xx_uart_hwmod_class,
2772 .clkdm_name = "l4_per_clkdm",
2773 .flags = HWMOD_SWSUP_SIDLE_ACT,
2774 .main_clk = "func_48m_fclk",
2775 .prcm = {
2776 .omap4 = {
2777 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2778 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2779 .modulemode = MODULEMODE_SWCTRL,
2780 },
2781 },
2782 };
2783
2784 /* uart2 */
2785 static struct omap_hwmod omap44xx_uart2_hwmod = {
2786 .name = "uart2",
2787 .class = &omap44xx_uart_hwmod_class,
2788 .clkdm_name = "l4_per_clkdm",
2789 .flags = HWMOD_SWSUP_SIDLE_ACT,
2790 .main_clk = "func_48m_fclk",
2791 .prcm = {
2792 .omap4 = {
2793 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2794 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2795 .modulemode = MODULEMODE_SWCTRL,
2796 },
2797 },
2798 };
2799
2800 /* uart3 */
2801 static struct omap_hwmod omap44xx_uart3_hwmod = {
2802 .name = "uart3",
2803 .class = &omap44xx_uart_hwmod_class,
2804 .clkdm_name = "l4_per_clkdm",
2805 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2806 .main_clk = "func_48m_fclk",
2807 .prcm = {
2808 .omap4 = {
2809 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2810 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2811 .modulemode = MODULEMODE_SWCTRL,
2812 },
2813 },
2814 };
2815
2816 /* uart4 */
2817 static struct omap_hwmod omap44xx_uart4_hwmod = {
2818 .name = "uart4",
2819 .class = &omap44xx_uart_hwmod_class,
2820 .clkdm_name = "l4_per_clkdm",
2821 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2822 .main_clk = "func_48m_fclk",
2823 .prcm = {
2824 .omap4 = {
2825 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2826 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2827 .modulemode = MODULEMODE_SWCTRL,
2828 },
2829 },
2830 };
2831
2832 /*
2833 * 'usb_host_fs' class
2834 * full-speed usb host controller
2835 */
2836
2837 /* The IP is not compliant to type1 / type2 scheme */
2838 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2839 .rev_offs = 0x0000,
2840 .sysc_offs = 0x0210,
2841 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2842 SYSC_HAS_SOFTRESET),
2843 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2844 SIDLE_SMART_WKUP),
2845 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
2846 };
2847
2848 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2849 .name = "usb_host_fs",
2850 .sysc = &omap44xx_usb_host_fs_sysc,
2851 };
2852
2853 /* usb_host_fs */
2854 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2855 .name = "usb_host_fs",
2856 .class = &omap44xx_usb_host_fs_hwmod_class,
2857 .clkdm_name = "l3_init_clkdm",
2858 .main_clk = "usb_host_fs_fck",
2859 .prcm = {
2860 .omap4 = {
2861 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2862 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2863 .modulemode = MODULEMODE_SWCTRL,
2864 },
2865 },
2866 };
2867
2868 /*
2869 * 'usb_host_hs' class
2870 * high-speed multi-port usb host controller
2871 */
2872
2873 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2874 .rev_offs = 0x0000,
2875 .sysc_offs = 0x0010,
2876 .syss_offs = 0x0014,
2877 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2878 SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2879 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2880 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2881 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2882 .sysc_fields = &omap_hwmod_sysc_type2,
2883 };
2884
2885 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2886 .name = "usb_host_hs",
2887 .sysc = &omap44xx_usb_host_hs_sysc,
2888 };
2889
2890 /* usb_host_hs */
2891 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2892 .name = "usb_host_hs",
2893 .class = &omap44xx_usb_host_hs_hwmod_class,
2894 .clkdm_name = "l3_init_clkdm",
2895 .main_clk = "usb_host_hs_fck",
2896 .prcm = {
2897 .omap4 = {
2898 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2899 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2900 .modulemode = MODULEMODE_SWCTRL,
2901 },
2902 },
2903
2904 /*
2905 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2906 * id: i660
2907 *
2908 * Description:
2909 * In the following configuration :
2910 * - USBHOST module is set to smart-idle mode
2911 * - PRCM asserts idle_req to the USBHOST module ( This typically
2912 * happens when the system is going to a low power mode : all ports
2913 * have been suspended, the master part of the USBHOST module has
2914 * entered the standby state, and SW has cut the functional clocks)
2915 * - an USBHOST interrupt occurs before the module is able to answer
2916 * idle_ack, typically a remote wakeup IRQ.
2917 * Then the USB HOST module will enter a deadlock situation where it
2918 * is no more accessible nor functional.
2919 *
2920 * Workaround:
2921 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2922 */
2923
2924 /*
2925 * Errata: USB host EHCI may stall when entering smart-standby mode
2926 * Id: i571
2927 *
2928 * Description:
2929 * When the USBHOST module is set to smart-standby mode, and when it is
2930 * ready to enter the standby state (i.e. all ports are suspended and
2931 * all attached devices are in suspend mode), then it can wrongly assert
2932 * the Mstandby signal too early while there are still some residual OCP
2933 * transactions ongoing. If this condition occurs, the internal state
2934 * machine may go to an undefined state and the USB link may be stuck
2935 * upon the next resume.
2936 *
2937 * Workaround:
2938 * Don't use smart standby; use only force standby,
2939 * hence HWMOD_SWSUP_MSTANDBY
2940 */
2941
2942 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2943 };
2944
2945 /*
2946 * 'usb_otg_hs' class
2947 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2948 */
2949
2950 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
2951 .rev_offs = 0x0400,
2952 .sysc_offs = 0x0404,
2953 .syss_offs = 0x0408,
2954 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2955 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2956 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2957 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2958 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2959 MSTANDBY_SMART),
2960 .sysc_fields = &omap_hwmod_sysc_type1,
2961 };
2962
2963 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
2964 .name = "usb_otg_hs",
2965 .sysc = &omap44xx_usb_otg_hs_sysc,
2966 };
2967
2968 /* usb_otg_hs */
2969 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
2970 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
2971 };
2972
2973 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
2974 .name = "usb_otg_hs",
2975 .class = &omap44xx_usb_otg_hs_hwmod_class,
2976 .clkdm_name = "l3_init_clkdm",
2977 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2978 .main_clk = "usb_otg_hs_ick",
2979 .prcm = {
2980 .omap4 = {
2981 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
2982 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
2983 .modulemode = MODULEMODE_HWCTRL,
2984 },
2985 },
2986 .opt_clks = usb_otg_hs_opt_clks,
2987 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
2988 };
2989
2990 /*
2991 * 'usb_tll_hs' class
2992 * usb_tll_hs module is the adapter on the usb_host_hs ports
2993 */
2994
2995 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
2996 .rev_offs = 0x0000,
2997 .sysc_offs = 0x0010,
2998 .syss_offs = 0x0014,
2999 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3000 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3001 SYSC_HAS_AUTOIDLE),
3002 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3003 .sysc_fields = &omap_hwmod_sysc_type1,
3004 };
3005
3006 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3007 .name = "usb_tll_hs",
3008 .sysc = &omap44xx_usb_tll_hs_sysc,
3009 };
3010
3011 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3012 .name = "usb_tll_hs",
3013 .class = &omap44xx_usb_tll_hs_hwmod_class,
3014 .clkdm_name = "l3_init_clkdm",
3015 .main_clk = "usb_tll_hs_ick",
3016 .prcm = {
3017 .omap4 = {
3018 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3019 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3020 .modulemode = MODULEMODE_HWCTRL,
3021 },
3022 },
3023 };
3024
3025 /*
3026 * 'wd_timer' class
3027 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3028 * overflow condition
3029 */
3030
3031 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3032 .rev_offs = 0x0000,
3033 .sysc_offs = 0x0010,
3034 .syss_offs = 0x0014,
3035 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3036 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3037 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3038 SIDLE_SMART_WKUP),
3039 .sysc_fields = &omap_hwmod_sysc_type1,
3040 };
3041
3042 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3043 .name = "wd_timer",
3044 .sysc = &omap44xx_wd_timer_sysc,
3045 .pre_shutdown = &omap2_wd_timer_disable,
3046 .reset = &omap2_wd_timer_reset,
3047 };
3048
3049 /* wd_timer2 */
3050 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3051 .name = "wd_timer2",
3052 .class = &omap44xx_wd_timer_hwmod_class,
3053 .clkdm_name = "l4_wkup_clkdm",
3054 .main_clk = "sys_32k_ck",
3055 .prcm = {
3056 .omap4 = {
3057 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3058 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3059 .modulemode = MODULEMODE_SWCTRL,
3060 },
3061 },
3062 };
3063
3064 /* wd_timer3 */
3065 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3066 .name = "wd_timer3",
3067 .class = &omap44xx_wd_timer_hwmod_class,
3068 .clkdm_name = "abe_clkdm",
3069 .main_clk = "sys_32k_ck",
3070 .prcm = {
3071 .omap4 = {
3072 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3073 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3074 .modulemode = MODULEMODE_SWCTRL,
3075 },
3076 },
3077 };
3078
3079
3080 /*
3081 * interfaces
3082 */
3083
3084 /* l3_main_1 -> dmm */
3085 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3086 .master = &omap44xx_l3_main_1_hwmod,
3087 .slave = &omap44xx_dmm_hwmod,
3088 .clk = "l3_div_ck",
3089 .user = OCP_USER_SDMA,
3090 };
3091
3092 /* mpu -> dmm */
3093 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3094 .master = &omap44xx_mpu_hwmod,
3095 .slave = &omap44xx_dmm_hwmod,
3096 .clk = "l3_div_ck",
3097 .user = OCP_USER_MPU,
3098 };
3099
3100 /* iva -> l3_instr */
3101 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3102 .master = &omap44xx_iva_hwmod,
3103 .slave = &omap44xx_l3_instr_hwmod,
3104 .clk = "l3_div_ck",
3105 .user = OCP_USER_MPU | OCP_USER_SDMA,
3106 };
3107
3108 /* l3_main_3 -> l3_instr */
3109 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3110 .master = &omap44xx_l3_main_3_hwmod,
3111 .slave = &omap44xx_l3_instr_hwmod,
3112 .clk = "l3_div_ck",
3113 .user = OCP_USER_MPU | OCP_USER_SDMA,
3114 };
3115
3116 /* ocp_wp_noc -> l3_instr */
3117 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3118 .master = &omap44xx_ocp_wp_noc_hwmod,
3119 .slave = &omap44xx_l3_instr_hwmod,
3120 .clk = "l3_div_ck",
3121 .user = OCP_USER_MPU | OCP_USER_SDMA,
3122 };
3123
3124 /* dsp -> l3_main_1 */
3125 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3126 .master = &omap44xx_dsp_hwmod,
3127 .slave = &omap44xx_l3_main_1_hwmod,
3128 .clk = "l3_div_ck",
3129 .user = OCP_USER_MPU | OCP_USER_SDMA,
3130 };
3131
3132 /* dss -> l3_main_1 */
3133 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3134 .master = &omap44xx_dss_hwmod,
3135 .slave = &omap44xx_l3_main_1_hwmod,
3136 .clk = "l3_div_ck",
3137 .user = OCP_USER_MPU | OCP_USER_SDMA,
3138 };
3139
3140 /* l3_main_2 -> l3_main_1 */
3141 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3142 .master = &omap44xx_l3_main_2_hwmod,
3143 .slave = &omap44xx_l3_main_1_hwmod,
3144 .clk = "l3_div_ck",
3145 .user = OCP_USER_MPU | OCP_USER_SDMA,
3146 };
3147
3148 /* l4_cfg -> l3_main_1 */
3149 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3150 .master = &omap44xx_l4_cfg_hwmod,
3151 .slave = &omap44xx_l3_main_1_hwmod,
3152 .clk = "l4_div_ck",
3153 .user = OCP_USER_MPU | OCP_USER_SDMA,
3154 };
3155
3156 /* mmc1 -> l3_main_1 */
3157 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3158 .master = &omap44xx_mmc1_hwmod,
3159 .slave = &omap44xx_l3_main_1_hwmod,
3160 .clk = "l3_div_ck",
3161 .user = OCP_USER_MPU | OCP_USER_SDMA,
3162 };
3163
3164 /* mmc2 -> l3_main_1 */
3165 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3166 .master = &omap44xx_mmc2_hwmod,
3167 .slave = &omap44xx_l3_main_1_hwmod,
3168 .clk = "l3_div_ck",
3169 .user = OCP_USER_MPU | OCP_USER_SDMA,
3170 };
3171
3172 /* mpu -> l3_main_1 */
3173 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3174 .master = &omap44xx_mpu_hwmod,
3175 .slave = &omap44xx_l3_main_1_hwmod,
3176 .clk = "l3_div_ck",
3177 .user = OCP_USER_MPU,
3178 };
3179
3180 /* debugss -> l3_main_2 */
3181 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3182 .master = &omap44xx_debugss_hwmod,
3183 .slave = &omap44xx_l3_main_2_hwmod,
3184 .clk = "dbgclk_mux_ck",
3185 .user = OCP_USER_MPU | OCP_USER_SDMA,
3186 };
3187
3188 /* dma_system -> l3_main_2 */
3189 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3190 .master = &omap44xx_dma_system_hwmod,
3191 .slave = &omap44xx_l3_main_2_hwmod,
3192 .clk = "l3_div_ck",
3193 .user = OCP_USER_MPU | OCP_USER_SDMA,
3194 };
3195
3196 /* fdif -> l3_main_2 */
3197 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3198 .master = &omap44xx_fdif_hwmod,
3199 .slave = &omap44xx_l3_main_2_hwmod,
3200 .clk = "l3_div_ck",
3201 .user = OCP_USER_MPU | OCP_USER_SDMA,
3202 };
3203
3204 /* gpu -> l3_main_2 */
3205 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3206 .master = &omap44xx_gpu_hwmod,
3207 .slave = &omap44xx_l3_main_2_hwmod,
3208 .clk = "l3_div_ck",
3209 .user = OCP_USER_MPU | OCP_USER_SDMA,
3210 };
3211
3212 /* hsi -> l3_main_2 */
3213 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3214 .master = &omap44xx_hsi_hwmod,
3215 .slave = &omap44xx_l3_main_2_hwmod,
3216 .clk = "l3_div_ck",
3217 .user = OCP_USER_MPU | OCP_USER_SDMA,
3218 };
3219
3220 /* ipu -> l3_main_2 */
3221 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3222 .master = &omap44xx_ipu_hwmod,
3223 .slave = &omap44xx_l3_main_2_hwmod,
3224 .clk = "l3_div_ck",
3225 .user = OCP_USER_MPU | OCP_USER_SDMA,
3226 };
3227
3228 /* iss -> l3_main_2 */
3229 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3230 .master = &omap44xx_iss_hwmod,
3231 .slave = &omap44xx_l3_main_2_hwmod,
3232 .clk = "l3_div_ck",
3233 .user = OCP_USER_MPU | OCP_USER_SDMA,
3234 };
3235
3236 /* iva -> l3_main_2 */
3237 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3238 .master = &omap44xx_iva_hwmod,
3239 .slave = &omap44xx_l3_main_2_hwmod,
3240 .clk = "l3_div_ck",
3241 .user = OCP_USER_MPU | OCP_USER_SDMA,
3242 };
3243
3244 /* l3_main_1 -> l3_main_2 */
3245 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3246 .master = &omap44xx_l3_main_1_hwmod,
3247 .slave = &omap44xx_l3_main_2_hwmod,
3248 .clk = "l3_div_ck",
3249 .user = OCP_USER_MPU,
3250 };
3251
3252 /* l4_cfg -> l3_main_2 */
3253 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3254 .master = &omap44xx_l4_cfg_hwmod,
3255 .slave = &omap44xx_l3_main_2_hwmod,
3256 .clk = "l4_div_ck",
3257 .user = OCP_USER_MPU | OCP_USER_SDMA,
3258 };
3259
3260 /* usb_host_fs -> l3_main_2 */
3261 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3262 .master = &omap44xx_usb_host_fs_hwmod,
3263 .slave = &omap44xx_l3_main_2_hwmod,
3264 .clk = "l3_div_ck",
3265 .user = OCP_USER_MPU | OCP_USER_SDMA,
3266 };
3267
3268 /* usb_host_hs -> l3_main_2 */
3269 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3270 .master = &omap44xx_usb_host_hs_hwmod,
3271 .slave = &omap44xx_l3_main_2_hwmod,
3272 .clk = "l3_div_ck",
3273 .user = OCP_USER_MPU | OCP_USER_SDMA,
3274 };
3275
3276 /* usb_otg_hs -> l3_main_2 */
3277 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3278 .master = &omap44xx_usb_otg_hs_hwmod,
3279 .slave = &omap44xx_l3_main_2_hwmod,
3280 .clk = "l3_div_ck",
3281 .user = OCP_USER_MPU | OCP_USER_SDMA,
3282 };
3283
3284 /* l3_main_1 -> l3_main_3 */
3285 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3286 .master = &omap44xx_l3_main_1_hwmod,
3287 .slave = &omap44xx_l3_main_3_hwmod,
3288 .clk = "l3_div_ck",
3289 .user = OCP_USER_MPU,
3290 };
3291
3292 /* l3_main_2 -> l3_main_3 */
3293 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3294 .master = &omap44xx_l3_main_2_hwmod,
3295 .slave = &omap44xx_l3_main_3_hwmod,
3296 .clk = "l3_div_ck",
3297 .user = OCP_USER_MPU | OCP_USER_SDMA,
3298 };
3299
3300 /* l4_cfg -> l3_main_3 */
3301 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3302 .master = &omap44xx_l4_cfg_hwmod,
3303 .slave = &omap44xx_l3_main_3_hwmod,
3304 .clk = "l4_div_ck",
3305 .user = OCP_USER_MPU | OCP_USER_SDMA,
3306 };
3307
3308 /* aess -> l4_abe */
3309 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3310 .master = &omap44xx_aess_hwmod,
3311 .slave = &omap44xx_l4_abe_hwmod,
3312 .clk = "ocp_abe_iclk",
3313 .user = OCP_USER_MPU | OCP_USER_SDMA,
3314 };
3315
3316 /* dsp -> l4_abe */
3317 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3318 .master = &omap44xx_dsp_hwmod,
3319 .slave = &omap44xx_l4_abe_hwmod,
3320 .clk = "ocp_abe_iclk",
3321 .user = OCP_USER_MPU | OCP_USER_SDMA,
3322 };
3323
3324 /* l3_main_1 -> l4_abe */
3325 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3326 .master = &omap44xx_l3_main_1_hwmod,
3327 .slave = &omap44xx_l4_abe_hwmod,
3328 .clk = "l3_div_ck",
3329 .user = OCP_USER_MPU | OCP_USER_SDMA,
3330 };
3331
3332 /* mpu -> l4_abe */
3333 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3334 .master = &omap44xx_mpu_hwmod,
3335 .slave = &omap44xx_l4_abe_hwmod,
3336 .clk = "ocp_abe_iclk",
3337 .user = OCP_USER_MPU | OCP_USER_SDMA,
3338 };
3339
3340 /* l3_main_1 -> l4_cfg */
3341 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3342 .master = &omap44xx_l3_main_1_hwmod,
3343 .slave = &omap44xx_l4_cfg_hwmod,
3344 .clk = "l3_div_ck",
3345 .user = OCP_USER_MPU | OCP_USER_SDMA,
3346 };
3347
3348 /* l3_main_2 -> l4_per */
3349 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3350 .master = &omap44xx_l3_main_2_hwmod,
3351 .slave = &omap44xx_l4_per_hwmod,
3352 .clk = "l3_div_ck",
3353 .user = OCP_USER_MPU | OCP_USER_SDMA,
3354 };
3355
3356 /* l4_cfg -> l4_wkup */
3357 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3358 .master = &omap44xx_l4_cfg_hwmod,
3359 .slave = &omap44xx_l4_wkup_hwmod,
3360 .clk = "l4_div_ck",
3361 .user = OCP_USER_MPU | OCP_USER_SDMA,
3362 };
3363
3364 /* mpu -> mpu_private */
3365 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3366 .master = &omap44xx_mpu_hwmod,
3367 .slave = &omap44xx_mpu_private_hwmod,
3368 .clk = "l3_div_ck",
3369 .user = OCP_USER_MPU | OCP_USER_SDMA,
3370 };
3371
3372 /* l4_cfg -> ocp_wp_noc */
3373 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3374 .master = &omap44xx_l4_cfg_hwmod,
3375 .slave = &omap44xx_ocp_wp_noc_hwmod,
3376 .clk = "l4_div_ck",
3377 .user = OCP_USER_MPU | OCP_USER_SDMA,
3378 };
3379
3380 /* l4_abe -> aess */
3381 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3382 .master = &omap44xx_l4_abe_hwmod,
3383 .slave = &omap44xx_aess_hwmod,
3384 .clk = "ocp_abe_iclk",
3385 .user = OCP_USER_MPU,
3386 };
3387
3388 /* l4_abe -> aess (dma) */
3389 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3390 .master = &omap44xx_l4_abe_hwmod,
3391 .slave = &omap44xx_aess_hwmod,
3392 .clk = "ocp_abe_iclk",
3393 .user = OCP_USER_SDMA,
3394 };
3395
3396 /* l3_main_2 -> c2c */
3397 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3398 .master = &omap44xx_l3_main_2_hwmod,
3399 .slave = &omap44xx_c2c_hwmod,
3400 .clk = "l3_div_ck",
3401 .user = OCP_USER_MPU | OCP_USER_SDMA,
3402 };
3403
3404 /* l4_wkup -> counter_32k */
3405 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3406 .master = &omap44xx_l4_wkup_hwmod,
3407 .slave = &omap44xx_counter_32k_hwmod,
3408 .clk = "l4_wkup_clk_mux_ck",
3409 .user = OCP_USER_MPU | OCP_USER_SDMA,
3410 };
3411
3412 /* l4_cfg -> ctrl_module_core */
3413 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3414 .master = &omap44xx_l4_cfg_hwmod,
3415 .slave = &omap44xx_ctrl_module_core_hwmod,
3416 .clk = "l4_div_ck",
3417 .user = OCP_USER_MPU | OCP_USER_SDMA,
3418 };
3419
3420 /* l4_cfg -> ctrl_module_pad_core */
3421 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3422 .master = &omap44xx_l4_cfg_hwmod,
3423 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
3424 .clk = "l4_div_ck",
3425 .user = OCP_USER_MPU | OCP_USER_SDMA,
3426 };
3427
3428 /* l4_wkup -> ctrl_module_wkup */
3429 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3430 .master = &omap44xx_l4_wkup_hwmod,
3431 .slave = &omap44xx_ctrl_module_wkup_hwmod,
3432 .clk = "l4_wkup_clk_mux_ck",
3433 .user = OCP_USER_MPU | OCP_USER_SDMA,
3434 };
3435
3436 /* l4_wkup -> ctrl_module_pad_wkup */
3437 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3438 .master = &omap44xx_l4_wkup_hwmod,
3439 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
3440 .clk = "l4_wkup_clk_mux_ck",
3441 .user = OCP_USER_MPU | OCP_USER_SDMA,
3442 };
3443
3444 /* l3_instr -> debugss */
3445 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3446 .master = &omap44xx_l3_instr_hwmod,
3447 .slave = &omap44xx_debugss_hwmod,
3448 .clk = "l3_div_ck",
3449 .user = OCP_USER_MPU | OCP_USER_SDMA,
3450 };
3451
3452 /* l4_cfg -> dma_system */
3453 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3454 .master = &omap44xx_l4_cfg_hwmod,
3455 .slave = &omap44xx_dma_system_hwmod,
3456 .clk = "l4_div_ck",
3457 .user = OCP_USER_MPU | OCP_USER_SDMA,
3458 };
3459
3460 /* l4_abe -> dmic */
3461 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3462 .master = &omap44xx_l4_abe_hwmod,
3463 .slave = &omap44xx_dmic_hwmod,
3464 .clk = "ocp_abe_iclk",
3465 .user = OCP_USER_MPU | OCP_USER_SDMA,
3466 };
3467
3468 /* dsp -> iva */
3469 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3470 .master = &omap44xx_dsp_hwmod,
3471 .slave = &omap44xx_iva_hwmod,
3472 .clk = "dpll_iva_m5x2_ck",
3473 .user = OCP_USER_DSP,
3474 };
3475
3476 /* dsp -> sl2if */
3477 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3478 .master = &omap44xx_dsp_hwmod,
3479 .slave = &omap44xx_sl2if_hwmod,
3480 .clk = "dpll_iva_m5x2_ck",
3481 .user = OCP_USER_DSP,
3482 };
3483
3484 /* l4_cfg -> dsp */
3485 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3486 .master = &omap44xx_l4_cfg_hwmod,
3487 .slave = &omap44xx_dsp_hwmod,
3488 .clk = "l4_div_ck",
3489 .user = OCP_USER_MPU | OCP_USER_SDMA,
3490 };
3491
3492 /* l3_main_2 -> dss */
3493 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3494 .master = &omap44xx_l3_main_2_hwmod,
3495 .slave = &omap44xx_dss_hwmod,
3496 .clk = "l3_div_ck",
3497 .user = OCP_USER_SDMA,
3498 };
3499
3500 /* l4_per -> dss */
3501 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3502 .master = &omap44xx_l4_per_hwmod,
3503 .slave = &omap44xx_dss_hwmod,
3504 .clk = "l4_div_ck",
3505 .user = OCP_USER_MPU,
3506 };
3507
3508 /* l3_main_2 -> dss_dispc */
3509 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3510 .master = &omap44xx_l3_main_2_hwmod,
3511 .slave = &omap44xx_dss_dispc_hwmod,
3512 .clk = "l3_div_ck",
3513 .user = OCP_USER_SDMA,
3514 };
3515
3516 /* l4_per -> dss_dispc */
3517 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3518 .master = &omap44xx_l4_per_hwmod,
3519 .slave = &omap44xx_dss_dispc_hwmod,
3520 .clk = "l4_div_ck",
3521 .user = OCP_USER_MPU,
3522 };
3523
3524 /* l3_main_2 -> dss_dsi1 */
3525 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3526 .master = &omap44xx_l3_main_2_hwmod,
3527 .slave = &omap44xx_dss_dsi1_hwmod,
3528 .clk = "l3_div_ck",
3529 .user = OCP_USER_SDMA,
3530 };
3531
3532 /* l4_per -> dss_dsi1 */
3533 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3534 .master = &omap44xx_l4_per_hwmod,
3535 .slave = &omap44xx_dss_dsi1_hwmod,
3536 .clk = "l4_div_ck",
3537 .user = OCP_USER_MPU,
3538 };
3539
3540 /* l3_main_2 -> dss_dsi2 */
3541 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3542 .master = &omap44xx_l3_main_2_hwmod,
3543 .slave = &omap44xx_dss_dsi2_hwmod,
3544 .clk = "l3_div_ck",
3545 .user = OCP_USER_SDMA,
3546 };
3547
3548 /* l4_per -> dss_dsi2 */
3549 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3550 .master = &omap44xx_l4_per_hwmod,
3551 .slave = &omap44xx_dss_dsi2_hwmod,
3552 .clk = "l4_div_ck",
3553 .user = OCP_USER_MPU,
3554 };
3555
3556 /* l3_main_2 -> dss_hdmi */
3557 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3558 .master = &omap44xx_l3_main_2_hwmod,
3559 .slave = &omap44xx_dss_hdmi_hwmod,
3560 .clk = "l3_div_ck",
3561 .user = OCP_USER_SDMA,
3562 };
3563
3564 /* l4_per -> dss_hdmi */
3565 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3566 .master = &omap44xx_l4_per_hwmod,
3567 .slave = &omap44xx_dss_hdmi_hwmod,
3568 .clk = "l4_div_ck",
3569 .user = OCP_USER_MPU,
3570 };
3571
3572 /* l3_main_2 -> dss_rfbi */
3573 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3574 .master = &omap44xx_l3_main_2_hwmod,
3575 .slave = &omap44xx_dss_rfbi_hwmod,
3576 .clk = "l3_div_ck",
3577 .user = OCP_USER_SDMA,
3578 };
3579
3580 /* l4_per -> dss_rfbi */
3581 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3582 .master = &omap44xx_l4_per_hwmod,
3583 .slave = &omap44xx_dss_rfbi_hwmod,
3584 .clk = "l4_div_ck",
3585 .user = OCP_USER_MPU,
3586 };
3587
3588 /* l3_main_2 -> dss_venc */
3589 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3590 .master = &omap44xx_l3_main_2_hwmod,
3591 .slave = &omap44xx_dss_venc_hwmod,
3592 .clk = "l3_div_ck",
3593 .user = OCP_USER_SDMA,
3594 };
3595
3596 /* l4_per -> dss_venc */
3597 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3598 .master = &omap44xx_l4_per_hwmod,
3599 .slave = &omap44xx_dss_venc_hwmod,
3600 .clk = "l4_div_ck",
3601 .user = OCP_USER_MPU,
3602 };
3603
3604 /* l3_main_2 -> sham */
3605 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
3606 .master = &omap44xx_l3_main_2_hwmod,
3607 .slave = &omap44xx_sha0_hwmod,
3608 .clk = "l3_div_ck",
3609 .user = OCP_USER_MPU | OCP_USER_SDMA,
3610 };
3611
3612 /* l4_per -> elm */
3613 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3614 .master = &omap44xx_l4_per_hwmod,
3615 .slave = &omap44xx_elm_hwmod,
3616 .clk = "l4_div_ck",
3617 .user = OCP_USER_MPU | OCP_USER_SDMA,
3618 };
3619
3620 /* l4_cfg -> fdif */
3621 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3622 .master = &omap44xx_l4_cfg_hwmod,
3623 .slave = &omap44xx_fdif_hwmod,
3624 .clk = "l4_div_ck",
3625 .user = OCP_USER_MPU | OCP_USER_SDMA,
3626 };
3627
3628 /* l4_wkup -> gpio1 */
3629 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3630 .master = &omap44xx_l4_wkup_hwmod,
3631 .slave = &omap44xx_gpio1_hwmod,
3632 .clk = "l4_wkup_clk_mux_ck",
3633 .user = OCP_USER_MPU | OCP_USER_SDMA,
3634 };
3635
3636 /* l4_per -> gpio2 */
3637 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3638 .master = &omap44xx_l4_per_hwmod,
3639 .slave = &omap44xx_gpio2_hwmod,
3640 .clk = "l4_div_ck",
3641 .user = OCP_USER_MPU | OCP_USER_SDMA,
3642 };
3643
3644 /* l4_per -> gpio3 */
3645 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3646 .master = &omap44xx_l4_per_hwmod,
3647 .slave = &omap44xx_gpio3_hwmod,
3648 .clk = "l4_div_ck",
3649 .user = OCP_USER_MPU | OCP_USER_SDMA,
3650 };
3651
3652 /* l4_per -> gpio4 */
3653 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3654 .master = &omap44xx_l4_per_hwmod,
3655 .slave = &omap44xx_gpio4_hwmod,
3656 .clk = "l4_div_ck",
3657 .user = OCP_USER_MPU | OCP_USER_SDMA,
3658 };
3659
3660 /* l4_per -> gpio5 */
3661 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3662 .master = &omap44xx_l4_per_hwmod,
3663 .slave = &omap44xx_gpio5_hwmod,
3664 .clk = "l4_div_ck",
3665 .user = OCP_USER_MPU | OCP_USER_SDMA,
3666 };
3667
3668 /* l4_per -> gpio6 */
3669 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3670 .master = &omap44xx_l4_per_hwmod,
3671 .slave = &omap44xx_gpio6_hwmod,
3672 .clk = "l4_div_ck",
3673 .user = OCP_USER_MPU | OCP_USER_SDMA,
3674 };
3675
3676 /* l3_main_2 -> gpmc */
3677 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
3678 .master = &omap44xx_l3_main_2_hwmod,
3679 .slave = &omap44xx_gpmc_hwmod,
3680 .clk = "l3_div_ck",
3681 .user = OCP_USER_MPU | OCP_USER_SDMA,
3682 };
3683
3684 /* l3_main_2 -> gpu */
3685 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
3686 .master = &omap44xx_l3_main_2_hwmod,
3687 .slave = &omap44xx_gpu_hwmod,
3688 .clk = "l3_div_ck",
3689 .user = OCP_USER_MPU | OCP_USER_SDMA,
3690 };
3691
3692 /* l4_per -> hdq1w */
3693 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
3694 .master = &omap44xx_l4_per_hwmod,
3695 .slave = &omap44xx_hdq1w_hwmod,
3696 .clk = "l4_div_ck",
3697 .user = OCP_USER_MPU | OCP_USER_SDMA,
3698 };
3699
3700 /* l4_cfg -> hsi */
3701 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
3702 .master = &omap44xx_l4_cfg_hwmod,
3703 .slave = &omap44xx_hsi_hwmod,
3704 .clk = "l4_div_ck",
3705 .user = OCP_USER_MPU | OCP_USER_SDMA,
3706 };
3707
3708 /* l4_per -> i2c1 */
3709 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
3710 .master = &omap44xx_l4_per_hwmod,
3711 .slave = &omap44xx_i2c1_hwmod,
3712 .clk = "l4_div_ck",
3713 .user = OCP_USER_MPU | OCP_USER_SDMA,
3714 };
3715
3716 /* l4_per -> i2c2 */
3717 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
3718 .master = &omap44xx_l4_per_hwmod,
3719 .slave = &omap44xx_i2c2_hwmod,
3720 .clk = "l4_div_ck",
3721 .user = OCP_USER_MPU | OCP_USER_SDMA,
3722 };
3723
3724 /* l4_per -> i2c3 */
3725 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
3726 .master = &omap44xx_l4_per_hwmod,
3727 .slave = &omap44xx_i2c3_hwmod,
3728 .clk = "l4_div_ck",
3729 .user = OCP_USER_MPU | OCP_USER_SDMA,
3730 };
3731
3732 /* l4_per -> i2c4 */
3733 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
3734 .master = &omap44xx_l4_per_hwmod,
3735 .slave = &omap44xx_i2c4_hwmod,
3736 .clk = "l4_div_ck",
3737 .user = OCP_USER_MPU | OCP_USER_SDMA,
3738 };
3739
3740 /* l3_main_2 -> ipu */
3741 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
3742 .master = &omap44xx_l3_main_2_hwmod,
3743 .slave = &omap44xx_ipu_hwmod,
3744 .clk = "l3_div_ck",
3745 .user = OCP_USER_MPU | OCP_USER_SDMA,
3746 };
3747
3748 /* l3_main_2 -> iss */
3749 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
3750 .master = &omap44xx_l3_main_2_hwmod,
3751 .slave = &omap44xx_iss_hwmod,
3752 .clk = "l3_div_ck",
3753 .user = OCP_USER_MPU | OCP_USER_SDMA,
3754 };
3755
3756 /* iva -> sl2if */
3757 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
3758 .master = &omap44xx_iva_hwmod,
3759 .slave = &omap44xx_sl2if_hwmod,
3760 .clk = "dpll_iva_m5x2_ck",
3761 .user = OCP_USER_IVA,
3762 };
3763
3764 /* l3_main_2 -> iva */
3765 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
3766 .master = &omap44xx_l3_main_2_hwmod,
3767 .slave = &omap44xx_iva_hwmod,
3768 .clk = "l3_div_ck",
3769 .user = OCP_USER_MPU,
3770 };
3771
3772 /* l4_wkup -> kbd */
3773 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
3774 .master = &omap44xx_l4_wkup_hwmod,
3775 .slave = &omap44xx_kbd_hwmod,
3776 .clk = "l4_wkup_clk_mux_ck",
3777 .user = OCP_USER_MPU | OCP_USER_SDMA,
3778 };
3779
3780 /* l4_cfg -> mailbox */
3781 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
3782 .master = &omap44xx_l4_cfg_hwmod,
3783 .slave = &omap44xx_mailbox_hwmod,
3784 .clk = "l4_div_ck",
3785 .user = OCP_USER_MPU | OCP_USER_SDMA,
3786 };
3787
3788 /* l4_abe -> mcasp */
3789 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
3790 .master = &omap44xx_l4_abe_hwmod,
3791 .slave = &omap44xx_mcasp_hwmod,
3792 .clk = "ocp_abe_iclk",
3793 .user = OCP_USER_MPU,
3794 };
3795
3796 /* l4_abe -> mcasp (dma) */
3797 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
3798 .master = &omap44xx_l4_abe_hwmod,
3799 .slave = &omap44xx_mcasp_hwmod,
3800 .clk = "ocp_abe_iclk",
3801 .user = OCP_USER_SDMA,
3802 };
3803
3804 /* l4_abe -> mcbsp1 */
3805 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
3806 .master = &omap44xx_l4_abe_hwmod,
3807 .slave = &omap44xx_mcbsp1_hwmod,
3808 .clk = "ocp_abe_iclk",
3809 .user = OCP_USER_MPU | OCP_USER_SDMA,
3810 };
3811
3812 /* l4_abe -> mcbsp2 */
3813 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3814 .master = &omap44xx_l4_abe_hwmod,
3815 .slave = &omap44xx_mcbsp2_hwmod,
3816 .clk = "ocp_abe_iclk",
3817 .user = OCP_USER_MPU | OCP_USER_SDMA,
3818 };
3819
3820 /* l4_abe -> mcbsp3 */
3821 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3822 .master = &omap44xx_l4_abe_hwmod,
3823 .slave = &omap44xx_mcbsp3_hwmod,
3824 .clk = "ocp_abe_iclk",
3825 .user = OCP_USER_MPU | OCP_USER_SDMA,
3826 };
3827
3828 /* l4_per -> mcbsp4 */
3829 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3830 .master = &omap44xx_l4_per_hwmod,
3831 .slave = &omap44xx_mcbsp4_hwmod,
3832 .clk = "l4_div_ck",
3833 .user = OCP_USER_MPU | OCP_USER_SDMA,
3834 };
3835
3836 /* l4_abe -> mcpdm */
3837 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3838 .master = &omap44xx_l4_abe_hwmod,
3839 .slave = &omap44xx_mcpdm_hwmod,
3840 .clk = "ocp_abe_iclk",
3841 .user = OCP_USER_MPU | OCP_USER_SDMA,
3842 };
3843
3844 /* l4_per -> mcspi1 */
3845 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3846 .master = &omap44xx_l4_per_hwmod,
3847 .slave = &omap44xx_mcspi1_hwmod,
3848 .clk = "l4_div_ck",
3849 .user = OCP_USER_MPU | OCP_USER_SDMA,
3850 };
3851
3852 /* l4_per -> mcspi2 */
3853 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3854 .master = &omap44xx_l4_per_hwmod,
3855 .slave = &omap44xx_mcspi2_hwmod,
3856 .clk = "l4_div_ck",
3857 .user = OCP_USER_MPU | OCP_USER_SDMA,
3858 };
3859
3860 /* l4_per -> mcspi3 */
3861 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3862 .master = &omap44xx_l4_per_hwmod,
3863 .slave = &omap44xx_mcspi3_hwmod,
3864 .clk = "l4_div_ck",
3865 .user = OCP_USER_MPU | OCP_USER_SDMA,
3866 };
3867
3868 /* l4_per -> mcspi4 */
3869 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3870 .master = &omap44xx_l4_per_hwmod,
3871 .slave = &omap44xx_mcspi4_hwmod,
3872 .clk = "l4_div_ck",
3873 .user = OCP_USER_MPU | OCP_USER_SDMA,
3874 };
3875
3876 /* l4_per -> mmc1 */
3877 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3878 .master = &omap44xx_l4_per_hwmod,
3879 .slave = &omap44xx_mmc1_hwmod,
3880 .clk = "l4_div_ck",
3881 .user = OCP_USER_MPU | OCP_USER_SDMA,
3882 };
3883
3884 /* l4_per -> mmc2 */
3885 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3886 .master = &omap44xx_l4_per_hwmod,
3887 .slave = &omap44xx_mmc2_hwmod,
3888 .clk = "l4_div_ck",
3889 .user = OCP_USER_MPU | OCP_USER_SDMA,
3890 };
3891
3892 /* l4_per -> mmc3 */
3893 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3894 .master = &omap44xx_l4_per_hwmod,
3895 .slave = &omap44xx_mmc3_hwmod,
3896 .clk = "l4_div_ck",
3897 .user = OCP_USER_MPU | OCP_USER_SDMA,
3898 };
3899
3900 /* l4_per -> mmc4 */
3901 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3902 .master = &omap44xx_l4_per_hwmod,
3903 .slave = &omap44xx_mmc4_hwmod,
3904 .clk = "l4_div_ck",
3905 .user = OCP_USER_MPU | OCP_USER_SDMA,
3906 };
3907
3908 /* l4_per -> mmc5 */
3909 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3910 .master = &omap44xx_l4_per_hwmod,
3911 .slave = &omap44xx_mmc5_hwmod,
3912 .clk = "l4_div_ck",
3913 .user = OCP_USER_MPU | OCP_USER_SDMA,
3914 };
3915
3916 /* l3_main_2 -> ocmc_ram */
3917 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
3918 .master = &omap44xx_l3_main_2_hwmod,
3919 .slave = &omap44xx_ocmc_ram_hwmod,
3920 .clk = "l3_div_ck",
3921 .user = OCP_USER_MPU | OCP_USER_SDMA,
3922 };
3923
3924 /* l4_cfg -> ocp2scp_usb_phy */
3925 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
3926 .master = &omap44xx_l4_cfg_hwmod,
3927 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
3928 .clk = "l4_div_ck",
3929 .user = OCP_USER_MPU | OCP_USER_SDMA,
3930 };
3931
3932 /* mpu_private -> prcm_mpu */
3933 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
3934 .master = &omap44xx_mpu_private_hwmod,
3935 .slave = &omap44xx_prcm_mpu_hwmod,
3936 .clk = "l3_div_ck",
3937 .user = OCP_USER_MPU | OCP_USER_SDMA,
3938 };
3939
3940 /* l4_wkup -> cm_core_aon */
3941 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
3942 .master = &omap44xx_l4_wkup_hwmod,
3943 .slave = &omap44xx_cm_core_aon_hwmod,
3944 .clk = "l4_wkup_clk_mux_ck",
3945 .user = OCP_USER_MPU | OCP_USER_SDMA,
3946 };
3947
3948 /* l4_cfg -> cm_core */
3949 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
3950 .master = &omap44xx_l4_cfg_hwmod,
3951 .slave = &omap44xx_cm_core_hwmod,
3952 .clk = "l4_div_ck",
3953 .user = OCP_USER_MPU | OCP_USER_SDMA,
3954 };
3955
3956 /* l4_wkup -> prm */
3957 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
3958 .master = &omap44xx_l4_wkup_hwmod,
3959 .slave = &omap44xx_prm_hwmod,
3960 .clk = "l4_wkup_clk_mux_ck",
3961 .user = OCP_USER_MPU | OCP_USER_SDMA,
3962 };
3963
3964 /* l4_wkup -> scrm */
3965 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
3966 .master = &omap44xx_l4_wkup_hwmod,
3967 .slave = &omap44xx_scrm_hwmod,
3968 .clk = "l4_wkup_clk_mux_ck",
3969 .user = OCP_USER_MPU | OCP_USER_SDMA,
3970 };
3971
3972 /* l3_main_2 -> sl2if */
3973 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
3974 .master = &omap44xx_l3_main_2_hwmod,
3975 .slave = &omap44xx_sl2if_hwmod,
3976 .clk = "l3_div_ck",
3977 .user = OCP_USER_MPU | OCP_USER_SDMA,
3978 };
3979
3980 /* l4_abe -> slimbus1 */
3981 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
3982 .master = &omap44xx_l4_abe_hwmod,
3983 .slave = &omap44xx_slimbus1_hwmod,
3984 .clk = "ocp_abe_iclk",
3985 .user = OCP_USER_MPU,
3986 };
3987
3988 /* l4_abe -> slimbus1 (dma) */
3989 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
3990 .master = &omap44xx_l4_abe_hwmod,
3991 .slave = &omap44xx_slimbus1_hwmod,
3992 .clk = "ocp_abe_iclk",
3993 .user = OCP_USER_SDMA,
3994 };
3995
3996 /* l4_per -> slimbus2 */
3997 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
3998 .master = &omap44xx_l4_per_hwmod,
3999 .slave = &omap44xx_slimbus2_hwmod,
4000 .clk = "l4_div_ck",
4001 .user = OCP_USER_MPU | OCP_USER_SDMA,
4002 };
4003
4004 /* l4_cfg -> smartreflex_core */
4005 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4006 .master = &omap44xx_l4_cfg_hwmod,
4007 .slave = &omap44xx_smartreflex_core_hwmod,
4008 .clk = "l4_div_ck",
4009 .user = OCP_USER_MPU | OCP_USER_SDMA,
4010 };
4011
4012 /* l4_cfg -> smartreflex_iva */
4013 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4014 .master = &omap44xx_l4_cfg_hwmod,
4015 .slave = &omap44xx_smartreflex_iva_hwmod,
4016 .clk = "l4_div_ck",
4017 .user = OCP_USER_MPU | OCP_USER_SDMA,
4018 };
4019
4020 /* l4_cfg -> smartreflex_mpu */
4021 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4022 .master = &omap44xx_l4_cfg_hwmod,
4023 .slave = &omap44xx_smartreflex_mpu_hwmod,
4024 .clk = "l4_div_ck",
4025 .user = OCP_USER_MPU | OCP_USER_SDMA,
4026 };
4027
4028 /* l4_cfg -> spinlock */
4029 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4030 .master = &omap44xx_l4_cfg_hwmod,
4031 .slave = &omap44xx_spinlock_hwmod,
4032 .clk = "l4_div_ck",
4033 .user = OCP_USER_MPU | OCP_USER_SDMA,
4034 };
4035
4036 /* l4_wkup -> timer1 */
4037 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4038 .master = &omap44xx_l4_wkup_hwmod,
4039 .slave = &omap44xx_timer1_hwmod,
4040 .clk = "l4_wkup_clk_mux_ck",
4041 .user = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4043
4044 /* l4_per -> timer2 */
4045 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4046 .master = &omap44xx_l4_per_hwmod,
4047 .slave = &omap44xx_timer2_hwmod,
4048 .clk = "l4_div_ck",
4049 .user = OCP_USER_MPU | OCP_USER_SDMA,
4050 };
4051
4052 /* l4_per -> timer3 */
4053 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4054 .master = &omap44xx_l4_per_hwmod,
4055 .slave = &omap44xx_timer3_hwmod,
4056 .clk = "l4_div_ck",
4057 .user = OCP_USER_MPU | OCP_USER_SDMA,
4058 };
4059
4060 /* l4_per -> timer4 */
4061 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4062 .master = &omap44xx_l4_per_hwmod,
4063 .slave = &omap44xx_timer4_hwmod,
4064 .clk = "l4_div_ck",
4065 .user = OCP_USER_MPU | OCP_USER_SDMA,
4066 };
4067
4068 /* l4_abe -> timer5 */
4069 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4070 .master = &omap44xx_l4_abe_hwmod,
4071 .slave = &omap44xx_timer5_hwmod,
4072 .clk = "ocp_abe_iclk",
4073 .user = OCP_USER_MPU | OCP_USER_SDMA,
4074 };
4075
4076 /* l4_abe -> timer6 */
4077 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4078 .master = &omap44xx_l4_abe_hwmod,
4079 .slave = &omap44xx_timer6_hwmod,
4080 .clk = "ocp_abe_iclk",
4081 .user = OCP_USER_MPU | OCP_USER_SDMA,
4082 };
4083
4084 /* l4_abe -> timer7 */
4085 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4086 .master = &omap44xx_l4_abe_hwmod,
4087 .slave = &omap44xx_timer7_hwmod,
4088 .clk = "ocp_abe_iclk",
4089 .user = OCP_USER_MPU | OCP_USER_SDMA,
4090 };
4091
4092 /* l4_abe -> timer8 */
4093 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4094 .master = &omap44xx_l4_abe_hwmod,
4095 .slave = &omap44xx_timer8_hwmod,
4096 .clk = "ocp_abe_iclk",
4097 .user = OCP_USER_MPU | OCP_USER_SDMA,
4098 };
4099
4100 /* l4_per -> timer9 */
4101 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4102 .master = &omap44xx_l4_per_hwmod,
4103 .slave = &omap44xx_timer9_hwmod,
4104 .clk = "l4_div_ck",
4105 .user = OCP_USER_MPU | OCP_USER_SDMA,
4106 };
4107
4108 /* l4_per -> timer10 */
4109 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4110 .master = &omap44xx_l4_per_hwmod,
4111 .slave = &omap44xx_timer10_hwmod,
4112 .clk = "l4_div_ck",
4113 .user = OCP_USER_MPU | OCP_USER_SDMA,
4114 };
4115
4116 /* l4_per -> timer11 */
4117 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4118 .master = &omap44xx_l4_per_hwmod,
4119 .slave = &omap44xx_timer11_hwmod,
4120 .clk = "l4_div_ck",
4121 .user = OCP_USER_MPU | OCP_USER_SDMA,
4122 };
4123
4124 /* l4_per -> uart1 */
4125 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4126 .master = &omap44xx_l4_per_hwmod,
4127 .slave = &omap44xx_uart1_hwmod,
4128 .clk = "l4_div_ck",
4129 .user = OCP_USER_MPU | OCP_USER_SDMA,
4130 };
4131
4132 /* l4_per -> uart2 */
4133 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4134 .master = &omap44xx_l4_per_hwmod,
4135 .slave = &omap44xx_uart2_hwmod,
4136 .clk = "l4_div_ck",
4137 .user = OCP_USER_MPU | OCP_USER_SDMA,
4138 };
4139
4140 /* l4_per -> uart3 */
4141 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4142 .master = &omap44xx_l4_per_hwmod,
4143 .slave = &omap44xx_uart3_hwmod,
4144 .clk = "l4_div_ck",
4145 .user = OCP_USER_MPU | OCP_USER_SDMA,
4146 };
4147
4148 /* l4_per -> uart4 */
4149 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4150 .master = &omap44xx_l4_per_hwmod,
4151 .slave = &omap44xx_uart4_hwmod,
4152 .clk = "l4_div_ck",
4153 .user = OCP_USER_MPU | OCP_USER_SDMA,
4154 };
4155
4156 /* l4_cfg -> usb_host_fs */
4157 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4158 .master = &omap44xx_l4_cfg_hwmod,
4159 .slave = &omap44xx_usb_host_fs_hwmod,
4160 .clk = "l4_div_ck",
4161 .user = OCP_USER_MPU | OCP_USER_SDMA,
4162 };
4163
4164 /* l4_cfg -> usb_host_hs */
4165 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4166 .master = &omap44xx_l4_cfg_hwmod,
4167 .slave = &omap44xx_usb_host_hs_hwmod,
4168 .clk = "l4_div_ck",
4169 .user = OCP_USER_MPU | OCP_USER_SDMA,
4170 };
4171
4172 /* l4_cfg -> usb_otg_hs */
4173 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4174 .master = &omap44xx_l4_cfg_hwmod,
4175 .slave = &omap44xx_usb_otg_hs_hwmod,
4176 .clk = "l4_div_ck",
4177 .user = OCP_USER_MPU | OCP_USER_SDMA,
4178 };
4179
4180 /* l4_cfg -> usb_tll_hs */
4181 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4182 .master = &omap44xx_l4_cfg_hwmod,
4183 .slave = &omap44xx_usb_tll_hs_hwmod,
4184 .clk = "l4_div_ck",
4185 .user = OCP_USER_MPU | OCP_USER_SDMA,
4186 };
4187
4188 /* l4_wkup -> wd_timer2 */
4189 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4190 .master = &omap44xx_l4_wkup_hwmod,
4191 .slave = &omap44xx_wd_timer2_hwmod,
4192 .clk = "l4_wkup_clk_mux_ck",
4193 .user = OCP_USER_MPU | OCP_USER_SDMA,
4194 };
4195
4196 /* l4_abe -> wd_timer3 */
4197 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4198 .master = &omap44xx_l4_abe_hwmod,
4199 .slave = &omap44xx_wd_timer3_hwmod,
4200 .clk = "ocp_abe_iclk",
4201 .user = OCP_USER_MPU,
4202 };
4203
4204 /* l4_abe -> wd_timer3 (dma) */
4205 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4206 .master = &omap44xx_l4_abe_hwmod,
4207 .slave = &omap44xx_wd_timer3_hwmod,
4208 .clk = "ocp_abe_iclk",
4209 .user = OCP_USER_SDMA,
4210 };
4211
4212 /* mpu -> emif1 */
4213 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4214 .master = &omap44xx_mpu_hwmod,
4215 .slave = &omap44xx_emif1_hwmod,
4216 .clk = "l3_div_ck",
4217 .user = OCP_USER_MPU | OCP_USER_SDMA,
4218 };
4219
4220 /* mpu -> emif2 */
4221 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4222 .master = &omap44xx_mpu_hwmod,
4223 .slave = &omap44xx_emif2_hwmod,
4224 .clk = "l3_div_ck",
4225 .user = OCP_USER_MPU | OCP_USER_SDMA,
4226 };
4227
4228 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4229 &omap44xx_l3_main_1__dmm,
4230 &omap44xx_mpu__dmm,
4231 &omap44xx_iva__l3_instr,
4232 &omap44xx_l3_main_3__l3_instr,
4233 &omap44xx_ocp_wp_noc__l3_instr,
4234 &omap44xx_dsp__l3_main_1,
4235 &omap44xx_dss__l3_main_1,
4236 &omap44xx_l3_main_2__l3_main_1,
4237 &omap44xx_l4_cfg__l3_main_1,
4238 &omap44xx_mmc1__l3_main_1,
4239 &omap44xx_mmc2__l3_main_1,
4240 &omap44xx_mpu__l3_main_1,
4241 &omap44xx_debugss__l3_main_2,
4242 &omap44xx_dma_system__l3_main_2,
4243 &omap44xx_fdif__l3_main_2,
4244 &omap44xx_gpu__l3_main_2,
4245 &omap44xx_hsi__l3_main_2,
4246 &omap44xx_ipu__l3_main_2,
4247 &omap44xx_iss__l3_main_2,
4248 &omap44xx_iva__l3_main_2,
4249 &omap44xx_l3_main_1__l3_main_2,
4250 &omap44xx_l4_cfg__l3_main_2,
4251 /* &omap44xx_usb_host_fs__l3_main_2, */
4252 &omap44xx_usb_host_hs__l3_main_2,
4253 &omap44xx_usb_otg_hs__l3_main_2,
4254 &omap44xx_l3_main_1__l3_main_3,
4255 &omap44xx_l3_main_2__l3_main_3,
4256 &omap44xx_l4_cfg__l3_main_3,
4257 &omap44xx_aess__l4_abe,
4258 &omap44xx_dsp__l4_abe,
4259 &omap44xx_l3_main_1__l4_abe,
4260 &omap44xx_mpu__l4_abe,
4261 &omap44xx_l3_main_1__l4_cfg,
4262 &omap44xx_l3_main_2__l4_per,
4263 &omap44xx_l4_cfg__l4_wkup,
4264 &omap44xx_mpu__mpu_private,
4265 &omap44xx_l4_cfg__ocp_wp_noc,
4266 &omap44xx_l4_abe__aess,
4267 &omap44xx_l4_abe__aess_dma,
4268 &omap44xx_l3_main_2__c2c,
4269 &omap44xx_l4_wkup__counter_32k,
4270 &omap44xx_l4_cfg__ctrl_module_core,
4271 &omap44xx_l4_cfg__ctrl_module_pad_core,
4272 &omap44xx_l4_wkup__ctrl_module_wkup,
4273 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4274 &omap44xx_l3_instr__debugss,
4275 &omap44xx_l4_cfg__dma_system,
4276 &omap44xx_l4_abe__dmic,
4277 &omap44xx_dsp__iva,
4278 /* &omap44xx_dsp__sl2if, */
4279 &omap44xx_l4_cfg__dsp,
4280 &omap44xx_l3_main_2__dss,
4281 &omap44xx_l4_per__dss,
4282 &omap44xx_l3_main_2__dss_dispc,
4283 &omap44xx_l4_per__dss_dispc,
4284 &omap44xx_l3_main_2__dss_dsi1,
4285 &omap44xx_l4_per__dss_dsi1,
4286 &omap44xx_l3_main_2__dss_dsi2,
4287 &omap44xx_l4_per__dss_dsi2,
4288 &omap44xx_l3_main_2__dss_hdmi,
4289 &omap44xx_l4_per__dss_hdmi,
4290 &omap44xx_l3_main_2__dss_rfbi,
4291 &omap44xx_l4_per__dss_rfbi,
4292 &omap44xx_l3_main_2__dss_venc,
4293 &omap44xx_l4_per__dss_venc,
4294 &omap44xx_l4_per__elm,
4295 &omap44xx_l4_cfg__fdif,
4296 &omap44xx_l4_wkup__gpio1,
4297 &omap44xx_l4_per__gpio2,
4298 &omap44xx_l4_per__gpio3,
4299 &omap44xx_l4_per__gpio4,
4300 &omap44xx_l4_per__gpio5,
4301 &omap44xx_l4_per__gpio6,
4302 &omap44xx_l3_main_2__gpmc,
4303 &omap44xx_l3_main_2__gpu,
4304 &omap44xx_l4_per__hdq1w,
4305 &omap44xx_l4_cfg__hsi,
4306 &omap44xx_l4_per__i2c1,
4307 &omap44xx_l4_per__i2c2,
4308 &omap44xx_l4_per__i2c3,
4309 &omap44xx_l4_per__i2c4,
4310 &omap44xx_l3_main_2__ipu,
4311 &omap44xx_l3_main_2__iss,
4312 /* &omap44xx_iva__sl2if, */
4313 &omap44xx_l3_main_2__iva,
4314 &omap44xx_l4_wkup__kbd,
4315 &omap44xx_l4_cfg__mailbox,
4316 &omap44xx_l4_abe__mcasp,
4317 &omap44xx_l4_abe__mcasp_dma,
4318 &omap44xx_l4_abe__mcbsp1,
4319 &omap44xx_l4_abe__mcbsp2,
4320 &omap44xx_l4_abe__mcbsp3,
4321 &omap44xx_l4_per__mcbsp4,
4322 &omap44xx_l4_abe__mcpdm,
4323 &omap44xx_l4_per__mcspi1,
4324 &omap44xx_l4_per__mcspi2,
4325 &omap44xx_l4_per__mcspi3,
4326 &omap44xx_l4_per__mcspi4,
4327 &omap44xx_l4_per__mmc1,
4328 &omap44xx_l4_per__mmc2,
4329 &omap44xx_l4_per__mmc3,
4330 &omap44xx_l4_per__mmc4,
4331 &omap44xx_l4_per__mmc5,
4332 &omap44xx_l3_main_2__mmu_ipu,
4333 &omap44xx_l4_cfg__mmu_dsp,
4334 &omap44xx_l3_main_2__ocmc_ram,
4335 &omap44xx_l4_cfg__ocp2scp_usb_phy,
4336 &omap44xx_mpu_private__prcm_mpu,
4337 &omap44xx_l4_wkup__cm_core_aon,
4338 &omap44xx_l4_cfg__cm_core,
4339 &omap44xx_l4_wkup__prm,
4340 &omap44xx_l4_wkup__scrm,
4341 /* &omap44xx_l3_main_2__sl2if, */
4342 &omap44xx_l4_abe__slimbus1,
4343 &omap44xx_l4_abe__slimbus1_dma,
4344 &omap44xx_l4_per__slimbus2,
4345 &omap44xx_l4_cfg__smartreflex_core,
4346 &omap44xx_l4_cfg__smartreflex_iva,
4347 &omap44xx_l4_cfg__smartreflex_mpu,
4348 &omap44xx_l4_cfg__spinlock,
4349 &omap44xx_l4_wkup__timer1,
4350 &omap44xx_l4_per__timer2,
4351 &omap44xx_l4_per__timer3,
4352 &omap44xx_l4_per__timer4,
4353 &omap44xx_l4_abe__timer5,
4354 &omap44xx_l4_abe__timer6,
4355 &omap44xx_l4_abe__timer7,
4356 &omap44xx_l4_abe__timer8,
4357 &omap44xx_l4_per__timer9,
4358 &omap44xx_l4_per__timer10,
4359 &omap44xx_l4_per__timer11,
4360 &omap44xx_l4_per__uart1,
4361 &omap44xx_l4_per__uart2,
4362 &omap44xx_l4_per__uart3,
4363 &omap44xx_l4_per__uart4,
4364 /* &omap44xx_l4_cfg__usb_host_fs, */
4365 &omap44xx_l4_cfg__usb_host_hs,
4366 &omap44xx_l4_cfg__usb_otg_hs,
4367 &omap44xx_l4_cfg__usb_tll_hs,
4368 &omap44xx_l4_wkup__wd_timer2,
4369 &omap44xx_l4_abe__wd_timer3,
4370 &omap44xx_l4_abe__wd_timer3_dma,
4371 &omap44xx_mpu__emif1,
4372 &omap44xx_mpu__emif2,
4373 &omap44xx_l3_main_2__aes1,
4374 &omap44xx_l3_main_2__aes2,
4375 &omap44xx_l3_main_2__des,
4376 &omap44xx_l3_main_2__sha0,
4377 NULL,
4378 };
4379
4380 int __init omap44xx_hwmod_init(void)
4381 {
4382 omap_hwmod_init();
4383 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4384 }
4385
CRIS linux kernel tree