arch/arm/mach-omap2/prminst44xx.c

   1 /*
   2  * OMAP4 PRM instance functions
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Copyright (C) 2011 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/errno.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18
  19 #include "iomap.h"
  20 #include "common.h"
  21 #include "prcm-common.h"
  22 #include "prm44xx.h"
  23 #include "prm54xx.h"
  24 #include "prm7xx.h"
  25 #include "prminst44xx.h"
  26 #include "prm-regbits-44xx.h"
  27 #include "prcm44xx.h"
  28 #include "prcm43xx.h"
  29 #include "prcm_mpu44xx.h"
  30 #include "soc.h"
  31
  32 static struct omap_domain_base _prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
  33
  34 static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
  35
  36 /**
  37  * omap_prm_base_init - Populates the prm partitions
  38  *
  39  * Populates the base addresses of the _prm_bases
  40  * array used for read/write of prm module registers.
  41  */
  42 void omap_prm_base_init(void)
  43 {
  44         memcpy(&_prm_bases[OMAP4430_PRM_PARTITION], &prm_base,
  45                sizeof(prm_base));
  46         memcpy(&_prm_bases[OMAP4430_PRCM_MPU_PARTITION], &prcm_mpu_base,
  47                sizeof(prcm_mpu_base));
  48 }
  49
  50 s32 omap4_prmst_get_prm_dev_inst(void)
  51 {
  52         return prm_dev_inst;
  53 }
  54
  55 void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
  56 {
  57         prm_dev_inst = dev_inst;
  58 }
  59
  60 /* Read a register in a PRM instance */
  61 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
  62 {
  63         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
  64                part == OMAP4430_INVALID_PRCM_PARTITION ||
  65                !_prm_bases[part].va);
  66         return readl_relaxed(_prm_bases[part].va + inst + idx);
  67 }
  68
  69 /* Write into a register in a PRM instance */
  70 void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
  71 {
  72         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
  73                part == OMAP4430_INVALID_PRCM_PARTITION ||
  74                !_prm_bases[part].va);
  75         writel_relaxed(val, _prm_bases[part].va + inst + idx);
  76 }
  77
  78 /* Read-modify-write a register in PRM. Caller must lock */
  79 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
  80                                     u16 idx)
  81 {
  82         u32 v;
  83
  84         v = omap4_prminst_read_inst_reg(part, inst, idx);
  85         v &= ~mask;
  86         v |= bits;
  87         omap4_prminst_write_inst_reg(v, part, inst, idx);
  88
  89         return v;
  90 }
  91
  92 /**
  93  * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
  94  * submodules contained in the hwmod module
  95  * @rstctrl_reg: RM_RSTCTRL register address for this module
  96  * @shift: register bit shift corresponding to the reset line to check
  97  *
  98  * Returns 1 if the (sub)module hardreset line is currently asserted,
  99  * 0 if the (sub)module hardreset line is not currently asserted, or
 100  * -EINVAL upon parameter error.
 101  */
 102 int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
 103                                         u16 rstctrl_offs)
 104 {
 105         u32 v;
 106
 107         v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
 108         v &= 1 << shift;
 109         v >>= shift;
 110
 111         return v;
 112 }
 113
 114 /**
 115  * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
 116  * @rstctrl_reg: RM_RSTCTRL register address for this module
 117  * @shift: register bit shift corresponding to the reset line to assert
 118  *
 119  * Some IPs like dsp, ipu or iva contain processors that require an HW
 120  * reset line to be asserted / deasserted in order to fully enable the
 121  * IP.  These modules may have multiple hard-reset lines that reset
 122  * different 'submodules' inside the IP block.  This function will
 123  * place the submodule into reset.  Returns 0 upon success or -EINVAL
 124  * upon an argument error.
 125  */
 126 int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
 127                                    u16 rstctrl_offs)
 128 {
 129         u32 mask = 1 << shift;
 130
 131         omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
 132
 133         return 0;
 134 }
 135
 136 /**
 137  * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
 138  * wait
 139  * @shift: register bit shift corresponding to the reset line to deassert
 140  * @st_shift: status bit offset corresponding to the reset line
 141  * @part: PRM partition
 142  * @inst: PRM instance offset
 143  * @rstctrl_offs: reset register offset
 144  * @rstst_offs: reset status register offset
 145  *
 146  * Some IPs like dsp, ipu or iva contain processors that require an HW
 147  * reset line to be asserted / deasserted in order to fully enable the
 148  * IP.  These modules may have multiple hard-reset lines that reset
 149  * different 'submodules' inside the IP block.  This function will
 150  * take the submodule out of reset and wait until the PRCM indicates
 151  * that the reset has completed before returning.  Returns 0 upon success or
 152  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 153  * of reset, or -EBUSY if the submodule did not exit reset promptly.
 154  */
 155 int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
 156                                      u16 rstctrl_offs, u16 rstst_offs)
 157 {
 158         int c;
 159         u32 mask = 1 << shift;
 160         u32 st_mask = 1 << st_shift;
 161
 162         /* Check the current status to avoid de-asserting the line twice */
 163         if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
 164                                                 rstctrl_offs) == 0)
 165                 return -EEXIST;
 166
 167         /* Clear the reset status by writing 1 to the status bit */
 168         omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
 169                                         rstst_offs);
 170         /* de-assert the reset control line */
 171         omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
 172         /* wait the status to be set */
 173         omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
 174                                                               inst, rstst_offs),
 175                           MAX_MODULE_HARDRESET_WAIT, c);
 176
 177         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 178 }
 179
 180
 181 void omap4_prminst_global_warm_sw_reset(void)
 182 {
 183         u32 v;
 184         s32 inst = omap4_prmst_get_prm_dev_inst();
 185
 186         if (inst == PRM_INSTANCE_UNKNOWN)
 187                 return;
 188
 189         v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
 190                                         OMAP4_PRM_RSTCTRL_OFFSET);
 191         v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
 192         omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
 193                                  inst, OMAP4_PRM_RSTCTRL_OFFSET);
 194
 195         /* OCP barrier */
 196         v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 197                                     inst, OMAP4_PRM_RSTCTRL_OFFSET);
 198 }