arch/arm/mach-pxa/include/mach/regs-uart.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ASM_ARCH_REGS_UART_H
   3 #define __ASM_ARCH_REGS_UART_H
   4
   5 /*
   6  * UARTs
   7  */
   8
   9 /* Full Function UART (FFUART) */
  10 #define FFUART          FFRBR
  11 #define FFRBR           __REG(0x40100000)  /* Receive Buffer Register (read only) */
  12 #define FFTHR           __REG(0x40100000)  /* Transmit Holding Register (write only) */
  13 #define FFIER           __REG(0x40100004)  /* Interrupt Enable Register (read/write) */
  14 #define FFIIR           __REG(0x40100008)  /* Interrupt ID Register (read only) */
  15 #define FFFCR           __REG(0x40100008)  /* FIFO Control Register (write only) */
  16 #define FFLCR           __REG(0x4010000C)  /* Line Control Register (read/write) */
  17 #define FFMCR           __REG(0x40100010)  /* Modem Control Register (read/write) */
  18 #define FFLSR           __REG(0x40100014)  /* Line Status Register (read only) */
  19 #define FFMSR           __REG(0x40100018)  /* Modem Status Register (read only) */
  20 #define FFSPR           __REG(0x4010001C)  /* Scratch Pad Register (read/write) */
  21 #define FFISR           __REG(0x40100020)  /* Infrared Selection Register (read/write) */
  22 #define FFDLL           __REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
  23 #define FFDLH           __REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
  24
  25 /* Bluetooth UART (BTUART) */
  26 #define BTUART          BTRBR
  27 #define BTRBR           __REG(0x40200000)  /* Receive Buffer Register (read only) */
  28 #define BTTHR           __REG(0x40200000)  /* Transmit Holding Register (write only) */
  29 #define BTIER           __REG(0x40200004)  /* Interrupt Enable Register (read/write) */
  30 #define BTIIR           __REG(0x40200008)  /* Interrupt ID Register (read only) */
  31 #define BTFCR           __REG(0x40200008)  /* FIFO Control Register (write only) */
  32 #define BTLCR           __REG(0x4020000C)  /* Line Control Register (read/write) */
  33 #define BTMCR           __REG(0x40200010)  /* Modem Control Register (read/write) */
  34 #define BTLSR           __REG(0x40200014)  /* Line Status Register (read only) */
  35 #define BTMSR           __REG(0x40200018)  /* Modem Status Register (read only) */
  36 #define BTSPR           __REG(0x4020001C)  /* Scratch Pad Register (read/write) */
  37 #define BTISR           __REG(0x40200020)  /* Infrared Selection Register (read/write) */
  38 #define BTDLL           __REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
  39 #define BTDLH           __REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
  40
  41 /* Standard UART (STUART) */
  42 #define STUART          STRBR
  43 #define STRBR           __REG(0x40700000)  /* Receive Buffer Register (read only) */
  44 #define STTHR           __REG(0x40700000)  /* Transmit Holding Register (write only) */
  45 #define STIER           __REG(0x40700004)  /* Interrupt Enable Register (read/write) */
  46 #define STIIR           __REG(0x40700008)  /* Interrupt ID Register (read only) */
  47 #define STFCR           __REG(0x40700008)  /* FIFO Control Register (write only) */
  48 #define STLCR           __REG(0x4070000C)  /* Line Control Register (read/write) */
  49 #define STMCR           __REG(0x40700010)  /* Modem Control Register (read/write) */
  50 #define STLSR           __REG(0x40700014)  /* Line Status Register (read only) */
  51 #define STMSR           __REG(0x40700018)  /* Reserved */
  52 #define STSPR           __REG(0x4070001C)  /* Scratch Pad Register (read/write) */
  53 #define STISR           __REG(0x40700020)  /* Infrared Selection Register (read/write) */
  54 #define STDLL           __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
  55 #define STDLH           __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
  56
  57 /* Hardware UART (HWUART) */
  58 #define HWUART          HWRBR
  59 #define HWRBR           __REG(0x41600000)  /* Receive Buffer Register (read only) */
  60 #define HWTHR           __REG(0x41600000)  /* Transmit Holding Register (write only) */
  61 #define HWIER           __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
  62 #define HWIIR           __REG(0x41600008)  /* Interrupt ID Register (read only) */
  63 #define HWFCR           __REG(0x41600008)  /* FIFO Control Register (write only) */
  64 #define HWLCR           __REG(0x4160000C)  /* Line Control Register (read/write) */
  65 #define HWMCR           __REG(0x41600010)  /* Modem Control Register (read/write) */
  66 #define HWLSR           __REG(0x41600014)  /* Line Status Register (read only) */
  67 #define HWMSR           __REG(0x41600018)  /* Modem Status Register (read only) */
  68 #define HWSPR           __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
  69 #define HWISR           __REG(0x41600020)  /* Infrared Selection Register (read/write) */
  70 #define HWFOR           __REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
  71 #define HWABR           __REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
  72 #define HWACR           __REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
  73 #define HWDLL           __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
  74 #define HWDLH           __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
  75
  76 #define IER_DMAE        (1 << 7)        /* DMA Requests Enable */
  77 #define IER_UUE         (1 << 6)        /* UART Unit Enable */
  78 #define IER_NRZE        (1 << 5)        /* NRZ coding Enable */
  79 #define IER_RTIOE       (1 << 4)        /* Receiver Time Out Interrupt Enable */
  80 #define IER_MIE         (1 << 3)        /* Modem Interrupt Enable */
  81 #define IER_RLSE        (1 << 2)        /* Receiver Line Status Interrupt Enable */
  82 #define IER_TIE         (1 << 1)        /* Transmit Data request Interrupt Enable */
  83 #define IER_RAVIE       (1 << 0)        /* Receiver Data Available Interrupt Enable */
  84
  85 #define IIR_FIFOES1     (1 << 7)        /* FIFO Mode Enable Status */
  86 #define IIR_FIFOES0     (1 << 6)        /* FIFO Mode Enable Status */
  87 #define IIR_TOD         (1 << 3)        /* Time Out Detected */
  88 #define IIR_IID2        (1 << 2)        /* Interrupt Source Encoded */
  89 #define IIR_IID1        (1 << 1)        /* Interrupt Source Encoded */
  90 #define IIR_IP          (1 << 0)        /* Interrupt Pending (active low) */
  91
  92 #define FCR_ITL2        (1 << 7)        /* Interrupt Trigger Level */
  93 #define FCR_ITL1        (1 << 6)        /* Interrupt Trigger Level */
  94 #define FCR_RESETTF     (1 << 2)        /* Reset Transmitter FIFO */
  95 #define FCR_RESETRF     (1 << 1)        /* Reset Receiver FIFO */
  96 #define FCR_TRFIFOE     (1 << 0)        /* Transmit and Receive FIFO Enable */
  97 #define FCR_ITL_1       (0)
  98 #define FCR_ITL_8       (FCR_ITL1)
  99 #define FCR_ITL_16      (FCR_ITL2)
 100 #define FCR_ITL_32      (FCR_ITL2|FCR_ITL1)
 101
 102 #define LCR_DLAB        (1 << 7)        /* Divisor Latch Access Bit */
 103 #define LCR_SB          (1 << 6)        /* Set Break */
 104 #define LCR_STKYP       (1 << 5)        /* Sticky Parity */
 105 #define LCR_EPS         (1 << 4)        /* Even Parity Select */
 106 #define LCR_PEN         (1 << 3)        /* Parity Enable */
 107 #define LCR_STB         (1 << 2)        /* Stop Bit */
 108 #define LCR_WLS1        (1 << 1)        /* Word Length Select */
 109 #define LCR_WLS0        (1 << 0)        /* Word Length Select */
 110
 111 #define LSR_FIFOE       (1 << 7)        /* FIFO Error Status */
 112 #define LSR_TEMT        (1 << 6)        /* Transmitter Empty */
 113 #define LSR_TDRQ        (1 << 5)        /* Transmit Data Request */
 114 #define LSR_BI          (1 << 4)        /* Break Interrupt */
 115 #define LSR_FE          (1 << 3)        /* Framing Error */
 116 #define LSR_PE          (1 << 2)        /* Parity Error */
 117 #define LSR_OE          (1 << 1)        /* Overrun Error */
 118 #define LSR_DR          (1 << 0)        /* Data Ready */
 119
 120 #define MCR_LOOP        (1 << 4)
 121 #define MCR_OUT2        (1 << 3)        /* force MSR_DCD in loopback mode */
 122 #define MCR_OUT1        (1 << 2)        /* force MSR_RI in loopback mode */
 123 #define MCR_RTS         (1 << 1)        /* Request to Send */
 124 #define MCR_DTR         (1 << 0)        /* Data Terminal Ready */
 125
 126 #define MSR_DCD         (1 << 7)        /* Data Carrier Detect */
 127 #define MSR_RI          (1 << 6)        /* Ring Indicator */
 128 #define MSR_DSR         (1 << 5)        /* Data Set Ready */
 129 #define MSR_CTS         (1 << 4)        /* Clear To Send */
 130 #define MSR_DDCD        (1 << 3)        /* Delta Data Carrier Detect */
 131 #define MSR_TERI        (1 << 2)        /* Trailing Edge Ring Indicator */
 132 #define MSR_DDSR        (1 << 1)        /* Delta Data Set Ready */
 133 #define MSR_DCTS        (1 << 0)        /* Delta Clear To Send */
 134
 135 /*
 136  * IrSR (Infrared Selection Register)
 137  */
 138 #define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
 139 #define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
 140 #define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
 141 #define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
 142 #define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */
 143
 144 #endif /* __ASM_ARCH_REGS_UART_H */