arch/arm/mach-s3c64xx/setup-usb-phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright (C) 2011 Samsung Electronics Co.Ltd
   4 // Author: Joonyoung Shim <jy0922.shim@samsung.com>
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/platform_device.h>
  11 #include <mach/map.h>
  12 #include <plat/cpu.h>
  13 #include <plat/usb-phy.h>
  14
  15 #include "regs-sys.h"
  16 #include "regs-usb-hsotg-phy.h"
  17
  18 static int s3c_usb_otgphy_init(struct platform_device *pdev)
  19 {
  20         struct clk *xusbxti;
  21         u32 phyclk;
  22
  23         writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
  24
  25         /* set clock frequency for PLL */
  26         phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
  27
  28         xusbxti = clk_get(&pdev->dev, "xusbxti");
  29         if (xusbxti && !IS_ERR(xusbxti)) {
  30                 switch (clk_get_rate(xusbxti)) {
  31                 case 12 * MHZ:
  32                         phyclk |= S3C_PHYCLK_CLKSEL_12M;
  33                         break;
  34                 case 24 * MHZ:
  35                         phyclk |= S3C_PHYCLK_CLKSEL_24M;
  36                         break;
  37                 default:
  38                 case 48 * MHZ:
  39                         /* default reference clock */
  40                         break;
  41                 }
  42                 clk_put(xusbxti);
  43         }
  44
  45         /* TODO: select external clock/oscillator */
  46         writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
  47
  48         /* set to normal OTG PHY */
  49         writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
  50         mdelay(1);
  51
  52         /* reset OTG PHY and Link */
  53         writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
  54                         S3C_RSTCON);
  55         udelay(20);     /* at-least 10uS */
  56         writel(0, S3C_RSTCON);
  57
  58         return 0;
  59 }
  60
  61 static int s3c_usb_otgphy_exit(struct platform_device *pdev)
  62 {
  63         writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
  64                                 S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
  65
  66         writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
  67
  68         return 0;
  69 }
  70
  71 int s5p_usb_phy_init(struct platform_device *pdev, int type)
  72 {
  73         if (type == USB_PHY_TYPE_DEVICE)
  74                 return s3c_usb_otgphy_init(pdev);
  75
  76         return -EINVAL;
  77 }
  78
  79 int s5p_usb_phy_exit(struct platform_device *pdev, int type)
  80 {
  81         if (type == USB_PHY_TYPE_DEVICE)
  82                 return s3c_usb_otgphy_exit(pdev);
  83
  84         return -EINVAL;
  85 }