arch/arm/mach-sa1100/include/mach/irqs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * arch/arm/mach-sa1100/include/mach/irqs.h
   4  *
   5  * Copyright (C) 1996 Russell King
   6  * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus).
   7  * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation)
   8  *
   9  * 2001/11/14   RMK     Cleaned up and standardised a lot of the IRQs.
  10  */
  11
  12 #define IRQ_GPIO0_SC            1
  13 #define IRQ_GPIO1_SC            2
  14 #define IRQ_GPIO2_SC            3
  15 #define IRQ_GPIO3_SC            4
  16 #define IRQ_GPIO4_SC            5
  17 #define IRQ_GPIO5_SC            6
  18 #define IRQ_GPIO6_SC            7
  19 #define IRQ_GPIO7_SC            8
  20 #define IRQ_GPIO8_SC            9
  21 #define IRQ_GPIO9_SC            10
  22 #define IRQ_GPIO10_SC           11
  23 #define IRQ_GPIO11_27           12
  24 #define IRQ_LCD                 13      /* LCD controller           */
  25 #define IRQ_Ser0UDC             14      /* Ser. port 0 UDC          */
  26 #define IRQ_Ser1SDLC            15      /* Ser. port 1 SDLC         */
  27 #define IRQ_Ser1UART            16      /* Ser. port 1 UART         */
  28 #define IRQ_Ser2ICP             17      /* Ser. port 2 ICP          */
  29 #define IRQ_Ser3UART            18      /* Ser. port 3 UART         */
  30 #define IRQ_Ser4MCP             19      /* Ser. port 4 MCP          */
  31 #define IRQ_Ser4SSP             20      /* Ser. port 4 SSP          */
  32 #define IRQ_DMA0                21      /* DMA controller channel 0 */
  33 #define IRQ_DMA1                22      /* DMA controller channel 1 */
  34 #define IRQ_DMA2                23      /* DMA controller channel 2 */
  35 #define IRQ_DMA3                24      /* DMA controller channel 3 */
  36 #define IRQ_DMA4                25      /* DMA controller channel 4 */
  37 #define IRQ_DMA5                26      /* DMA controller channel 5 */
  38 #define IRQ_OST0                27      /* OS Timer match 0         */
  39 #define IRQ_OST1                28      /* OS Timer match 1         */
  40 #define IRQ_OST2                29      /* OS Timer match 2         */
  41 #define IRQ_OST3                30      /* OS Timer match 3         */
  42 #define IRQ_RTC1Hz              31      /* RTC 1 Hz clock           */
  43 #define IRQ_RTCAlrm             32      /* RTC Alarm                */
  44
  45 #define IRQ_GPIO0               33
  46 #define IRQ_GPIO1               34
  47 #define IRQ_GPIO2               35
  48 #define IRQ_GPIO3               36
  49 #define IRQ_GPIO4               37
  50 #define IRQ_GPIO5               38
  51 #define IRQ_GPIO6               39
  52 #define IRQ_GPIO7               40
  53 #define IRQ_GPIO8               41
  54 #define IRQ_GPIO9               42
  55 #define IRQ_GPIO10              43
  56 #define IRQ_GPIO11              44
  57 #define IRQ_GPIO12              45
  58 #define IRQ_GPIO13              46
  59 #define IRQ_GPIO14              47
  60 #define IRQ_GPIO15              48
  61 #define IRQ_GPIO16              49
  62 #define IRQ_GPIO17              50
  63 #define IRQ_GPIO18              51
  64 #define IRQ_GPIO19              52
  65 #define IRQ_GPIO20              53
  66 #define IRQ_GPIO21              54
  67 #define IRQ_GPIO22              55
  68 #define IRQ_GPIO23              56
  69 #define IRQ_GPIO24              57
  70 #define IRQ_GPIO25              58
  71 #define IRQ_GPIO26              59
  72 #define IRQ_GPIO27              60
  73
  74 /*
  75  * The next 16 interrupts are for board specific purposes.  Since
  76  * the kernel can only run on one machine at a time, we can re-use
  77  * these.  If you need more, increase IRQ_BOARD_END, but keep it
  78  * within sensible limits.  IRQs 61 to 76 are available.
  79  */
  80 #define IRQ_BOARD_START         61
  81 #define IRQ_BOARD_END           77
  82
  83 /*
  84  * Figure out the MAX IRQ number.
  85  *
  86  * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically
  87  * allocate their IRQs above NR_IRQS.
  88  *
  89  * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has
  90  * to be included in the NR_IRQS calculation.
  91  */
  92 #ifdef CONFIG_SHARP_LOCOMO
  93 #define NR_IRQS_LOCOMO          4
  94 #else
  95 #define NR_IRQS_LOCOMO          0
  96 #endif
  97
  98 #ifndef NR_IRQS
  99 #define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
 100 #endif
 101 #define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)