| blob | 7f14acf67caff57b2daf8cca2b97f28d120d8532 |
1 # SPDX-License-Identifier: GPL-2.0
2 comment "Processor Type"
4 # Select CPU types depending on the architecture selected. This selects
5 # which CPUs we support in the kernel image, and the compiler instruction
6 # optimiser behaviour.
8 # ARM7TDMI
9 config CPU_ARM7TDMI
10 bool
11 depends on !MMU
12 select CPU_32v4T
13 select CPU_ABRT_LV4T
14 select CPU_CACHE_V4
15 select CPU_PABRT_LEGACY
16 help
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
20 Say Y if you want support for the ARM7TDMI processor.
21 Otherwise, say N.
23 # ARM720T
24 config CPU_ARM720T
25 bool
26 select CPU_32v4T
27 select CPU_ABRT_LV4T
28 select CPU_CACHE_V4
29 select CPU_CACHE_VIVT
30 select CPU_COPY_V4WT if MMU
31 select CPU_CP15_MMU
32 select CPU_PABRT_LEGACY
33 select CPU_THUMB_CAPABLE
34 select CPU_TLB_V4WT if MMU
35 help
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
37 MMU built around an ARM7TDMI core.
39 Say Y if you want support for the ARM720T processor.
40 Otherwise, say N.
42 # ARM740T
43 config CPU_ARM740T
44 bool
45 depends on !MMU
46 select CPU_32v4T
47 select CPU_ABRT_LV4T
48 select CPU_CACHE_V4
49 select CPU_CP15_MPU
50 select CPU_PABRT_LEGACY
51 select CPU_THUMB_CAPABLE
52 help
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
54 write buffer and MPU(Protection Unit) built around
55 an ARM7TDMI core.
57 Say Y if you want support for the ARM740T processor.
58 Otherwise, say N.
60 # ARM9TDMI
61 config CPU_ARM9TDMI
62 bool
63 depends on !MMU
64 select CPU_32v4T
65 select CPU_ABRT_NOMMU
66 select CPU_CACHE_V4
67 select CPU_PABRT_LEGACY
68 help
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
72 Say Y if you want support for the ARM9TDMI processor.
73 Otherwise, say N.
75 # ARM920T
76 config CPU_ARM920T
77 bool
78 select CPU_32v4T
79 select CPU_ABRT_EV4T
80 select CPU_CACHE_V4WT
81 select CPU_CACHE_VIVT
82 select CPU_COPY_V4WB if MMU
83 select CPU_CP15_MMU
84 select CPU_PABRT_LEGACY
85 select CPU_THUMB_CAPABLE
86 select CPU_TLB_V4WBI if MMU
87 help
88 The ARM920T is licensed to be produced by numerous vendors,
89 and is used in the Cirrus EP93xx and the Samsung S3C2410.
91 Say Y if you want support for the ARM920T processor.
92 Otherwise, say N.
94 # ARM922T
95 config CPU_ARM922T
96 bool
97 select CPU_32v4T
98 select CPU_ABRT_EV4T
99 select CPU_CACHE_V4WT
100 select CPU_CACHE_VIVT
101 select CPU_COPY_V4WB if MMU
102 select CPU_CP15_MMU
103 select CPU_PABRT_LEGACY
104 select CPU_THUMB_CAPABLE
105 select CPU_TLB_V4WBI if MMU
106 help
107 The ARM922T is a version of the ARM920T, but with smaller
108 instruction and data caches. It is used in Altera's
109 Excalibur XA device family and Micrel's KS8695 Centaur.
111 Say Y if you want support for the ARM922T processor.
112 Otherwise, say N.
114 # ARM925T
115 config CPU_ARM925T
116 bool
117 select CPU_32v4T
118 select CPU_ABRT_EV4T
119 select CPU_CACHE_V4WT
120 select CPU_CACHE_VIVT
121 select CPU_COPY_V4WB if MMU
122 select CPU_CP15_MMU
123 select CPU_PABRT_LEGACY
124 select CPU_THUMB_CAPABLE
125 select CPU_TLB_V4WBI if MMU
126 help
127 The ARM925T is a mix between the ARM920T and ARM926T, but with
128 different instruction and data caches. It is used in TI's OMAP
129 device family.
131 Say Y if you want support for the ARM925T processor.
132 Otherwise, say N.
134 # ARM926T
135 config CPU_ARM926T
136 bool
137 select CPU_32v5
138 select CPU_ABRT_EV5TJ
139 select CPU_CACHE_VIVT
140 select CPU_COPY_V4WB if MMU
141 select CPU_CP15_MMU
142 select CPU_PABRT_LEGACY
143 select CPU_THUMB_CAPABLE
144 select CPU_TLB_V4WBI if MMU
145 help
146 This is a variant of the ARM920. It has slightly different
147 instruction sequences for cache and TLB operations. Curiously,
148 there is no documentation on it at the ARM corporate website.
150 Say Y if you want support for the ARM926T processor.
151 Otherwise, say N.
153 # FA526
154 config CPU_FA526
155 bool
156 select CPU_32v4
157 select CPU_ABRT_EV4
158 select CPU_CACHE_FA
159 select CPU_CACHE_VIVT
160 select CPU_COPY_FA if MMU
161 select CPU_CP15_MMU
162 select CPU_PABRT_LEGACY
163 select CPU_TLB_FA if MMU
164 help
165 The FA526 is a version of the ARMv4 compatible processor with
166 Branch Target Buffer, Unified TLB and cache line size 16.
168 Say Y if you want support for the FA526 processor.
169 Otherwise, say N.
171 # ARM940T
172 config CPU_ARM940T
173 bool
174 depends on !MMU
175 select CPU_32v4T
176 select CPU_ABRT_NOMMU
177 select CPU_CACHE_VIVT
178 select CPU_CP15_MPU
179 select CPU_PABRT_LEGACY
180 select CPU_THUMB_CAPABLE
181 help
182 ARM940T is a member of the ARM9TDMI family of general-
183 purpose microprocessors with MPU and separate 4KB
184 instruction and 4KB data cases, each with a 4-word line
185 length.
187 Say Y if you want support for the ARM940T processor.
188 Otherwise, say N.
190 # ARM946E-S
191 config CPU_ARM946E
192 bool
193 depends on !MMU
194 select CPU_32v5
195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU
198 select CPU_PABRT_LEGACY
199 select CPU_THUMB_CAPABLE
200 help
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
205 Say Y if you want support for the ARM946E-S processor.
206 Otherwise, say N.
208 # ARM1020 - needs validating
209 config CPU_ARM1020
210 bool
211 select CPU_32v5
212 select CPU_ABRT_EV4T
213 select CPU_CACHE_V4WT
214 select CPU_CACHE_VIVT
215 select CPU_COPY_V4WB if MMU
216 select CPU_CP15_MMU
217 select CPU_PABRT_LEGACY
218 select CPU_THUMB_CAPABLE
219 select CPU_TLB_V4WBI if MMU
220 help
221 The ARM1020 is the 32K cached version of the ARM10 processor,
222 with an addition of a floating-point unit.
224 Say Y if you want support for the ARM1020 processor.
225 Otherwise, say N.
227 # ARM1020E - needs validating
228 config CPU_ARM1020E
229 bool
230 depends on n
231 select CPU_32v5
232 select CPU_ABRT_EV4T
233 select CPU_CACHE_V4WT
234 select CPU_CACHE_VIVT
235 select CPU_COPY_V4WB if MMU
236 select CPU_CP15_MMU
237 select CPU_PABRT_LEGACY
238 select CPU_THUMB_CAPABLE
239 select CPU_TLB_V4WBI if MMU
241 # ARM1022E
242 config CPU_ARM1022
243 bool
244 select CPU_32v5
245 select CPU_ABRT_EV4T
246 select CPU_CACHE_VIVT
247 select CPU_COPY_V4WB if MMU # can probably do better
248 select CPU_CP15_MMU
249 select CPU_PABRT_LEGACY
250 select CPU_THUMB_CAPABLE
251 select CPU_TLB_V4WBI if MMU
252 help
253 The ARM1022E is an implementation of the ARMv5TE architecture
254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
255 embedded trace macrocell, and a floating-point unit.
257 Say Y if you want support for the ARM1022E processor.
258 Otherwise, say N.
260 # ARM1026EJ-S
261 config CPU_ARM1026
262 bool
263 select CPU_32v5
264 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
265 select CPU_CACHE_VIVT
266 select CPU_COPY_V4WB if MMU # can probably do better
267 select CPU_CP15_MMU
268 select CPU_PABRT_LEGACY
269 select CPU_THUMB_CAPABLE
270 select CPU_TLB_V4WBI if MMU
271 help
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
273 based upon the ARM10 integer core.
275 Say Y if you want support for the ARM1026EJ-S processor.
276 Otherwise, say N.
278 # SA110
279 config CPU_SA110
280 bool
281 select CPU_32v3 if ARCH_RPC
282 select CPU_32v4 if !ARCH_RPC
283 select CPU_ABRT_EV4
284 select CPU_CACHE_V4WB
285 select CPU_CACHE_VIVT
286 select CPU_COPY_V4WB if MMU
287 select CPU_CP15_MMU
288 select CPU_PABRT_LEGACY
289 select CPU_TLB_V4WB if MMU
290 help
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
292 is available at five speeds ranging from 100 MHz to 233 MHz.
293 More information is available at
294 <http://developer.intel.com/design/strong/sa110.htm>.
296 Say Y if you want support for the SA-110 processor.
297 Otherwise, say N.
299 # SA1100
300 config CPU_SA1100
301 bool
302 select CPU_32v4
303 select CPU_ABRT_EV4
304 select CPU_CACHE_V4WB
305 select CPU_CACHE_VIVT
306 select CPU_CP15_MMU
307 select CPU_PABRT_LEGACY
308 select CPU_TLB_V4WB if MMU
310 # XScale
311 config CPU_XSCALE
312 bool
313 select CPU_32v5
314 select CPU_ABRT_EV5T
315 select CPU_CACHE_VIVT
316 select CPU_CP15_MMU
317 select CPU_PABRT_LEGACY
318 select CPU_THUMB_CAPABLE
319 select CPU_TLB_V4WBI if MMU
321 # XScale Core Version 3
322 config CPU_XSC3
323 bool
324 select CPU_32v5
325 select CPU_ABRT_EV5T
326 select CPU_CACHE_VIVT
327 select CPU_CP15_MMU
328 select CPU_PABRT_LEGACY
329 select CPU_THUMB_CAPABLE
330 select CPU_TLB_V4WBI if MMU
331 select IO_36
333 # Marvell PJ1 (Mohawk)
334 config CPU_MOHAWK
335 bool
336 select CPU_32v5
337 select CPU_ABRT_EV5T
338 select CPU_CACHE_VIVT
339 select CPU_COPY_V4WB if MMU
340 select CPU_CP15_MMU
341 select CPU_PABRT_LEGACY
342 select CPU_THUMB_CAPABLE
343 select CPU_TLB_V4WBI if MMU
345 # Feroceon
346 config CPU_FEROCEON
347 bool
348 select CPU_32v5
349 select CPU_ABRT_EV5T
350 select CPU_CACHE_VIVT
351 select CPU_COPY_FEROCEON if MMU
352 select CPU_CP15_MMU
353 select CPU_PABRT_LEGACY
354 select CPU_THUMB_CAPABLE
355 select CPU_TLB_FEROCEON if MMU
357 config CPU_FEROCEON_OLD_ID
358 bool "Accept early Feroceon cores with an ARM926 ID"
359 depends on CPU_FEROCEON && !CPU_ARM926T
360 default y
361 help
362 This enables the usage of some old Feroceon cores
363 for which the CPU ID is equal to the ARM926 ID.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
366 # Marvell PJ4
367 config CPU_PJ4
368 bool
369 select ARM_THUMBEE
370 select CPU_V7
372 config CPU_PJ4B
373 bool
374 select CPU_V7
376 # ARMv6
377 config CPU_V6
378 bool
379 select CPU_32v6
380 select CPU_ABRT_EV6
381 select CPU_CACHE_V6
382 select CPU_CACHE_VIPT
383 select CPU_COPY_V6 if MMU
384 select CPU_CP15_MMU
385 select CPU_HAS_ASID if MMU
386 select CPU_PABRT_V6
387 select CPU_THUMB_CAPABLE
388 select CPU_TLB_V6 if MMU
390 # ARMv6k
391 config CPU_V6K
392 bool
393 select CPU_32v6
394 select CPU_32v6K
395 select CPU_ABRT_EV6
396 select CPU_CACHE_V6
397 select CPU_CACHE_VIPT
398 select CPU_COPY_V6 if MMU
399 select CPU_CP15_MMU
400 select CPU_HAS_ASID if MMU
401 select CPU_PABRT_V6
402 select CPU_THUMB_CAPABLE
403 select CPU_TLB_V6 if MMU
405 # ARMv7
406 config CPU_V7
407 bool
408 select CPU_32v6K
409 select CPU_32v7
410 select CPU_ABRT_EV7
411 select CPU_CACHE_V7
412 select CPU_CACHE_VIPT
413 select CPU_COPY_V6 if MMU
414 select CPU_CP15_MMU if MMU
415 select CPU_CP15_MPU if !MMU
416 select CPU_HAS_ASID if MMU
417 select CPU_PABRT_V7
418 select CPU_THUMB_CAPABLE
419 select CPU_TLB_V7 if MMU
421 # ARMv7M
422 config CPU_V7M
423 bool
424 select CPU_32v7M
425 select CPU_ABRT_NOMMU
426 select CPU_CACHE_V7M
427 select CPU_CACHE_NOP
428 select CPU_PABRT_LEGACY
429 select CPU_THUMBONLY
431 config CPU_THUMBONLY
432 bool
433 select CPU_THUMB_CAPABLE
434 # There are no CPUs available with MMU that don't implement an ARM ISA:
435 depends on !MMU
436 help
437 Select this if your CPU doesn't support the 32 bit ARM instructions.
439 config CPU_THUMB_CAPABLE
440 bool
441 help
442 Select this if your CPU can support Thumb mode.
444 # Figure out what processor architecture version we should be using.
445 # This defines the compiler instruction set which depends on the machine type.
446 config CPU_32v3
447 bool
448 select CPU_USE_DOMAINS if MMU
449 select NEED_KUSER_HELPERS
450 select TLS_REG_EMUL if SMP || !MMU
451 select CPU_NO_EFFICIENT_FFS
453 config CPU_32v4
454 bool
455 select CPU_USE_DOMAINS if MMU
456 select NEED_KUSER_HELPERS
457 select TLS_REG_EMUL if SMP || !MMU
458 select CPU_NO_EFFICIENT_FFS
460 config CPU_32v4T
461 bool
462 select CPU_USE_DOMAINS if MMU
463 select NEED_KUSER_HELPERS
464 select TLS_REG_EMUL if SMP || !MMU
465 select CPU_NO_EFFICIENT_FFS
467 config CPU_32v5
468 bool
469 select CPU_USE_DOMAINS if MMU
470 select NEED_KUSER_HELPERS
471 select TLS_REG_EMUL if SMP || !MMU
473 config CPU_32v6
474 bool
475 select TLS_REG_EMUL if !CPU_32v6K && !MMU
477 config CPU_32v6K
478 bool
480 config CPU_32v7
481 bool
483 config CPU_32v7M
484 bool
486 # The abort model
487 config CPU_ABRT_NOMMU
488 bool
490 config CPU_ABRT_EV4
491 bool
493 config CPU_ABRT_EV4T
494 bool
496 config CPU_ABRT_LV4T
497 bool
499 config CPU_ABRT_EV5T
500 bool
502 config CPU_ABRT_EV5TJ
503 bool
505 config CPU_ABRT_EV6
506 bool
508 config CPU_ABRT_EV7
509 bool
511 config CPU_PABRT_LEGACY
512 bool
514 config CPU_PABRT_V6
515 bool
517 config CPU_PABRT_V7
518 bool
520 # The cache model
521 config CPU_CACHE_V4
522 bool
524 config CPU_CACHE_V4WT
525 bool
527 config CPU_CACHE_V4WB
528 bool
530 config CPU_CACHE_V6
531 bool
533 config CPU_CACHE_V7
534 bool
536 config CPU_CACHE_NOP
537 bool
539 config CPU_CACHE_VIVT
540 bool
542 config CPU_CACHE_VIPT
543 bool
545 config CPU_CACHE_FA
546 bool
548 config CPU_CACHE_V7M
549 bool
551 if MMU
552 # The copy-page model
553 config CPU_COPY_V4WT
554 bool
556 config CPU_COPY_V4WB
557 bool
559 config CPU_COPY_FEROCEON
560 bool
562 config CPU_COPY_FA
563 bool
565 config CPU_COPY_V6
566 bool
568 # This selects the TLB model
569 config CPU_TLB_V4WT
570 bool
571 help
572 ARM Architecture Version 4 TLB with writethrough cache.
574 config CPU_TLB_V4WB
575 bool
576 help
577 ARM Architecture Version 4 TLB with writeback cache.
579 config CPU_TLB_V4WBI
580 bool
581 help
582 ARM Architecture Version 4 TLB with writeback cache and invalidate
583 instruction cache entry.
585 config CPU_TLB_FEROCEON
586 bool
587 help
588 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
590 config CPU_TLB_FA
591 bool
592 help
593 Faraday ARM FA526 architecture, unified TLB with writeback cache
594 and invalidate instruction cache entry. Branch target buffer is
595 also supported.
597 config CPU_TLB_V6
598 bool
600 config CPU_TLB_V7
601 bool
603 config VERIFY_PERMISSION_FAULT
604 bool
605 endif
607 config CPU_HAS_ASID
608 bool
609 help
610 This indicates whether the CPU has the ASID register; used to
611 tag TLB and possibly cache entries.
613 config CPU_CP15
614 bool
615 help
616 Processor has the CP15 register.
618 config CPU_CP15_MMU
619 bool
620 select CPU_CP15
621 help
622 Processor has the CP15 register, which has MMU related registers.
624 config CPU_CP15_MPU
625 bool
626 select CPU_CP15
627 help
628 Processor has the CP15 register, which has MPU related registers.
630 config CPU_USE_DOMAINS
631 bool
632 help
633 This option enables or disables the use of domain switching
634 via the set_fs() function.
636 config CPU_V7M_NUM_IRQ
637 int "Number of external interrupts connected to the NVIC"
638 depends on CPU_V7M
639 default 90 if ARCH_STM32
640 default 38 if ARCH_EFM32
641 default 112 if SOC_VF610
642 default 240
643 help
644 This option indicates the number of interrupts connected to the NVIC.
645 The value can be larger than the real number of interrupts supported
646 by the system, but must not be lower.
647 The default value is 240, corresponding to the maximum number of
648 interrupts supported by the NVIC on Cortex-M family.
650 If unsure, keep default value.
652 #
653 # CPU supports 36-bit I/O
654 #
655 config IO_36
656 bool
658 comment "Processor Features"
660 config ARM_LPAE
661 bool "Support for the Large Physical Address Extension"
662 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
663 !CPU_32v4 && !CPU_32v3
664 help
665 Say Y if you have an ARMv7 processor supporting the LPAE page
666 table format and you would like to access memory beyond the
667 4GB limit. The resulting kernel image will not run on
668 processors without the LPA extension.
670 If unsure, say N.
672 config ARM_PV_FIXUP
673 def_bool y
674 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
676 config ARCH_PHYS_ADDR_T_64BIT
677 def_bool ARM_LPAE
679 config ARCH_DMA_ADDR_T_64BIT
680 bool
682 config ARM_THUMB
683 bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
684 depends on CPU_THUMB_CAPABLE
685 default y
686 help
687 Say Y if you want to include kernel support for running user space
688 Thumb binaries.
690 The Thumb instruction set is a compressed form of the standard ARM
691 instruction set resulting in smaller binaries at the expense of
692 slightly less efficient code.
694 If this option is disabled, and you run userspace that switches to
695 Thumb mode, signal handling will not work correctly, resulting in
696 segmentation faults or illegal instruction aborts.
698 If you don't know what this all is, saying Y is a safe choice.
700 config ARM_THUMBEE
701 bool "Enable ThumbEE CPU extension"
702 depends on CPU_V7
703 help
704 Say Y here if you have a CPU with the ThumbEE extension and code to
705 make use of it. Say N for code that can run on CPUs without ThumbEE.
707 config ARM_VIRT_EXT
708 bool
709 depends on MMU
710 default y if CPU_V7
711 help
712 Enable the kernel to make use of the ARM Virtualization
713 Extensions to install hypervisors without run-time firmware
714 assistance.
716 A compliant bootloader is required in order to make maximum
717 use of this feature. Refer to Documentation/arm/Booting for
718 details.
720 config SWP_EMULATE
721 bool "Emulate SWP/SWPB instructions" if !SMP
722 depends on CPU_V7
723 default y if SMP
724 select HAVE_PROC_CPU if PROC_FS
725 help
726 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
727 ARMv7 multiprocessing extensions introduce the ability to disable
728 these instructions, triggering an undefined instruction exception
729 when executed. Say Y here to enable software emulation of these
730 instructions for userspace (not kernel) using LDREX/STREX.
731 Also creates /proc/cpu/swp_emulation for statistics.
733 In some older versions of glibc [<=2.8] SWP is used during futex
734 trylock() operations with the assumption that the code will not
735 be preempted. This invalid assumption may be more likely to fail
736 with SWP emulation enabled, leading to deadlock of the user
737 application.
739 NOTE: when accessing uncached shared regions, LDREX/STREX rely
740 on an external transaction monitoring block called a global
741 monitor to maintain update atomicity. If your system does not
742 implement a global monitor, this option can cause programs that
743 perform SWP operations to uncached memory to deadlock.
745 If unsure, say Y.
747 config CPU_BIG_ENDIAN
748 bool "Build big-endian kernel"
749 depends on ARCH_SUPPORTS_BIG_ENDIAN
750 help
751 Say Y if you plan on running a kernel in big-endian mode.
752 Note that your board must be properly built and your board
753 port must properly enable any big-endian related features
754 of your chipset/board/processor.
756 config CPU_ENDIAN_BE8
757 bool
758 depends on CPU_BIG_ENDIAN
759 default CPU_V6 || CPU_V6K || CPU_V7
760 help
761 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
763 config CPU_ENDIAN_BE32
764 bool
765 depends on CPU_BIG_ENDIAN
766 default !CPU_ENDIAN_BE8
767 help
768 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
770 config CPU_HIGH_VECTOR
771 depends on !MMU && CPU_CP15 && !CPU_ARM740T
772 bool "Select the High exception vector"
773 help
774 Say Y here to select high exception vector(0xFFFF0000~).
775 The exception vector can vary depending on the platform
776 design in nommu mode. If your platform needs to select
777 high exception vector, say Y.
778 Otherwise or if you are unsure, say N, and the low exception
779 vector (0x00000000~) will be used.
781 config CPU_ICACHE_DISABLE
782 bool "Disable I-Cache (I-bit)"
783 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
784 help
785 Say Y here to disable the processor instruction cache. Unless
786 you have a reason not to or are unsure, say N.
788 config CPU_DCACHE_DISABLE
789 bool "Disable D-Cache (C-bit)"
790 depends on (CPU_CP15 && !SMP) || CPU_V7M
791 help
792 Say Y here to disable the processor data cache. Unless
793 you have a reason not to or are unsure, say N.
795 config CPU_DCACHE_SIZE
796 hex
797 depends on CPU_ARM740T || CPU_ARM946E
798 default 0x00001000 if CPU_ARM740T
799 default 0x00002000 # default size for ARM946E-S
800 help
801 Some cores are synthesizable to have various sized cache. For
802 ARM946E-S case, it can vary from 0KB to 1MB.
803 To support such cache operations, it is efficient to know the size
804 before compile time.
805 If your SoC is configured to have a different size, define the value
806 here with proper conditions.
808 config CPU_DCACHE_WRITETHROUGH
809 bool "Force write through D-cache"
810 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
811 default y if CPU_ARM925T
812 help
813 Say Y here to use the data cache in writethrough mode. Unless you
814 specifically require this or are unsure, say N.
816 config CPU_CACHE_ROUND_ROBIN
817 bool "Round robin I and D cache replacement algorithm"
818 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
819 help
820 Say Y here to use the predictable round-robin cache replacement
821 policy. Unless you specifically require this or are unsure, say N.
823 config CPU_BPREDICT_DISABLE
824 bool "Disable branch prediction"
825 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
826 help
827 Say Y here to disable branch prediction. If unsure, say N.
829 config TLS_REG_EMUL
830 bool
831 select NEED_KUSER_HELPERS
832 help
833 An SMP system using a pre-ARMv6 processor (there are apparently
834 a few prototypes like that in existence) and therefore access to
835 that required register must be emulated.
837 config NEED_KUSER_HELPERS
838 bool
840 config KUSER_HELPERS
841 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
842 depends on MMU
843 default y
844 help
845 Warning: disabling this option may break user programs.
847 Provide kuser helpers in the vector page. The kernel provides
848 helper code to userspace in read only form at a fixed location
849 in the high vector page to allow userspace to be independent of
850 the CPU type fitted to the system. This permits binaries to be
851 run on ARMv4 through to ARMv7 without modification.
853 See Documentation/arm/kernel_user_helpers.txt for details.
855 However, the fixed address nature of these helpers can be used
856 by ROP (return orientated programming) authors when creating
857 exploits.
859 If all of the binaries and libraries which run on your platform
860 are built specifically for your platform, and make no use of
861 these helpers, then you can turn this option off to hinder
862 such exploits. However, in that case, if a binary or library
863 relying on those helpers is run, it will receive a SIGILL signal,
864 which will terminate the program.
866 Say N here only if you are absolutely certain that you do not
867 need these helpers; otherwise, the safe option is to say Y.
869 config VDSO
870 bool "Enable VDSO for acceleration of some system calls"
871 depends on AEABI && MMU && CPU_V7
872 default y if ARM_ARCH_TIMER
873 select GENERIC_TIME_VSYSCALL
874 help
875 Place in the process address space an ELF shared object
876 providing fast implementations of gettimeofday and
877 clock_gettime. Systems that implement the ARM architected
878 timer will receive maximum benefit.
880 You must have glibc 2.22 or later for programs to seamlessly
881 take advantage of this.
883 config DMA_CACHE_RWFO
884 bool "Enable read/write for ownership DMA cache maintenance"
885 depends on CPU_V6K && SMP
886 default y
887 help
888 The Snoop Control Unit on ARM11MPCore does not detect the
889 cache maintenance operations and the dma_{map,unmap}_area()
890 functions may leave stale cache entries on other CPUs. By
891 enabling this option, Read or Write For Ownership in the ARMv6
892 DMA cache maintenance functions is performed. These LDR/STR
893 instructions change the cache line state to shared or modified
894 so that the cache operation has the desired effect.
896 Note that the workaround is only valid on processors that do
897 not perform speculative loads into the D-cache. For such
898 processors, if cache maintenance operations are not broadcast
899 in hardware, other workarounds are needed (e.g. cache
900 maintenance broadcasting in software via FIQ).
902 config OUTER_CACHE
903 bool
905 config OUTER_CACHE_SYNC
906 bool
907 select ARM_HEAVY_MB
908 help
909 The outer cache has a outer_cache_fns.sync function pointer
910 that can be used to drain the write buffer of the outer cache.
912 config CACHE_B15_RAC
913 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
914 depends on ARCH_BRCMSTB
915 default y
916 help
917 This option enables the Broadcom Brahma-B15 read-ahead cache
918 controller. If disabled, the read-ahead cache remains off.
920 config CACHE_FEROCEON_L2
921 bool "Enable the Feroceon L2 cache controller"
922 depends on ARCH_MV78XX0 || ARCH_MVEBU
923 default y
924 select OUTER_CACHE
925 help
926 This option enables the Feroceon L2 cache controller.
928 config CACHE_FEROCEON_L2_WRITETHROUGH
929 bool "Force Feroceon L2 cache write through"
930 depends on CACHE_FEROCEON_L2
931 help
932 Say Y here to use the Feroceon L2 cache in writethrough mode.
933 Unless you specifically require this, say N for writeback mode.
935 config MIGHT_HAVE_CACHE_L2X0
936 bool
937 help
938 This option should be selected by machines which have a L2x0
939 or PL310 cache controller, but where its use is optional.
941 The only effect of this option is to make CACHE_L2X0 and
942 related options available to the user for configuration.
944 Boards or SoCs which always require the cache controller
945 support to be present should select CACHE_L2X0 directly
946 instead of this option, thus preventing the user from
947 inadvertently configuring a broken kernel.
949 config CACHE_L2X0
950 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
951 default MIGHT_HAVE_CACHE_L2X0
952 select OUTER_CACHE
953 select OUTER_CACHE_SYNC
954 help
955 This option enables the L2x0 PrimeCell.
957 config CACHE_L2X0_PMU
958 bool "L2x0 performance monitor support" if CACHE_L2X0
959 depends on PERF_EVENTS
960 help
961 This option enables support for the performance monitoring features
962 of the L220 and PL310 outer cache controllers.
964 if CACHE_L2X0
966 config PL310_ERRATA_588369
967 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
968 help
969 The PL310 L2 cache controller implements three types of Clean &
970 Invalidate maintenance operations: by Physical Address
971 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
972 They are architecturally defined to behave as the execution of a
973 clean operation followed immediately by an invalidate operation,
974 both performing to the same memory location. This functionality
975 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
976 as clean lines are not invalidated as a result of these operations.
978 config PL310_ERRATA_727915
979 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
980 help
981 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
982 operation (offset 0x7FC). This operation runs in background so that
983 PL310 can handle normal accesses while it is in progress. Under very
984 rare circumstances, due to this erratum, write data can be lost when
985 PL310 treats a cacheable write transaction during a Clean &
986 Invalidate by Way operation. Revisions prior to r3p1 are affected by
987 this errata (fixed in r3p1).
989 config PL310_ERRATA_753970
990 bool "PL310 errata: cache sync operation may be faulty"
991 help
992 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
994 Under some condition the effect of cache sync operation on
995 the store buffer still remains when the operation completes.
996 This means that the store buffer is always asked to drain and
997 this prevents it from merging any further writes. The workaround
998 is to replace the normal offset of cache sync operation (0x730)
999 by another offset targeting an unmapped PL310 register 0x740.
1000 This has the same effect as the cache sync operation: store buffer
1001 drain and waiting for all buffers empty.
1003 config PL310_ERRATA_769419
1004 bool "PL310 errata: no automatic Store Buffer drain"
1005 help
1006 On revisions of the PL310 prior to r3p2, the Store Buffer does
1007 not automatically drain. This can cause normal, non-cacheable
1008 writes to be retained when the memory system is idle, leading
1009 to suboptimal I/O performance for drivers using coherent DMA.
1010 This option adds a write barrier to the cpu_idle loop so that,
1011 on systems with an outer cache, the store buffer is drained
1012 explicitly.
1014 endif
1016 config CACHE_TAUROS2
1017 bool "Enable the Tauros2 L2 cache controller"
1018 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
1019 default y
1020 select OUTER_CACHE
1021 help
1022 This option enables the Tauros2 L2 cache controller (as
1023 found on PJ1/PJ4).
1025 config CACHE_UNIPHIER
1026 bool "Enable the UniPhier outer cache controller"
1027 depends on ARCH_UNIPHIER
1028 select ARM_L1_CACHE_SHIFT_7
1029 select OUTER_CACHE
1030 select OUTER_CACHE_SYNC
1031 help
1032 This option enables the UniPhier outer cache (system cache)
1033 controller.
1035 config CACHE_XSC3L2
1036 bool "Enable the L2 cache on XScale3"
1037 depends on CPU_XSC3
1038 default y
1039 select OUTER_CACHE
1040 help
1041 This option enables the L2 cache on XScale3.
1043 config ARM_L1_CACHE_SHIFT_6
1044 bool
1045 default y if CPU_V7
1046 help
1047 Setting ARM L1 cache line size to 64 Bytes.
1049 config ARM_L1_CACHE_SHIFT_7
1050 bool
1051 help
1052 Setting ARM L1 cache line size to 128 Bytes.
1054 config ARM_L1_CACHE_SHIFT
1055 int
1056 default 7 if ARM_L1_CACHE_SHIFT_7
1057 default 6 if ARM_L1_CACHE_SHIFT_6
1058 default 5
1060 config ARM_DMA_MEM_BUFFERABLE
1061 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1062 default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
1063 help
1064 Historically, the kernel has used strongly ordered mappings to
1065 provide DMA coherent memory. With the advent of ARMv7, mapping
1066 memory with differing types results in unpredictable behaviour,
1067 so on these CPUs, this option is forced on.
1069 Multiple mappings with differing attributes is also unpredictable
1070 on ARMv6 CPUs, but since they do not have aggressive speculative
1071 prefetch, no harm appears to occur.
1073 However, drivers may be missing the necessary barriers for ARMv6,
1074 and therefore turning this on may result in unpredictable driver
1075 behaviour. Therefore, we offer this as an option.
1077 On some of the beefier ARMv7-M machines (with DMA and write
1078 buffers) you likely want this enabled, while those that
1079 didn't need it until now also won't need it in the future.
1081 You are recommended say 'Y' here and debug any affected drivers.
1083 config ARM_HEAVY_MB
1084 bool
1086 config ARCH_SUPPORTS_BIG_ENDIAN
1087 bool
1088 help
1089 This option specifies the architecture can support big endian
1090 operation.
1092 config DEBUG_ALIGN_RODATA
1093 bool "Make rodata strictly non-executable"
1094 depends on STRICT_KERNEL_RWX
1095 default y
1096 help
1097 If this is set, rodata will be made explicitly non-executable. This
1098 provides protection on the rare chance that attackers might find and
1099 use ROP gadgets that exist in the rodata section. This adds an
1100 additional section-aligned split of rodata from kernel text so it
1101 can be made explicitly non-executable. This padding may waste memory
1102 space to gain the additional protection.