| blob | d55d493f9a1e7056a57dc26c4db20e64c6e6cced |
1 /*
2 * linux/arch/arm/mm/proc-v7.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This is the "shell" of the ARMv7 processor support.
11 */
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
19 #include <asm/memory.h>
21 #include "proc-macros.S"
23 #ifdef CONFIG_ARM_LPAE
24 #include "proc-v7-3level.S"
25 #else
26 #include "proc-v7-2level.S"
27 #endif
29 ENTRY(cpu_v7_proc_init)
30 ret lr
31 ENDPROC(cpu_v7_proc_init)
33 ENTRY(cpu_v7_proc_fin)
34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 bic r0, r0, #0x1000 @ ...i............
36 bic r0, r0, #0x0006 @ .............ca.
37 mcr p15, 0, r0, c1, c0, 0 @ disable caches
38 ret lr
39 ENDPROC(cpu_v7_proc_fin)
41 /*
42 * cpu_v7_reset(loc, hyp)
43 *
44 * Perform a soft reset of the system. Put the CPU into the
45 * same state as it would be if it had been reset, and branch
46 * to what would be the reset vector.
47 *
48 * - loc - location to jump to for soft reset
49 * - hyp - indicate if restart occurs in HYP mode
50 *
51 * This code must be executed using a flat identity mapping with
52 * caches disabled.
53 */
54 .align 5
55 .pushsection .idmap.text, "ax"
56 ENTRY(cpu_v7_reset)
57 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
58 bic r2, r2, #0x1 @ ...............m
59 THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
60 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
61 isb
62 #ifdef CONFIG_ARM_VIRT_EXT
63 teq r1, #0
64 bne __hyp_soft_restart
65 #endif
66 bx r0
67 ENDPROC(cpu_v7_reset)
68 .popsection
70 /*
71 * cpu_v7_do_idle()
72 *
73 * Idle the processor (eg, wait for interrupt).
74 *
75 * IRQs are already disabled.
76 */
77 ENTRY(cpu_v7_do_idle)
78 dsb @ WFI may enter a low-power mode
79 wfi
80 ret lr
81 ENDPROC(cpu_v7_do_idle)
83 ENTRY(cpu_v7_dcache_clean_area)
84 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
85 ALT_UP_B(1f)
86 ret lr
87 1: dcache_line_size r2, r3
88 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
89 add r0, r0, r2
90 subs r1, r1, r2
91 bhi 2b
92 dsb ishst
93 ret lr
94 ENDPROC(cpu_v7_dcache_clean_area)
96 string cpu_v7_name, "ARMv7 Processor"
97 .align
99 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
100 .globl cpu_v7_suspend_size
101 .equ cpu_v7_suspend_size, 4 * 9
102 #ifdef CONFIG_ARM_CPU_SUSPEND
103 ENTRY(cpu_v7_do_suspend)
104 stmfd sp!, {r4 - r11, lr}
105 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
106 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
107 stmia r0!, {r4 - r5}
108 #ifdef CONFIG_MMU
109 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
110 #ifdef CONFIG_ARM_LPAE
111 mrrc p15, 1, r5, r7, c2 @ TTB 1
112 #else
113 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
114 #endif
115 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
116 #endif
117 mrc p15, 0, r8, c1, c0, 0 @ Control register
118 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
119 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
120 stmia r0, {r5 - r11}
121 ldmfd sp!, {r4 - r11, pc}
122 ENDPROC(cpu_v7_do_suspend)
124 ENTRY(cpu_v7_do_resume)
125 mov ip, #0
126 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
128 ldmia r0!, {r4 - r5}
129 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
130 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
131 ldmia r0, {r5 - r11}
132 #ifdef CONFIG_MMU
133 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
134 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
135 #ifdef CONFIG_ARM_LPAE
136 mcrr p15, 0, r1, ip, c2 @ TTB 0
137 mcrr p15, 1, r5, r7, c2 @ TTB 1
138 #else
139 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
140 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
141 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
142 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
143 #endif
144 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
145 ldr r4, =PRRR @ PRRR
146 ldr r5, =NMRR @ NMRR
147 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
148 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
149 #endif /* CONFIG_MMU */
150 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
151 teq r4, r9 @ Is it already set?
152 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
153 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
154 isb
155 dsb
156 mov r0, r8 @ control register
157 b cpu_resume_mmu
158 ENDPROC(cpu_v7_do_resume)
159 #endif
161 /*
162 * Cortex-A8
163 */
164 globl_equ cpu_ca8_proc_init, cpu_v7_proc_init
165 globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin
166 globl_equ cpu_ca8_reset, cpu_v7_reset
167 globl_equ cpu_ca8_do_idle, cpu_v7_do_idle
168 globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
169 globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext
170 globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size
171 #ifdef CONFIG_ARM_CPU_SUSPEND
172 globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend
173 globl_equ cpu_ca8_do_resume, cpu_v7_do_resume
174 #endif
176 /*
177 * Cortex-A9 processor functions
178 */
179 globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
180 globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
181 globl_equ cpu_ca9mp_reset, cpu_v7_reset
182 globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
183 globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
184 globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
185 globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
186 .globl cpu_ca9mp_suspend_size
187 .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
188 #ifdef CONFIG_ARM_CPU_SUSPEND
189 ENTRY(cpu_ca9mp_do_suspend)
190 stmfd sp!, {r4 - r5}
191 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
192 mrc p15, 0, r5, c15, c0, 0 @ Power register
193 stmia r0!, {r4 - r5}
194 ldmfd sp!, {r4 - r5}
195 b cpu_v7_do_suspend
196 ENDPROC(cpu_ca9mp_do_suspend)
198 ENTRY(cpu_ca9mp_do_resume)
199 ldmia r0!, {r4 - r5}
200 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
201 teq r4, r10 @ Already restored?
202 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
203 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
204 teq r5, r10 @ Already restored?
205 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
206 b cpu_v7_do_resume
207 ENDPROC(cpu_ca9mp_do_resume)
208 #endif
210 #ifdef CONFIG_CPU_PJ4B
211 globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
212 globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
213 globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
214 globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
215 globl_equ cpu_pj4b_reset, cpu_v7_reset
216 #ifdef CONFIG_PJ4B_ERRATA_4742
217 ENTRY(cpu_pj4b_do_idle)
218 dsb @ WFI may enter a low-power mode
219 wfi
220 dsb @barrier
221 ret lr
222 ENDPROC(cpu_pj4b_do_idle)
223 #else
224 globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
225 #endif
226 globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
227 #ifdef CONFIG_ARM_CPU_SUSPEND
228 ENTRY(cpu_pj4b_do_suspend)
229 stmfd sp!, {r6 - r10}
230 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
231 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
232 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
233 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
234 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
235 stmia r0!, {r6 - r10}
236 ldmfd sp!, {r6 - r10}
237 b cpu_v7_do_suspend
238 ENDPROC(cpu_pj4b_do_suspend)
240 ENTRY(cpu_pj4b_do_resume)
241 ldmia r0!, {r6 - r10}
242 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
243 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
244 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
245 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
246 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
247 b cpu_v7_do_resume
248 ENDPROC(cpu_pj4b_do_resume)
249 #endif
250 .globl cpu_pj4b_suspend_size
251 .equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
253 #endif
255 /*
256 * __v7_setup
257 *
258 * Initialise TLB, Caches, and MMU state ready to switch the MMU
259 * on. Return in r0 the new CP15 C1 control register setting.
260 *
261 * r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
262 * r4: TTBR0 (low word)
263 * r5: TTBR0 (high word if LPAE)
264 * r8: TTBR1
265 * r9: Main ID register
266 *
267 * This should be able to cover all ARMv7 cores.
268 *
269 * It is assumed that:
270 * - cache type register is implemented
271 */
272 __v7_ca5mp_setup:
273 __v7_ca9mp_setup:
274 __v7_cr7mp_setup:
275 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
276 b 1f
277 __v7_ca7mp_setup:
278 __v7_ca12mp_setup:
279 __v7_ca15mp_setup:
280 __v7_b15mp_setup:
281 __v7_ca17mp_setup:
282 mov r10, #0
283 1: adr r0, __v7_setup_stack_ptr
284 ldr r12, [r0]
285 add r12, r12, r0 @ the local stack
286 stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6
287 bl v7_invalidate_l1
288 ldmia r12, {r1-r6, lr}
289 #ifdef CONFIG_SMP
290 orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode
291 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
292 ALT_UP(mov r0, r10) @ fake it for UP
293 orr r10, r10, r0 @ Set required bits
294 teq r10, r0 @ Were they already set?
295 mcrne p15, 0, r10, c1, c0, 1 @ No, update register
296 #endif
297 b __v7_setup_cont
299 /*
300 * Errata:
301 * r0, r10 available for use
302 * r1, r2, r4, r5, r9, r13: must be preserved
303 * r3: contains MIDR rX number in bits 23-20
304 * r6: contains MIDR rXpY as 8-bit XY number
305 * r9: MIDR
306 */
307 __ca8_errata:
308 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
309 teq r3, #0x00100000 @ only present in r1p*
310 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
311 orreq r0, r0, #(1 << 6) @ set IBE to 1
312 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
313 #endif
314 #ifdef CONFIG_ARM_ERRATA_458693
315 teq r6, #0x20 @ only present in r2p0
316 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
317 orreq r0, r0, #(1 << 5) @ set L1NEON to 1
318 orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
319 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
320 #endif
321 #ifdef CONFIG_ARM_ERRATA_460075
322 teq r6, #0x20 @ only present in r2p0
323 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
324 tsteq r0, #1 << 22
325 orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
326 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
327 #endif
328 b __errata_finish
330 __ca9_errata:
331 #ifdef CONFIG_ARM_ERRATA_742230
332 cmp r6, #0x22 @ only present up to r2p2
333 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
334 orrle r0, r0, #1 << 4 @ set bit #4
335 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
336 #endif
337 #ifdef CONFIG_ARM_ERRATA_742231
338 teq r6, #0x20 @ present in r2p0
339 teqne r6, #0x21 @ present in r2p1
340 teqne r6, #0x22 @ present in r2p2
341 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
342 orreq r0, r0, #1 << 12 @ set bit #12
343 orreq r0, r0, #1 << 22 @ set bit #22
344 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
345 #endif
346 #ifdef CONFIG_ARM_ERRATA_743622
347 teq r3, #0x00200000 @ only present in r2p*
348 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
349 orreq r0, r0, #1 << 6 @ set bit #6
350 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
351 #endif
352 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
353 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
354 ALT_UP_B(1f)
355 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
356 orrlt r0, r0, #1 << 11 @ set bit #11
357 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
358 1:
359 #endif
360 b __errata_finish
362 __ca15_errata:
363 #ifdef CONFIG_ARM_ERRATA_773022
364 cmp r6, #0x4 @ only present up to r0p4
365 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
366 orrle r0, r0, #1 << 1 @ disable loop buffer
367 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
368 #endif
369 b __errata_finish
371 __ca12_errata:
372 #ifdef CONFIG_ARM_ERRATA_818325_852422
373 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
374 orr r10, r10, #1 << 12 @ set bit #12
375 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
376 #endif
377 #ifdef CONFIG_ARM_ERRATA_821420
378 mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
379 orr r10, r10, #1 << 1 @ set bit #1
380 mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
381 #endif
382 #ifdef CONFIG_ARM_ERRATA_825619
383 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
384 orr r10, r10, #1 << 24 @ set bit #24
385 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
386 #endif
387 b __errata_finish
389 __ca17_errata:
390 #ifdef CONFIG_ARM_ERRATA_852421
391 cmp r6, #0x12 @ only present up to r1p2
392 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
393 orrle r10, r10, #1 << 24 @ set bit #24
394 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
395 #endif
396 #ifdef CONFIG_ARM_ERRATA_852423
397 cmp r6, #0x12 @ only present up to r1p2
398 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
399 orrle r10, r10, #1 << 12 @ set bit #12
400 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
401 #endif
402 b __errata_finish
404 __v7_pj4b_setup:
405 #ifdef CONFIG_CPU_PJ4B
407 /* Auxiliary Debug Modes Control 1 Register */
408 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
409 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
410 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
412 /* Auxiliary Debug Modes Control 2 Register */
413 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
414 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
415 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
416 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
417 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
418 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
419 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
421 /* Auxiliary Functional Modes Control Register 0 */
422 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
423 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
424 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
426 /* Auxiliary Debug Modes Control 0 Register */
427 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
429 /* Auxiliary Debug Modes Control 1 Register */
430 mrc p15, 1, r0, c15, c1, 1
431 orr r0, r0, #PJ4B_CLEAN_LINE
432 orr r0, r0, #PJ4B_INTER_PARITY
433 bic r0, r0, #PJ4B_STATIC_BP
434 mcr p15, 1, r0, c15, c1, 1
436 /* Auxiliary Debug Modes Control 2 Register */
437 mrc p15, 1, r0, c15, c1, 2
438 bic r0, r0, #PJ4B_FAST_LDR
439 orr r0, r0, #PJ4B_AUX_DBG_CTRL2
440 mcr p15, 1, r0, c15, c1, 2
442 /* Auxiliary Functional Modes Control Register 0 */
443 mrc p15, 1, r0, c15, c2, 0
444 #ifdef CONFIG_SMP
445 orr r0, r0, #PJ4B_SMP_CFB
446 #endif
447 orr r0, r0, #PJ4B_L1_PAR_CHK
448 orr r0, r0, #PJ4B_BROADCAST_CACHE
449 mcr p15, 1, r0, c15, c2, 0
451 /* Auxiliary Debug Modes Control 0 Register */
452 mrc p15, 1, r0, c15, c1, 0
453 orr r0, r0, #PJ4B_WFI_WFE
454 mcr p15, 1, r0, c15, c1, 0
456 #endif /* CONFIG_CPU_PJ4B */
458 __v7_setup:
459 adr r0, __v7_setup_stack_ptr
460 ldr r12, [r0]
461 add r12, r12, r0 @ the local stack
462 stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6
463 bl v7_invalidate_l1
464 ldmia r12, {r1-r6, lr}
466 __v7_setup_cont:
467 and r0, r9, #0xff000000 @ ARM?
468 teq r0, #0x41000000
469 bne __errata_finish
470 and r3, r9, #0x00f00000 @ variant
471 and r6, r9, #0x0000000f @ revision
472 orr r6, r6, r3, lsr #20-4 @ combine variant and revision
473 ubfx r0, r9, #4, #12 @ primary part number
475 /* Cortex-A8 Errata */
476 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
477 teq r0, r10
478 beq __ca8_errata
480 /* Cortex-A9 Errata */
481 ldr r10, =0x00000c09 @ Cortex-A9 primary part number
482 teq r0, r10
483 beq __ca9_errata
485 /* Cortex-A12 Errata */
486 ldr r10, =0x00000c0d @ Cortex-A12 primary part number
487 teq r0, r10
488 beq __ca12_errata
490 /* Cortex-A17 Errata */
491 ldr r10, =0x00000c0e @ Cortex-A17 primary part number
492 teq r0, r10
493 beq __ca17_errata
495 /* Cortex-A15 Errata */
496 ldr r10, =0x00000c0f @ Cortex-A15 primary part number
497 teq r0, r10
498 beq __ca15_errata
500 __errata_finish:
501 mov r10, #0
502 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
503 #ifdef CONFIG_MMU
504 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
505 v7_ttb_setup r10, r4, r5, r8, r3 @ TTBCR, TTBRx setup
506 ldr r3, =PRRR @ PRRR
507 ldr r6, =NMRR @ NMRR
508 mcr p15, 0, r3, c10, c2, 0 @ write PRRR
509 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
510 #endif
511 dsb @ Complete invalidations
512 #ifndef CONFIG_ARM_THUMBEE
513 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
514 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
515 teq r0, #(1 << 12) @ check if ThumbEE is present
516 bne 1f
517 mov r3, #0
518 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
519 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
520 orr r0, r0, #1 @ set the 1st bit in order to
521 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
522 1:
523 #endif
524 adr r3, v7_crval
525 ldmia r3, {r3, r6}
526 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
527 #ifdef CONFIG_SWP_EMULATE
528 orr r3, r3, #(1 << 10) @ set SW bit in "clear"
529 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
530 #endif
531 mrc p15, 0, r0, c1, c0, 0 @ read control register
532 bic r0, r0, r3 @ clear bits them
533 orr r0, r0, r6 @ set them
534 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
535 ret lr @ return to head.S:__ret
537 .align 2
538 __v7_setup_stack_ptr:
539 .word PHYS_RELATIVE(__v7_setup_stack, .)
540 ENDPROC(__v7_setup)
542 .bss
543 .align 2
544 __v7_setup_stack:
545 .space 4 * 7 @ 7 registers
547 __INITDATA
549 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
550 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
551 #ifndef CONFIG_ARM_LPAE
552 define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
553 define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
554 #endif
555 #ifdef CONFIG_CPU_PJ4B
556 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
557 #endif
559 .section ".rodata"
561 string cpu_arch_name, "armv7"
562 string cpu_elf_name, "v7"
563 .align
565 .section ".proc.info.init", #alloc
567 /*
568 * Standard v7 proc info content
569 */
570 .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions, cache_fns = v7_cache_fns
571 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
572 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
573 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
574 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
575 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
576 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
577 initfn \initfunc, \name
578 .long cpu_arch_name
579 .long cpu_elf_name
580 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
581 HWCAP_EDSP | HWCAP_TLS | \hwcaps
582 .long cpu_v7_name
583 .long \proc_fns
584 .long v7wbi_tlb_fns
585 .long v6_user_fns
586 .long \cache_fns
587 .endm
589 #ifndef CONFIG_ARM_LPAE
590 /*
591 * ARM Ltd. Cortex A5 processor.
592 */
593 .type __v7_ca5mp_proc_info, #object
594 __v7_ca5mp_proc_info:
595 .long 0x410fc050
596 .long 0xff0ffff0
597 __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
598 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
600 /*
601 * ARM Ltd. Cortex A9 processor.
602 */
603 .type __v7_ca9mp_proc_info, #object
604 __v7_ca9mp_proc_info:
605 .long 0x410fc090
606 .long 0xff0ffff0
607 __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
608 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
610 /*
611 * ARM Ltd. Cortex A8 processor.
612 */
613 .type __v7_ca8_proc_info, #object
614 __v7_ca8_proc_info:
615 .long 0x410fc080
616 .long 0xff0ffff0
617 __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
618 .size __v7_ca8_proc_info, . - __v7_ca8_proc_info
620 #endif /* CONFIG_ARM_LPAE */
622 /*
623 * Marvell PJ4B processor.
624 */
625 #ifdef CONFIG_CPU_PJ4B
626 .type __v7_pj4b_proc_info, #object
627 __v7_pj4b_proc_info:
628 .long 0x560f5800
629 .long 0xff0fff00
630 __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
631 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
632 #endif
634 /*
635 * ARM Ltd. Cortex R7 processor.
636 */
637 .type __v7_cr7mp_proc_info, #object
638 __v7_cr7mp_proc_info:
639 .long 0x410fc170
640 .long 0xff0ffff0
641 __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
642 .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
644 /*
645 * ARM Ltd. Cortex A7 processor.
646 */
647 .type __v7_ca7mp_proc_info, #object
648 __v7_ca7mp_proc_info:
649 .long 0x410fc070
650 .long 0xff0ffff0
651 __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
652 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
654 /*
655 * ARM Ltd. Cortex A12 processor.
656 */
657 .type __v7_ca12mp_proc_info, #object
658 __v7_ca12mp_proc_info:
659 .long 0x410fc0d0
660 .long 0xff0ffff0
661 __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup
662 .size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
664 /*
665 * ARM Ltd. Cortex A15 processor.
666 */
667 .type __v7_ca15mp_proc_info, #object
668 __v7_ca15mp_proc_info:
669 .long 0x410fc0f0
670 .long 0xff0ffff0
671 __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup
672 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
674 /*
675 * Broadcom Corporation Brahma-B15 processor.
676 */
677 .type __v7_b15mp_proc_info, #object
678 __v7_b15mp_proc_info:
679 .long 0x420f00f0
680 .long 0xff0ffff0
681 __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, cache_fns = b15_cache_fns
682 .size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
684 /*
685 * ARM Ltd. Cortex A17 processor.
686 */
687 .type __v7_ca17mp_proc_info, #object
688 __v7_ca17mp_proc_info:
689 .long 0x410fc0e0
690 .long 0xff0ffff0
691 __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup
692 .size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
694 /*
695 * Qualcomm Inc. Krait processors.
696 */
697 .type __krait_proc_info, #object
698 __krait_proc_info:
699 .long 0x510f0400 @ Required ID value
700 .long 0xff0ffc00 @ Mask for ID
701 /*
702 * Some Krait processors don't indicate support for SDIV and UDIV
703 * instructions in the ARM instruction set, even though they actually
704 * do support them. They also don't indicate support for fused multiply
705 * instructions even though they actually do support them.
706 */
707 __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
708 .size __krait_proc_info, . - __krait_proc_info
710 /*
711 * Match any ARMv7 processor core.
712 */
713 .type __v7_proc_info, #object
714 __v7_proc_info:
715 .long 0x000f0000 @ Required ID value
716 .long 0x000f0000 @ Mask for ID
717 __v7_proc __v7_proc_info, __v7_setup
718 .size __v7_proc_info, . - __v7_proc_info