| blob | d8ecd16614616fe00fcd293e013f3487db351a2f |
1 /*
2 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
3 *
4 * Copyright (C) 2015, Applied Micro Circuits Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 */
12 / {
13 compatible = "apm,xgene-shadowcat";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
18 cpus {
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu@0 {
23 device_type = "cpu";
24 compatible = "apm,strega", "arm,armv8";
25 reg = <0x0 0x000>;
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
28 next-level-cache = <&xgene_L2_0>;
29 #clock-cells = <1>;
30 clocks = <&pmd0clk 0>;
31 };
32 cpu@1 {
33 device_type = "cpu";
34 compatible = "apm,strega", "arm,armv8";
35 reg = <0x0 0x001>;
36 enable-method = "spin-table";
37 cpu-release-addr = <0x1 0x0000fff8>;
38 next-level-cache = <&xgene_L2_0>;
39 #clock-cells = <1>;
40 clocks = <&pmd0clk 0>;
41 };
42 cpu@100 {
43 device_type = "cpu";
44 compatible = "apm,strega", "arm,armv8";
45 reg = <0x0 0x100>;
46 enable-method = "spin-table";
47 cpu-release-addr = <0x1 0x0000fff8>;
48 next-level-cache = <&xgene_L2_1>;
49 #clock-cells = <1>;
50 clocks = <&pmd1clk 0>;
51 };
52 cpu@101 {
53 device_type = "cpu";
54 compatible = "apm,strega", "arm,armv8";
55 reg = <0x0 0x101>;
56 enable-method = "spin-table";
57 cpu-release-addr = <0x1 0x0000fff8>;
58 next-level-cache = <&xgene_L2_1>;
59 #clock-cells = <1>;
60 clocks = <&pmd1clk 0>;
61 };
62 cpu@200 {
63 device_type = "cpu";
64 compatible = "apm,strega", "arm,armv8";
65 reg = <0x0 0x200>;
66 enable-method = "spin-table";
67 cpu-release-addr = <0x1 0x0000fff8>;
68 next-level-cache = <&xgene_L2_2>;
69 #clock-cells = <1>;
70 clocks = <&pmd2clk 0>;
71 };
72 cpu@201 {
73 device_type = "cpu";
74 compatible = "apm,strega", "arm,armv8";
75 reg = <0x0 0x201>;
76 enable-method = "spin-table";
77 cpu-release-addr = <0x1 0x0000fff8>;
78 next-level-cache = <&xgene_L2_2>;
79 #clock-cells = <1>;
80 clocks = <&pmd2clk 0>;
81 };
82 cpu@300 {
83 device_type = "cpu";
84 compatible = "apm,strega", "arm,armv8";
85 reg = <0x0 0x300>;
86 enable-method = "spin-table";
87 cpu-release-addr = <0x1 0x0000fff8>;
88 next-level-cache = <&xgene_L2_3>;
89 #clock-cells = <1>;
90 clocks = <&pmd3clk 0>;
91 };
92 cpu@301 {
93 device_type = "cpu";
94 compatible = "apm,strega", "arm,armv8";
95 reg = <0x0 0x301>;
96 enable-method = "spin-table";
97 cpu-release-addr = <0x1 0x0000fff8>;
98 next-level-cache = <&xgene_L2_3>;
99 #clock-cells = <1>;
100 clocks = <&pmd3clk 0>;
101 };
102 xgene_L2_0: l2-cache-0 {
103 compatible = "cache";
104 };
105 xgene_L2_1: l2-cache-1 {
106 compatible = "cache";
107 };
108 xgene_L2_2: l2-cache-2 {
109 compatible = "cache";
110 };
111 xgene_L2_3: l2-cache-3 {
112 compatible = "cache";
113 };
114 };
116 gic: interrupt-controller@78090000 {
117 compatible = "arm,cortex-a15-gic";
118 #interrupt-cells = <3>;
119 #address-cells = <2>;
120 #size-cells = <2>;
121 interrupt-controller;
122 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
123 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
124 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
125 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
126 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
127 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
128 v2m0: v2m@0 {
129 compatible = "arm,gic-v2m-frame";
130 msi-controller;
131 reg = <0x0 0x0 0x0 0x1000>;
132 };
133 v2m1: v2m@10000 {
134 compatible = "arm,gic-v2m-frame";
135 msi-controller;
136 reg = <0x0 0x10000 0x0 0x1000>;
137 };
138 v2m2: v2m@20000 {
139 compatible = "arm,gic-v2m-frame";
140 msi-controller;
141 reg = <0x0 0x20000 0x0 0x1000>;
142 };
143 v2m3: v2m@30000 {
144 compatible = "arm,gic-v2m-frame";
145 msi-controller;
146 reg = <0x0 0x30000 0x0 0x1000>;
147 };
148 v2m4: v2m@40000 {
149 compatible = "arm,gic-v2m-frame";
150 msi-controller;
151 reg = <0x0 0x40000 0x0 0x1000>;
152 };
153 v2m5: v2m@50000 {
154 compatible = "arm,gic-v2m-frame";
155 msi-controller;
156 reg = <0x0 0x50000 0x0 0x1000>;
157 };
158 v2m6: v2m@60000 {
159 compatible = "arm,gic-v2m-frame";
160 msi-controller;
161 reg = <0x0 0x60000 0x0 0x1000>;
162 };
163 v2m7: v2m@70000 {
164 compatible = "arm,gic-v2m-frame";
165 msi-controller;
166 reg = <0x0 0x70000 0x0 0x1000>;
167 };
168 v2m8: v2m@80000 {
169 compatible = "arm,gic-v2m-frame";
170 msi-controller;
171 reg = <0x0 0x80000 0x0 0x1000>;
172 };
173 v2m9: v2m@90000 {
174 compatible = "arm,gic-v2m-frame";
175 msi-controller;
176 reg = <0x0 0x90000 0x0 0x1000>;
177 };
178 v2m10: v2m@a0000 {
179 compatible = "arm,gic-v2m-frame";
180 msi-controller;
181 reg = <0x0 0xa0000 0x0 0x1000>;
182 };
183 v2m11: v2m@b0000 {
184 compatible = "arm,gic-v2m-frame";
185 msi-controller;
186 reg = <0x0 0xb0000 0x0 0x1000>;
187 };
188 v2m12: v2m@c0000 {
189 compatible = "arm,gic-v2m-frame";
190 msi-controller;
191 reg = <0x0 0xc0000 0x0 0x1000>;
192 };
193 v2m13: v2m@d0000 {
194 compatible = "arm,gic-v2m-frame";
195 msi-controller;
196 reg = <0x0 0xd0000 0x0 0x1000>;
197 };
198 v2m14: v2m@e0000 {
199 compatible = "arm,gic-v2m-frame";
200 msi-controller;
201 reg = <0x0 0xe0000 0x0 0x1000>;
202 };
203 v2m15: v2m@f0000 {
204 compatible = "arm,gic-v2m-frame";
205 msi-controller;
206 reg = <0x0 0xf0000 0x0 0x1000>;
207 };
208 };
210 pmu {
211 compatible = "arm,armv8-pmuv3";
212 interrupts = <1 12 0xff04>;
213 };
215 timer {
216 compatible = "arm,armv8-timer";
217 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
218 <1 13 0xff08>, /* Non-secure Phys IRQ */
219 <1 14 0xff08>, /* Virt IRQ */
220 <1 15 0xff08>; /* Hyp IRQ */
221 clock-frequency = <50000000>;
222 };
224 soc {
225 compatible = "simple-bus";
226 #address-cells = <2>;
227 #size-cells = <2>;
228 ranges;
230 clocks {
231 #address-cells = <2>;
232 #size-cells = <2>;
233 ranges;
235 refclk: refclk {
236 compatible = "fixed-clock";
237 #clock-cells = <1>;
238 clock-frequency = <100000000>;
239 clock-output-names = "refclk";
240 };
242 pmdpll: pmdpll@170000f0 {
243 compatible = "apm,xgene-pcppll-v2-clock";
244 #clock-cells = <1>;
245 clocks = <&refclk 0>;
246 reg = <0x0 0x170000f0 0x0 0x10>;
247 clock-output-names = "pmdpll";
248 };
250 pmd0clk: pmd0clk@7e200200 {
251 compatible = "apm,xgene-pmd-clock";
252 #clock-cells = <1>;
253 clocks = <&pmdpll 0>;
254 reg = <0x0 0x7e200200 0x0 0x10>;
255 clock-output-names = "pmd0clk";
256 };
258 pmd1clk: pmd1clk@7e200210 {
259 compatible = "apm,xgene-pmd-clock";
260 #clock-cells = <1>;
261 clocks = <&pmdpll 0>;
262 reg = <0x0 0x7e200210 0x0 0x10>;
263 clock-output-names = "pmd1clk";
264 };
266 pmd2clk: pmd2clk@7e200220 {
267 compatible = "apm,xgene-pmd-clock";
268 #clock-cells = <1>;
269 clocks = <&pmdpll 0>;
270 reg = <0x0 0x7e200220 0x0 0x10>;
271 clock-output-names = "pmd2clk";
272 };
274 pmd3clk: pmd3clk@7e200230 {
275 compatible = "apm,xgene-pmd-clock";
276 #clock-cells = <1>;
277 clocks = <&pmdpll 0>;
278 reg = <0x0 0x7e200230 0x0 0x10>;
279 clock-output-names = "pmd3clk";
280 };
282 socpll: socpll@17000120 {
283 compatible = "apm,xgene-socpll-v2-clock";
284 #clock-cells = <1>;
285 clocks = <&refclk 0>;
286 reg = <0x0 0x17000120 0x0 0x1000>;
287 clock-output-names = "socpll";
288 };
290 socplldiv2: socplldiv2 {
291 compatible = "fixed-factor-clock";
292 #clock-cells = <1>;
293 clocks = <&socpll 0>;
294 clock-mult = <1>;
295 clock-div = <2>;
296 clock-output-names = "socplldiv2";
297 };
299 ahbclk: ahbclk@17000000 {
300 compatible = "apm,xgene-device-clock";
301 #clock-cells = <1>;
302 clocks = <&socplldiv2 0>;
303 reg = <0x0 0x17000000 0x0 0x2000>;
304 reg-names = "div-reg";
305 divider-offset = <0x164>;
306 divider-width = <0x5>;
307 divider-shift = <0x0>;
308 clock-output-names = "ahbclk";
309 };
311 sbapbclk: sbapbclk@1704c000 {
312 compatible = "apm,xgene-device-clock";
313 #clock-cells = <1>;
314 clocks = <&ahbclk 0>;
315 reg = <0x0 0x1704c000 0x0 0x2000>;
316 reg-names = "div-reg";
317 divider-offset = <0x10>;
318 divider-width = <0x2>;
319 divider-shift = <0x0>;
320 clock-output-names = "sbapbclk";
321 };
323 sdioclk: sdioclk@1f2ac000 {
324 compatible = "apm,xgene-device-clock";
325 #clock-cells = <1>;
326 clocks = <&socplldiv2 0>;
327 reg = <0x0 0x1f2ac000 0x0 0x1000
328 0x0 0x17000000 0x0 0x2000>;
329 reg-names = "csr-reg", "div-reg";
330 csr-offset = <0x0>;
331 csr-mask = <0x2>;
332 enable-offset = <0x8>;
333 enable-mask = <0x2>;
334 divider-offset = <0x178>;
335 divider-width = <0x8>;
336 divider-shift = <0x0>;
337 clock-output-names = "sdioclk";
338 };
340 pcie0clk: pcie0clk@1f2bc000 {
341 compatible = "apm,xgene-device-clock";
342 #clock-cells = <1>;
343 clocks = <&socplldiv2 0>;
344 reg = <0x0 0x1f2bc000 0x0 0x1000>;
345 reg-names = "csr-reg";
346 clock-output-names = "pcie0clk";
347 };
349 pcie1clk: pcie1clk@1f2cc000 {
350 compatible = "apm,xgene-device-clock";
351 #clock-cells = <1>;
352 clocks = <&socplldiv2 0>;
353 reg = <0x0 0x1f2cc000 0x0 0x1000>;
354 reg-names = "csr-reg";
355 clock-output-names = "pcie1clk";
356 };
358 xge0clk: xge0clk@1f61c000 {
359 compatible = "apm,xgene-device-clock";
360 #clock-cells = <1>;
361 clocks = <&socplldiv2 0>;
362 reg = <0x0 0x1f61c000 0x0 0x1000>;
363 reg-names = "csr-reg";
364 enable-mask = <0x3>;
365 csr-mask = <0x3>;
366 clock-output-names = "xge0clk";
367 };
369 xge1clk: xge1clk@1f62c000 {
370 compatible = "apm,xgene-device-clock";
371 #clock-cells = <1>;
372 clocks = <&socplldiv2 0>;
373 reg = <0x0 0x1f62c000 0x0 0x1000>;
374 reg-names = "csr-reg";
375 enable-mask = <0x3>;
376 csr-mask = <0x3>;
377 clock-output-names = "xge1clk";
378 };
380 rngpkaclk: rngpkaclk@17000000 {
381 compatible = "apm,xgene-device-clock";
382 #clock-cells = <1>;
383 clocks = <&socplldiv2 0>;
384 reg = <0x0 0x17000000 0x0 0x2000>;
385 reg-names = "csr-reg";
386 csr-offset = <0xc>;
387 csr-mask = <0x10>;
388 enable-offset = <0x10>;
389 enable-mask = <0x10>;
390 clock-output-names = "rngpkaclk";
391 };
393 i2c4clk: i2c4clk@1704c000 {
394 compatible = "apm,xgene-device-clock";
395 #clock-cells = <1>;
396 clocks = <&sbapbclk 0>;
397 reg = <0x0 0x1704c000 0x0 0x1000>;
398 reg-names = "csr-reg";
399 csr-offset = <0x0>;
400 csr-mask = <0x40>;
401 enable-offset = <0x8>;
402 enable-mask = <0x40>;
403 clock-output-names = "i2c4clk";
404 };
405 };
407 scu: system-clk-controller@17000000 {
408 compatible = "apm,xgene-scu","syscon";
409 reg = <0x0 0x17000000 0x0 0x400>;
410 };
412 reboot: reboot@17000014 {
413 compatible = "syscon-reboot";
414 regmap = <&scu>;
415 offset = <0x14>;
416 mask = <0x1>;
417 };
419 csw: csw@7e200000 {
420 compatible = "apm,xgene-csw", "syscon";
421 reg = <0x0 0x7e200000 0x0 0x1000>;
422 };
424 mcba: mcba@7e700000 {
425 compatible = "apm,xgene-mcb", "syscon";
426 reg = <0x0 0x7e700000 0x0 0x1000>;
427 };
429 mcbb: mcbb@7e720000 {
430 compatible = "apm,xgene-mcb", "syscon";
431 reg = <0x0 0x7e720000 0x0 0x1000>;
432 };
434 efuse: efuse@1054a000 {
435 compatible = "apm,xgene-efuse", "syscon";
436 reg = <0x0 0x1054a000 0x0 0x20>;
437 };
439 edac@78800000 {
440 compatible = "apm,xgene-edac";
441 #address-cells = <2>;
442 #size-cells = <2>;
443 ranges;
444 regmap-csw = <&csw>;
445 regmap-mcba = <&mcba>;
446 regmap-mcbb = <&mcbb>;
447 regmap-efuse = <&efuse>;
448 reg = <0x0 0x78800000 0x0 0x100>;
449 interrupts = <0x0 0x20 0x4>,
450 <0x0 0x21 0x4>,
451 <0x0 0x27 0x4>;
453 edacmc@7e800000 {
454 compatible = "apm,xgene-edac-mc";
455 reg = <0x0 0x7e800000 0x0 0x1000>;
456 memory-controller = <0>;
457 };
459 edacmc@7e840000 {
460 compatible = "apm,xgene-edac-mc";
461 reg = <0x0 0x7e840000 0x0 0x1000>;
462 memory-controller = <1>;
463 };
465 edacmc@7e880000 {
466 compatible = "apm,xgene-edac-mc";
467 reg = <0x0 0x7e880000 0x0 0x1000>;
468 memory-controller = <2>;
469 };
471 edacmc@7e8c0000 {
472 compatible = "apm,xgene-edac-mc";
473 reg = <0x0 0x7e8c0000 0x0 0x1000>;
474 memory-controller = <3>;
475 };
477 edacpmd@7c000000 {
478 compatible = "apm,xgene-edac-pmd";
479 reg = <0x0 0x7c000000 0x0 0x200000>;
480 pmd-controller = <0>;
481 };
483 edacpmd@7c200000 {
484 compatible = "apm,xgene-edac-pmd";
485 reg = <0x0 0x7c200000 0x0 0x200000>;
486 pmd-controller = <1>;
487 };
489 edacpmd@7c400000 {
490 compatible = "apm,xgene-edac-pmd";
491 reg = <0x0 0x7c400000 0x0 0x200000>;
492 pmd-controller = <2>;
493 };
495 edacpmd@7c600000 {
496 compatible = "apm,xgene-edac-pmd";
497 reg = <0x0 0x7c600000 0x0 0x200000>;
498 pmd-controller = <3>;
499 };
501 edacl3@7e600000 {
502 compatible = "apm,xgene-edac-l3-v2";
503 reg = <0x0 0x7e600000 0x0 0x1000>;
504 };
506 edacsoc@7e930000 {
507 compatible = "apm,xgene-edac-soc";
508 reg = <0x0 0x7e930000 0x0 0x1000>;
509 };
510 };
512 pmu: pmu@78810000 {
513 compatible = "apm,xgene-pmu-v2";
514 #address-cells = <2>;
515 #size-cells = <2>;
516 ranges;
517 regmap-csw = <&csw>;
518 regmap-mcba = <&mcba>;
519 regmap-mcbb = <&mcbb>;
520 reg = <0x0 0x78810000 0x0 0x1000>;
521 interrupts = <0x0 0x22 0x4>;
523 pmul3c@7e610000 {
524 compatible = "apm,xgene-pmu-l3c";
525 reg = <0x0 0x7e610000 0x0 0x1000>;
526 };
528 pmuiob@7e940000 {
529 compatible = "apm,xgene-pmu-iob";
530 reg = <0x0 0x7e940000 0x0 0x1000>;
531 };
533 pmucmcb@7e710000 {
534 compatible = "apm,xgene-pmu-mcb";
535 reg = <0x0 0x7e710000 0x0 0x1000>;
536 enable-bit-index = <0>;
537 };
539 pmucmcb@7e730000 {
540 compatible = "apm,xgene-pmu-mcb";
541 reg = <0x0 0x7e730000 0x0 0x1000>;
542 enable-bit-index = <1>;
543 };
545 pmucmc@7e810000 {
546 compatible = "apm,xgene-pmu-mc";
547 reg = <0x0 0x7e810000 0x0 0x1000>;
548 enable-bit-index = <0>;
549 };
551 pmucmc@7e850000 {
552 compatible = "apm,xgene-pmu-mc";
553 reg = <0x0 0x7e850000 0x0 0x1000>;
554 enable-bit-index = <1>;
555 };
557 pmucmc@7e890000 {
558 compatible = "apm,xgene-pmu-mc";
559 reg = <0x0 0x7e890000 0x0 0x1000>;
560 enable-bit-index = <2>;
561 };
563 pmucmc@7e8d0000 {
564 compatible = "apm,xgene-pmu-mc";
565 reg = <0x0 0x7e8d0000 0x0 0x1000>;
566 enable-bit-index = <3>;
567 };
568 };
570 mailbox: mailbox@10540000 {
571 compatible = "apm,xgene-slimpro-mbox";
572 reg = <0x0 0x10540000 0x0 0x8000>;
573 #mbox-cells = <1>;
574 interrupts = <0x0 0x0 0x4
575 0x0 0x1 0x4
576 0x0 0x2 0x4
577 0x0 0x3 0x4
578 0x0 0x4 0x4
579 0x0 0x5 0x4
580 0x0 0x6 0x4
581 0x0 0x7 0x4>;
582 };
584 i2cslimpro {
585 compatible = "apm,xgene-slimpro-i2c";
586 mboxes = <&mailbox 0>;
587 };
589 hwmonslimpro {
590 compatible = "apm,xgene-slimpro-hwmon";
591 mboxes = <&mailbox 7>;
592 };
594 serial0: serial@10600000 {
595 device_type = "serial";
596 compatible = "ns16550";
597 reg = <0 0x10600000 0x0 0x1000>;
598 reg-shift = <2>;
599 clock-frequency = <10000000>;
600 interrupt-parent = <&gic>;
601 interrupts = <0x0 0x4c 0x4>;
602 };
604 /* Do not change dwusb name, coded for backward compatibility */
605 usb0: dwusb@19000000 {
606 status = "disabled";
607 compatible = "snps,dwc3";
608 reg = <0x0 0x19000000 0x0 0x100000>;
609 interrupts = <0x0 0x5d 0x4>;
610 dma-coherent;
611 dr_mode = "host";
612 };
614 pcie0: pcie@1f2b0000 {
615 status = "disabled";
616 device_type = "pci";
617 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
618 #interrupt-cells = <1>;
619 #size-cells = <2>;
620 #address-cells = <3>;
621 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
622 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
623 reg-names = "csr", "cfg";
624 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
625 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */
626 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
627 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
628 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
629 bus-range = <0x00 0xff>;
630 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
631 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
632 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
633 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
634 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
635 dma-coherent;
636 clocks = <&pcie0clk 0>;
637 msi-parent = <&v2m0>;
638 };
640 pcie1: pcie@1f2c0000 {
641 status = "disabled";
642 device_type = "pci";
643 compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
644 #interrupt-cells = <1>;
645 #size-cells = <2>;
646 #address-cells = <3>;
647 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
648 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
649 reg-names = "csr", "cfg";
650 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
651 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */
652 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
653 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
654 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
655 bus-range = <0x00 0xff>;
656 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
657 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
658 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
659 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
660 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
661 dma-coherent;
662 clocks = <&pcie1clk 0>;
663 msi-parent = <&v2m0>;
664 };
666 sata1: sata@1a000000 {
667 compatible = "apm,xgene-ahci-v2";
668 reg = <0x0 0x1a000000 0x0 0x1000>,
669 <0x0 0x1f200000 0x0 0x1000>,
670 <0x0 0x1f20d000 0x0 0x1000>,
671 <0x0 0x1f20e000 0x0 0x1000>;
672 interrupts = <0x0 0x5a 0x4>;
673 dma-coherent;
674 };
676 sata2: sata@1a200000 {
677 compatible = "apm,xgene-ahci-v2";
678 reg = <0x0 0x1a200000 0x0 0x1000>,
679 <0x0 0x1f210000 0x0 0x1000>,
680 <0x0 0x1f21d000 0x0 0x1000>,
681 <0x0 0x1f21e000 0x0 0x1000>;
682 interrupts = <0x0 0x5b 0x4>;
683 dma-coherent;
684 };
686 sata3: sata@1a400000 {
687 compatible = "apm,xgene-ahci-v2";
688 reg = <0x0 0x1a400000 0x0 0x1000>,
689 <0x0 0x1f220000 0x0 0x1000>,
690 <0x0 0x1f22d000 0x0 0x1000>,
691 <0x0 0x1f22e000 0x0 0x1000>;
692 interrupts = <0x0 0x5c 0x4>;
693 dma-coherent;
694 };
696 mmc0: mmc@1c000000 {
697 compatible = "arasan,sdhci-4.9a";
698 reg = <0x0 0x1c000000 0x0 0x100>;
699 interrupts = <0x0 0x49 0x4>;
700 dma-coherent;
701 no-1-8-v;
702 clock-names = "clk_xin", "clk_ahb";
703 clocks = <&sdioclk 0>, <&ahbclk 0>;
704 };
706 gfcgpio: gpio@1f63c000 {
707 compatible = "apm,xgene-gpio";
708 reg = <0x0 0x1f63c000 0x0 0x40>;
709 gpio-controller;
710 #gpio-cells = <2>;
711 };
713 dwgpio: gpio@1c024000 {
714 compatible = "snps,dw-apb-gpio";
715 reg = <0x0 0x1c024000 0x0 0x1000>;
716 reg-io-width = <4>;
717 #address-cells = <1>;
718 #size-cells = <0>;
720 porta: gpio-controller@0 {
721 compatible = "snps,dw-apb-gpio-port";
722 gpio-controller;
723 snps,nr-gpios = <32>;
724 reg = <0>;
725 };
726 };
728 sbgpio: gpio@17001000{
729 compatible = "apm,xgene-gpio-sb";
730 reg = <0x0 0x17001000 0x0 0x400>;
731 #gpio-cells = <2>;
732 gpio-controller;
733 interrupts = <0x0 0x28 0x1>,
734 <0x0 0x29 0x1>,
735 <0x0 0x2a 0x1>,
736 <0x0 0x2b 0x1>,
737 <0x0 0x2c 0x1>,
738 <0x0 0x2d 0x1>,
739 <0x0 0x2e 0x1>,
740 <0x0 0x2f 0x1>;
741 interrupt-parent = <&gic>;
742 #interrupt-cells = <2>;
743 interrupt-controller;
744 apm,nr-gpios = <22>;
745 apm,nr-irqs = <8>;
746 apm,irq-start = <8>;
747 };
749 mdio: mdio@1f610000 {
750 compatible = "apm,xgene-mdio-xfi";
751 #address-cells = <1>;
752 #size-cells = <0>;
753 reg = <0x0 0x1f610000 0x0 0xd100>;
754 clocks = <&xge0clk 0>;
755 };
757 sgenet0: ethernet@1f610000 {
758 compatible = "apm,xgene2-sgenet";
759 status = "disabled";
760 reg = <0x0 0x1f610000 0x0 0xd100>,
761 <0x0 0x1f600000 0x0 0xd100>,
762 <0x0 0x20000000 0x0 0x20000>;
763 interrupts = <0 96 4>,
764 <0 97 4>;
765 dma-coherent;
766 clocks = <&xge0clk 0>;
767 local-mac-address = [00 01 73 00 00 01];
768 phy-connection-type = "sgmii";
769 phy-handle = <&sgenet0phy>;
770 };
772 xgenet1: ethernet@1f620000 {
773 compatible = "apm,xgene2-xgenet";
774 status = "disabled";
775 reg = <0x0 0x1f620000 0x0 0x10000>,
776 <0x0 0x1f600000 0x0 0xd100>,
777 <0x0 0x20000000 0x0 0x220000>;
778 interrupts = <0 108 4>,
779 <0 109 4>,
780 <0 110 4>,
781 <0 111 4>,
782 <0 112 4>,
783 <0 113 4>,
784 <0 114 4>,
785 <0 115 4>;
786 channel = <12>;
787 port-id = <1>;
788 dma-coherent;
789 clocks = <&xge1clk 0>;
790 local-mac-address = [00 01 73 00 00 02];
791 phy-connection-type = "xgmii";
792 };
794 rng: rng@10520000 {
795 compatible = "apm,xgene-rng";
796 reg = <0x0 0x10520000 0x0 0x100>;
797 interrupts = <0x0 0x41 0x4>;
798 clocks = <&rngpkaclk 0>;
799 };
801 i2c1: i2c@10511000 {
802 #address-cells = <1>;
803 #size-cells = <0>;
804 compatible = "snps,designware-i2c";
805 reg = <0x0 0x10511000 0x0 0x1000>;
806 interrupts = <0 0x45 0x4>;
807 #clock-cells = <1>;
808 clocks = <&sbapbclk 0>;
809 bus_num = <1>;
810 };
812 i2c4: i2c@10640000 {
813 #address-cells = <1>;
814 #size-cells = <0>;
815 compatible = "snps,designware-i2c";
816 reg = <0x0 0x10640000 0x0 0x1000>;
817 interrupts = <0 0x3a 0x4>;
818 clocks = <&i2c4clk 0>;
819 bus_num = <4>;
820 };
821 };
822 };