| blob | 00e82b8e9a19bef6865bb34b7b991c1de6a2006a |
1 /*
2 * dts file for AppliedMicro (APM) X-Gene Storm SOC
3 *
4 * Copyright (C) 2013, Applied Micro Circuits Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 */
12 / {
13 compatible = "apm,xgene-storm";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
18 cpus {
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu@0 {
23 device_type = "cpu";
24 compatible = "apm,potenza", "arm,armv8";
25 reg = <0x0 0x000>;
26 enable-method = "spin-table";
27 cpu-release-addr = <0x1 0x0000fff8>;
28 next-level-cache = <&xgene_L2_0>;
29 };
30 cpu@1 {
31 device_type = "cpu";
32 compatible = "apm,potenza", "arm,armv8";
33 reg = <0x0 0x001>;
34 enable-method = "spin-table";
35 cpu-release-addr = <0x1 0x0000fff8>;
36 next-level-cache = <&xgene_L2_0>;
37 };
38 cpu@100 {
39 device_type = "cpu";
40 compatible = "apm,potenza", "arm,armv8";
41 reg = <0x0 0x100>;
42 enable-method = "spin-table";
43 cpu-release-addr = <0x1 0x0000fff8>;
44 next-level-cache = <&xgene_L2_1>;
45 };
46 cpu@101 {
47 device_type = "cpu";
48 compatible = "apm,potenza", "arm,armv8";
49 reg = <0x0 0x101>;
50 enable-method = "spin-table";
51 cpu-release-addr = <0x1 0x0000fff8>;
52 next-level-cache = <&xgene_L2_1>;
53 };
54 cpu@200 {
55 device_type = "cpu";
56 compatible = "apm,potenza", "arm,armv8";
57 reg = <0x0 0x200>;
58 enable-method = "spin-table";
59 cpu-release-addr = <0x1 0x0000fff8>;
60 next-level-cache = <&xgene_L2_2>;
61 };
62 cpu@201 {
63 device_type = "cpu";
64 compatible = "apm,potenza", "arm,armv8";
65 reg = <0x0 0x201>;
66 enable-method = "spin-table";
67 cpu-release-addr = <0x1 0x0000fff8>;
68 next-level-cache = <&xgene_L2_2>;
69 };
70 cpu@300 {
71 device_type = "cpu";
72 compatible = "apm,potenza", "arm,armv8";
73 reg = <0x0 0x300>;
74 enable-method = "spin-table";
75 cpu-release-addr = <0x1 0x0000fff8>;
76 next-level-cache = <&xgene_L2_3>;
77 };
78 cpu@301 {
79 device_type = "cpu";
80 compatible = "apm,potenza", "arm,armv8";
81 reg = <0x0 0x301>;
82 enable-method = "spin-table";
83 cpu-release-addr = <0x1 0x0000fff8>;
84 next-level-cache = <&xgene_L2_3>;
85 };
86 xgene_L2_0: l2-cache-0 {
87 compatible = "cache";
88 };
89 xgene_L2_1: l2-cache-1 {
90 compatible = "cache";
91 };
92 xgene_L2_2: l2-cache-2 {
93 compatible = "cache";
94 };
95 xgene_L2_3: l2-cache-3 {
96 compatible = "cache";
97 };
98 };
100 gic: interrupt-controller@78010000 {
101 compatible = "arm,cortex-a15-gic";
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
105 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
106 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
107 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
108 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
109 };
111 timer {
112 compatible = "arm,armv8-timer";
113 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
114 <1 13 0xff08>, /* Non-secure Phys IRQ */
115 <1 14 0xff08>, /* Virt IRQ */
116 <1 15 0xff08>; /* Hyp IRQ */
117 clock-frequency = <50000000>;
118 };
120 pmu {
121 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
122 interrupts = <1 12 0xff04>;
123 };
125 soc {
126 compatible = "simple-bus";
127 #address-cells = <2>;
128 #size-cells = <2>;
129 ranges;
130 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
132 clocks {
133 #address-cells = <2>;
134 #size-cells = <2>;
135 ranges;
136 refclk: refclk {
137 compatible = "fixed-clock";
138 #clock-cells = <1>;
139 clock-frequency = <100000000>;
140 clock-output-names = "refclk";
141 };
143 pcppll: pcppll@17000100 {
144 compatible = "apm,xgene-pcppll-clock";
145 #clock-cells = <1>;
146 clocks = <&refclk 0>;
147 clock-names = "pcppll";
148 reg = <0x0 0x17000100 0x0 0x1000>;
149 clock-output-names = "pcppll";
150 type = <0>;
151 };
153 socpll: socpll@17000120 {
154 compatible = "apm,xgene-socpll-clock";
155 #clock-cells = <1>;
156 clocks = <&refclk 0>;
157 clock-names = "socpll";
158 reg = <0x0 0x17000120 0x0 0x1000>;
159 clock-output-names = "socpll";
160 type = <1>;
161 };
163 socplldiv2: socplldiv2 {
164 compatible = "fixed-factor-clock";
165 #clock-cells = <1>;
166 clocks = <&socpll 0>;
167 clock-names = "socplldiv2";
168 clock-mult = <1>;
169 clock-div = <2>;
170 clock-output-names = "socplldiv2";
171 };
173 ahbclk: ahbclk@17000000 {
174 compatible = "apm,xgene-device-clock";
175 #clock-cells = <1>;
176 clocks = <&socplldiv2 0>;
177 reg = <0x0 0x17000000 0x0 0x2000>;
178 reg-names = "div-reg";
179 divider-offset = <0x164>;
180 divider-width = <0x5>;
181 divider-shift = <0x0>;
182 clock-output-names = "ahbclk";
183 };
185 sdioclk: sdioclk@1f2ac000 {
186 compatible = "apm,xgene-device-clock";
187 #clock-cells = <1>;
188 clocks = <&socplldiv2 0>;
189 reg = <0x0 0x1f2ac000 0x0 0x1000
190 0x0 0x17000000 0x0 0x2000>;
191 reg-names = "csr-reg", "div-reg";
192 csr-offset = <0x0>;
193 csr-mask = <0x2>;
194 enable-offset = <0x8>;
195 enable-mask = <0x2>;
196 divider-offset = <0x178>;
197 divider-width = <0x8>;
198 divider-shift = <0x0>;
199 clock-output-names = "sdioclk";
200 };
202 ethclk: ethclk {
203 compatible = "apm,xgene-device-clock";
204 #clock-cells = <1>;
205 clocks = <&socplldiv2 0>;
206 clock-names = "ethclk";
207 reg = <0x0 0x17000000 0x0 0x1000>;
208 reg-names = "div-reg";
209 divider-offset = <0x238>;
210 divider-width = <0x9>;
211 divider-shift = <0x0>;
212 clock-output-names = "ethclk";
213 };
215 menetclk: menetclk {
216 compatible = "apm,xgene-device-clock";
217 #clock-cells = <1>;
218 clocks = <ðclk 0>;
219 reg = <0x0 0x1702c000 0x0 0x1000>;
220 reg-names = "csr-reg";
221 clock-output-names = "menetclk";
222 };
224 sge0clk: sge0clk@1f21c000 {
225 compatible = "apm,xgene-device-clock";
226 #clock-cells = <1>;
227 clocks = <&socplldiv2 0>;
228 reg = <0x0 0x1f21c000 0x0 0x1000>;
229 reg-names = "csr-reg";
230 csr-mask = <0xa>;
231 enable-mask = <0xf>;
232 clock-output-names = "sge0clk";
233 };
235 xge0clk: xge0clk@1f61c000 {
236 compatible = "apm,xgene-device-clock";
237 #clock-cells = <1>;
238 clocks = <&socplldiv2 0>;
239 reg = <0x0 0x1f61c000 0x0 0x1000>;
240 reg-names = "csr-reg";
241 csr-mask = <0x3>;
242 clock-output-names = "xge0clk";
243 };
245 xge1clk: xge1clk@1f62c000 {
246 compatible = "apm,xgene-device-clock";
247 status = "disabled";
248 #clock-cells = <1>;
249 clocks = <&socplldiv2 0>;
250 reg = <0x0 0x1f62c000 0x0 0x1000>;
251 reg-names = "csr-reg";
252 csr-mask = <0x3>;
253 clock-output-names = "xge1clk";
254 };
256 sataphy1clk: sataphy1clk@1f21c000 {
257 compatible = "apm,xgene-device-clock";
258 #clock-cells = <1>;
259 clocks = <&socplldiv2 0>;
260 reg = <0x0 0x1f21c000 0x0 0x1000>;
261 reg-names = "csr-reg";
262 clock-output-names = "sataphy1clk";
263 status = "disabled";
264 csr-offset = <0x4>;
265 csr-mask = <0x00>;
266 enable-offset = <0x0>;
267 enable-mask = <0x06>;
268 };
270 sataphy2clk: sataphy1clk@1f22c000 {
271 compatible = "apm,xgene-device-clock";
272 #clock-cells = <1>;
273 clocks = <&socplldiv2 0>;
274 reg = <0x0 0x1f22c000 0x0 0x1000>;
275 reg-names = "csr-reg";
276 clock-output-names = "sataphy2clk";
277 status = "ok";
278 csr-offset = <0x4>;
279 csr-mask = <0x3a>;
280 enable-offset = <0x0>;
281 enable-mask = <0x06>;
282 };
284 sataphy3clk: sataphy1clk@1f23c000 {
285 compatible = "apm,xgene-device-clock";
286 #clock-cells = <1>;
287 clocks = <&socplldiv2 0>;
288 reg = <0x0 0x1f23c000 0x0 0x1000>;
289 reg-names = "csr-reg";
290 clock-output-names = "sataphy3clk";
291 status = "ok";
292 csr-offset = <0x4>;
293 csr-mask = <0x3a>;
294 enable-offset = <0x0>;
295 enable-mask = <0x06>;
296 };
298 sata01clk: sata01clk@1f21c000 {
299 compatible = "apm,xgene-device-clock";
300 #clock-cells = <1>;
301 clocks = <&socplldiv2 0>;
302 reg = <0x0 0x1f21c000 0x0 0x1000>;
303 reg-names = "csr-reg";
304 clock-output-names = "sata01clk";
305 csr-offset = <0x4>;
306 csr-mask = <0x05>;
307 enable-offset = <0x0>;
308 enable-mask = <0x39>;
309 };
311 sata23clk: sata23clk@1f22c000 {
312 compatible = "apm,xgene-device-clock";
313 #clock-cells = <1>;
314 clocks = <&socplldiv2 0>;
315 reg = <0x0 0x1f22c000 0x0 0x1000>;
316 reg-names = "csr-reg";
317 clock-output-names = "sata23clk";
318 csr-offset = <0x4>;
319 csr-mask = <0x05>;
320 enable-offset = <0x0>;
321 enable-mask = <0x39>;
322 };
324 sata45clk: sata45clk@1f23c000 {
325 compatible = "apm,xgene-device-clock";
326 #clock-cells = <1>;
327 clocks = <&socplldiv2 0>;
328 reg = <0x0 0x1f23c000 0x0 0x1000>;
329 reg-names = "csr-reg";
330 clock-output-names = "sata45clk";
331 csr-offset = <0x4>;
332 csr-mask = <0x05>;
333 enable-offset = <0x0>;
334 enable-mask = <0x39>;
335 };
337 rtcclk: rtcclk@17000000 {
338 compatible = "apm,xgene-device-clock";
339 #clock-cells = <1>;
340 clocks = <&socplldiv2 0>;
341 reg = <0x0 0x17000000 0x0 0x2000>;
342 reg-names = "csr-reg";
343 csr-offset = <0xc>;
344 csr-mask = <0x2>;
345 enable-offset = <0x10>;
346 enable-mask = <0x2>;
347 clock-output-names = "rtcclk";
348 };
350 rngpkaclk: rngpkaclk@17000000 {
351 compatible = "apm,xgene-device-clock";
352 #clock-cells = <1>;
353 clocks = <&socplldiv2 0>;
354 reg = <0x0 0x17000000 0x0 0x2000>;
355 reg-names = "csr-reg";
356 csr-offset = <0xc>;
357 csr-mask = <0x10>;
358 enable-offset = <0x10>;
359 enable-mask = <0x10>;
360 clock-output-names = "rngpkaclk";
361 };
363 pcie0clk: pcie0clk@1f2bc000 {
364 status = "disabled";
365 compatible = "apm,xgene-device-clock";
366 #clock-cells = <1>;
367 clocks = <&socplldiv2 0>;
368 reg = <0x0 0x1f2bc000 0x0 0x1000>;
369 reg-names = "csr-reg";
370 clock-output-names = "pcie0clk";
371 };
373 pcie1clk: pcie1clk@1f2cc000 {
374 status = "disabled";
375 compatible = "apm,xgene-device-clock";
376 #clock-cells = <1>;
377 clocks = <&socplldiv2 0>;
378 reg = <0x0 0x1f2cc000 0x0 0x1000>;
379 reg-names = "csr-reg";
380 clock-output-names = "pcie1clk";
381 };
383 pcie2clk: pcie2clk@1f2dc000 {
384 status = "disabled";
385 compatible = "apm,xgene-device-clock";
386 #clock-cells = <1>;
387 clocks = <&socplldiv2 0>;
388 reg = <0x0 0x1f2dc000 0x0 0x1000>;
389 reg-names = "csr-reg";
390 clock-output-names = "pcie2clk";
391 };
393 pcie3clk: pcie3clk@1f50c000 {
394 status = "disabled";
395 compatible = "apm,xgene-device-clock";
396 #clock-cells = <1>;
397 clocks = <&socplldiv2 0>;
398 reg = <0x0 0x1f50c000 0x0 0x1000>;
399 reg-names = "csr-reg";
400 clock-output-names = "pcie3clk";
401 };
403 pcie4clk: pcie4clk@1f51c000 {
404 status = "disabled";
405 compatible = "apm,xgene-device-clock";
406 #clock-cells = <1>;
407 clocks = <&socplldiv2 0>;
408 reg = <0x0 0x1f51c000 0x0 0x1000>;
409 reg-names = "csr-reg";
410 clock-output-names = "pcie4clk";
411 };
413 dmaclk: dmaclk@1f27c000 {
414 compatible = "apm,xgene-device-clock";
415 #clock-cells = <1>;
416 clocks = <&socplldiv2 0>;
417 reg = <0x0 0x1f27c000 0x0 0x1000>;
418 reg-names = "csr-reg";
419 clock-output-names = "dmaclk";
420 };
421 };
423 msi: msi@79000000 {
424 compatible = "apm,xgene1-msi";
425 msi-controller;
426 reg = <0x00 0x79000000 0x0 0x900000>;
427 interrupts = < 0x0 0x10 0x4
428 0x0 0x11 0x4
429 0x0 0x12 0x4
430 0x0 0x13 0x4
431 0x0 0x14 0x4
432 0x0 0x15 0x4
433 0x0 0x16 0x4
434 0x0 0x17 0x4
435 0x0 0x18 0x4
436 0x0 0x19 0x4
437 0x0 0x1a 0x4
438 0x0 0x1b 0x4
439 0x0 0x1c 0x4
440 0x0 0x1d 0x4
441 0x0 0x1e 0x4
442 0x0 0x1f 0x4>;
443 };
445 scu: system-clk-controller@17000000 {
446 compatible = "apm,xgene-scu","syscon";
447 reg = <0x0 0x17000000 0x0 0x400>;
448 };
450 reboot: reboot@17000014 {
451 compatible = "syscon-reboot";
452 regmap = <&scu>;
453 offset = <0x14>;
454 mask = <0x1>;
455 };
457 csw: csw@7e200000 {
458 compatible = "apm,xgene-csw", "syscon";
459 reg = <0x0 0x7e200000 0x0 0x1000>;
460 };
462 mcba: mcba@7e700000 {
463 compatible = "apm,xgene-mcb", "syscon";
464 reg = <0x0 0x7e700000 0x0 0x1000>;
465 };
467 mcbb: mcbb@7e720000 {
468 compatible = "apm,xgene-mcb", "syscon";
469 reg = <0x0 0x7e720000 0x0 0x1000>;
470 };
472 efuse: efuse@1054a000 {
473 compatible = "apm,xgene-efuse", "syscon";
474 reg = <0x0 0x1054a000 0x0 0x20>;
475 };
477 rb: rb@7e000000 {
478 compatible = "apm,xgene-rb", "syscon";
479 reg = <0x0 0x7e000000 0x0 0x10>;
480 };
482 edac@78800000 {
483 compatible = "apm,xgene-edac";
484 #address-cells = <2>;
485 #size-cells = <2>;
486 ranges;
487 regmap-csw = <&csw>;
488 regmap-mcba = <&mcba>;
489 regmap-mcbb = <&mcbb>;
490 regmap-efuse = <&efuse>;
491 regmap-rb = <&rb>;
492 reg = <0x0 0x78800000 0x0 0x100>;
493 interrupts = <0x0 0x20 0x4>,
494 <0x0 0x21 0x4>,
495 <0x0 0x27 0x4>;
497 edacmc@7e800000 {
498 compatible = "apm,xgene-edac-mc";
499 reg = <0x0 0x7e800000 0x0 0x1000>;
500 memory-controller = <0>;
501 };
503 edacmc@7e840000 {
504 compatible = "apm,xgene-edac-mc";
505 reg = <0x0 0x7e840000 0x0 0x1000>;
506 memory-controller = <1>;
507 };
509 edacmc@7e880000 {
510 compatible = "apm,xgene-edac-mc";
511 reg = <0x0 0x7e880000 0x0 0x1000>;
512 memory-controller = <2>;
513 };
515 edacmc@7e8c0000 {
516 compatible = "apm,xgene-edac-mc";
517 reg = <0x0 0x7e8c0000 0x0 0x1000>;
518 memory-controller = <3>;
519 };
521 edacpmd@7c000000 {
522 compatible = "apm,xgene-edac-pmd";
523 reg = <0x0 0x7c000000 0x0 0x200000>;
524 pmd-controller = <0>;
525 };
527 edacpmd@7c200000 {
528 compatible = "apm,xgene-edac-pmd";
529 reg = <0x0 0x7c200000 0x0 0x200000>;
530 pmd-controller = <1>;
531 };
533 edacpmd@7c400000 {
534 compatible = "apm,xgene-edac-pmd";
535 reg = <0x0 0x7c400000 0x0 0x200000>;
536 pmd-controller = <2>;
537 };
539 edacpmd@7c600000 {
540 compatible = "apm,xgene-edac-pmd";
541 reg = <0x0 0x7c600000 0x0 0x200000>;
542 pmd-controller = <3>;
543 };
545 edacl3@7e600000 {
546 compatible = "apm,xgene-edac-l3";
547 reg = <0x0 0x7e600000 0x0 0x1000>;
548 };
550 edacsoc@7e930000 {
551 compatible = "apm,xgene-edac-soc-v1";
552 reg = <0x0 0x7e930000 0x0 0x1000>;
553 };
554 };
556 pmu: pmu@78810000 {
557 compatible = "apm,xgene-pmu-v2";
558 #address-cells = <2>;
559 #size-cells = <2>;
560 ranges;
561 regmap-csw = <&csw>;
562 regmap-mcba = <&mcba>;
563 regmap-mcbb = <&mcbb>;
564 reg = <0x0 0x78810000 0x0 0x1000>;
565 interrupts = <0x0 0x22 0x4>;
567 pmul3c@7e610000 {
568 compatible = "apm,xgene-pmu-l3c";
569 reg = <0x0 0x7e610000 0x0 0x1000>;
570 };
572 pmuiob@7e940000 {
573 compatible = "apm,xgene-pmu-iob";
574 reg = <0x0 0x7e940000 0x0 0x1000>;
575 };
577 pmucmcb@7e710000 {
578 compatible = "apm,xgene-pmu-mcb";
579 reg = <0x0 0x7e710000 0x0 0x1000>;
580 enable-bit-index = <0>;
581 };
583 pmucmcb@7e730000 {
584 compatible = "apm,xgene-pmu-mcb";
585 reg = <0x0 0x7e730000 0x0 0x1000>;
586 enable-bit-index = <1>;
587 };
589 pmucmc@7e810000 {
590 compatible = "apm,xgene-pmu-mc";
591 reg = <0x0 0x7e810000 0x0 0x1000>;
592 enable-bit-index = <0>;
593 };
595 pmucmc@7e850000 {
596 compatible = "apm,xgene-pmu-mc";
597 reg = <0x0 0x7e850000 0x0 0x1000>;
598 enable-bit-index = <1>;
599 };
601 pmucmc@7e890000 {
602 compatible = "apm,xgene-pmu-mc";
603 reg = <0x0 0x7e890000 0x0 0x1000>;
604 enable-bit-index = <2>;
605 };
607 pmucmc@7e8d0000 {
608 compatible = "apm,xgene-pmu-mc";
609 reg = <0x0 0x7e8d0000 0x0 0x1000>;
610 enable-bit-index = <3>;
611 };
612 };
614 pcie0: pcie@1f2b0000 {
615 status = "disabled";
616 device_type = "pci";
617 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
618 #interrupt-cells = <1>;
619 #size-cells = <2>;
620 #address-cells = <3>;
621 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
622 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
623 reg-names = "csr", "cfg";
624 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
625 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
626 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
627 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
628 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
629 bus-range = <0x00 0xff>;
630 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
631 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
632 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
633 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
634 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
635 dma-coherent;
636 clocks = <&pcie0clk 0>;
637 msi-parent = <&msi>;
638 };
640 pcie1: pcie@1f2c0000 {
641 status = "disabled";
642 device_type = "pci";
643 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
644 #interrupt-cells = <1>;
645 #size-cells = <2>;
646 #address-cells = <3>;
647 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
648 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
649 reg-names = "csr", "cfg";
650 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
651 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
652 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
653 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
654 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
655 bus-range = <0x00 0xff>;
656 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
657 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
658 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
659 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
660 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
661 dma-coherent;
662 clocks = <&pcie1clk 0>;
663 msi-parent = <&msi>;
664 };
666 pcie2: pcie@1f2d0000 {
667 status = "disabled";
668 device_type = "pci";
669 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
670 #interrupt-cells = <1>;
671 #size-cells = <2>;
672 #address-cells = <3>;
673 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
674 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
675 reg-names = "csr", "cfg";
676 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
677 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
678 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
679 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
680 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
681 bus-range = <0x00 0xff>;
682 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
683 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
684 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
685 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
686 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
687 dma-coherent;
688 clocks = <&pcie2clk 0>;
689 msi-parent = <&msi>;
690 };
692 pcie3: pcie@1f500000 {
693 status = "disabled";
694 device_type = "pci";
695 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
696 #interrupt-cells = <1>;
697 #size-cells = <2>;
698 #address-cells = <3>;
699 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
700 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
701 reg-names = "csr", "cfg";
702 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
703 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
704 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
705 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
706 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
707 bus-range = <0x00 0xff>;
708 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
709 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
710 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
711 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
712 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
713 dma-coherent;
714 clocks = <&pcie3clk 0>;
715 msi-parent = <&msi>;
716 };
718 pcie4: pcie@1f510000 {
719 status = "disabled";
720 device_type = "pci";
721 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
722 #interrupt-cells = <1>;
723 #size-cells = <2>;
724 #address-cells = <3>;
725 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
726 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
727 reg-names = "csr", "cfg";
728 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
729 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
730 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
731 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
732 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
733 bus-range = <0x00 0xff>;
734 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
735 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
736 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
737 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
738 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
739 dma-coherent;
740 clocks = <&pcie4clk 0>;
741 msi-parent = <&msi>;
742 };
744 mailbox: mailbox@10540000 {
745 compatible = "apm,xgene-slimpro-mbox";
746 reg = <0x0 0x10540000 0x0 0xa000>;
747 #mbox-cells = <1>;
748 interrupts = <0x0 0x0 0x4>,
749 <0x0 0x1 0x4>,
750 <0x0 0x2 0x4>,
751 <0x0 0x3 0x4>,
752 <0x0 0x4 0x4>,
753 <0x0 0x5 0x4>,
754 <0x0 0x6 0x4>,
755 <0x0 0x7 0x4>;
756 };
758 i2cslimpro {
759 compatible = "apm,xgene-slimpro-i2c";
760 mboxes = <&mailbox 0>;
761 };
763 hwmonslimpro {
764 compatible = "apm,xgene-slimpro-hwmon";
765 mboxes = <&mailbox 7>;
766 };
768 serial0: serial@1c020000 {
769 status = "disabled";
770 device_type = "serial";
771 compatible = "ns16550a";
772 reg = <0 0x1c020000 0x0 0x1000>;
773 reg-shift = <2>;
774 clock-frequency = <10000000>; /* Updated by bootloader */
775 interrupt-parent = <&gic>;
776 interrupts = <0x0 0x4c 0x4>;
777 };
779 serial1: serial@1c021000 {
780 status = "disabled";
781 device_type = "serial";
782 compatible = "ns16550a";
783 reg = <0 0x1c021000 0x0 0x1000>;
784 reg-shift = <2>;
785 clock-frequency = <10000000>; /* Updated by bootloader */
786 interrupt-parent = <&gic>;
787 interrupts = <0x0 0x4d 0x4>;
788 };
790 serial2: serial@1c022000 {
791 status = "disabled";
792 device_type = "serial";
793 compatible = "ns16550a";
794 reg = <0 0x1c022000 0x0 0x1000>;
795 reg-shift = <2>;
796 clock-frequency = <10000000>; /* Updated by bootloader */
797 interrupt-parent = <&gic>;
798 interrupts = <0x0 0x4e 0x4>;
799 };
801 serial3: serial@1c023000 {
802 status = "disabled";
803 device_type = "serial";
804 compatible = "ns16550a";
805 reg = <0 0x1c023000 0x0 0x1000>;
806 reg-shift = <2>;
807 clock-frequency = <10000000>; /* Updated by bootloader */
808 interrupt-parent = <&gic>;
809 interrupts = <0x0 0x4f 0x4>;
810 };
812 mmc0: mmc@1c000000 {
813 compatible = "arasan,sdhci-4.9a";
814 reg = <0x0 0x1c000000 0x0 0x100>;
815 interrupts = <0x0 0x49 0x4>;
816 dma-coherent;
817 no-1-8-v;
818 clock-names = "clk_xin", "clk_ahb";
819 clocks = <&sdioclk 0>, <&ahbclk 0>;
820 };
822 gfcgpio: gpio0@1701c000 {
823 compatible = "apm,xgene-gpio";
824 reg = <0x0 0x1701c000 0x0 0x40>;
825 gpio-controller;
826 #gpio-cells = <2>;
827 };
829 dwgpio: gpio@1c024000 {
830 compatible = "snps,dw-apb-gpio";
831 reg = <0x0 0x1c024000 0x0 0x1000>;
832 reg-io-width = <4>;
833 #address-cells = <1>;
834 #size-cells = <0>;
836 porta: gpio-controller@0 {
837 compatible = "snps,dw-apb-gpio-port";
838 gpio-controller;
839 snps,nr-gpios = <32>;
840 reg = <0>;
841 };
842 };
844 i2c0: i2c@10512000 {
845 status = "disabled";
846 #address-cells = <1>;
847 #size-cells = <0>;
848 compatible = "snps,designware-i2c";
849 reg = <0x0 0x10512000 0x0 0x1000>;
850 interrupts = <0 0x44 0x4>;
851 #clock-cells = <1>;
852 clocks = <&ahbclk 0>;
853 bus_num = <0>;
854 };
856 phy1: phy@1f21a000 {
857 compatible = "apm,xgene-phy";
858 reg = <0x0 0x1f21a000 0x0 0x100>;
859 #phy-cells = <1>;
860 clocks = <&sataphy1clk 0>;
861 status = "disabled";
862 apm,tx-boost-gain = <30 30 30 30 30 30>;
863 apm,tx-eye-tuning = <2 10 10 2 10 10>;
864 };
866 phy2: phy@1f22a000 {
867 compatible = "apm,xgene-phy";
868 reg = <0x0 0x1f22a000 0x0 0x100>;
869 #phy-cells = <1>;
870 clocks = <&sataphy2clk 0>;
871 status = "ok";
872 apm,tx-boost-gain = <30 30 30 30 30 30>;
873 apm,tx-eye-tuning = <1 10 10 2 10 10>;
874 };
876 phy3: phy@1f23a000 {
877 compatible = "apm,xgene-phy";
878 reg = <0x0 0x1f23a000 0x0 0x100>;
879 #phy-cells = <1>;
880 clocks = <&sataphy3clk 0>;
881 status = "ok";
882 apm,tx-boost-gain = <31 31 31 31 31 31>;
883 apm,tx-eye-tuning = <2 10 10 2 10 10>;
884 };
886 sata1: sata@1a000000 {
887 compatible = "apm,xgene-ahci";
888 reg = <0x0 0x1a000000 0x0 0x1000>,
889 <0x0 0x1f210000 0x0 0x1000>,
890 <0x0 0x1f21d000 0x0 0x1000>,
891 <0x0 0x1f21e000 0x0 0x1000>,
892 <0x0 0x1f217000 0x0 0x1000>;
893 interrupts = <0x0 0x86 0x4>;
894 dma-coherent;
895 status = "disabled";
896 clocks = <&sata01clk 0>;
897 phys = <&phy1 0>;
898 phy-names = "sata-phy";
899 };
901 sata2: sata@1a400000 {
902 compatible = "apm,xgene-ahci";
903 reg = <0x0 0x1a400000 0x0 0x1000>,
904 <0x0 0x1f220000 0x0 0x1000>,
905 <0x0 0x1f22d000 0x0 0x1000>,
906 <0x0 0x1f22e000 0x0 0x1000>,
907 <0x0 0x1f227000 0x0 0x1000>;
908 interrupts = <0x0 0x87 0x4>;
909 dma-coherent;
910 status = "ok";
911 clocks = <&sata23clk 0>;
912 phys = <&phy2 0>;
913 phy-names = "sata-phy";
914 };
916 sata3: sata@1a800000 {
917 compatible = "apm,xgene-ahci";
918 reg = <0x0 0x1a800000 0x0 0x1000>,
919 <0x0 0x1f230000 0x0 0x1000>,
920 <0x0 0x1f23d000 0x0 0x1000>,
921 <0x0 0x1f23e000 0x0 0x1000>;
922 interrupts = <0x0 0x88 0x4>;
923 dma-coherent;
924 status = "ok";
925 clocks = <&sata45clk 0>;
926 phys = <&phy3 0>;
927 phy-names = "sata-phy";
928 };
930 /* Do not change dwusb name, coded for backward compatibility */
931 usb0: dwusb@19000000 {
932 status = "disabled";
933 compatible = "snps,dwc3";
934 reg = <0x0 0x19000000 0x0 0x100000>;
935 interrupts = <0x0 0x89 0x4>;
936 dma-coherent;
937 dr_mode = "host";
938 };
940 usb1: dwusb@19800000 {
941 status = "disabled";
942 compatible = "snps,dwc3";
943 reg = <0x0 0x19800000 0x0 0x100000>;
944 interrupts = <0x0 0x8a 0x4>;
945 dma-coherent;
946 dr_mode = "host";
947 };
949 sbgpio: gpio@17001000{
950 compatible = "apm,xgene-gpio-sb";
951 reg = <0x0 0x17001000 0x0 0x400>;
952 #gpio-cells = <2>;
953 gpio-controller;
954 interrupts = <0x0 0x28 0x1>,
955 <0x0 0x29 0x1>,
956 <0x0 0x2a 0x1>,
957 <0x0 0x2b 0x1>,
958 <0x0 0x2c 0x1>,
959 <0x0 0x2d 0x1>;
960 interrupt-parent = <&gic>;
961 #interrupt-cells = <2>;
962 interrupt-controller;
963 };
965 rtc: rtc@10510000 {
966 compatible = "apm,xgene-rtc";
967 reg = <0x0 0x10510000 0x0 0x400>;
968 interrupts = <0x0 0x46 0x4>;
969 #clock-cells = <1>;
970 clocks = <&rtcclk 0>;
971 };
973 mdio: mdio@17020000 {
974 compatible = "apm,xgene-mdio-rgmii";
975 #address-cells = <1>;
976 #size-cells = <0>;
977 reg = <0x0 0x17020000 0x0 0xd100>;
978 clocks = <&menetclk 0>;
979 };
981 menet: ethernet@17020000 {
982 compatible = "apm,xgene-enet";
983 status = "disabled";
984 reg = <0x0 0x17020000 0x0 0xd100>,
985 <0x0 0x17030000 0x0 0xc300>,
986 <0x0 0x10000000 0x0 0x200>;
987 reg-names = "enet_csr", "ring_csr", "ring_cmd";
988 interrupts = <0x0 0x3c 0x4>;
989 dma-coherent;
990 clocks = <&menetclk 0>;
991 /* mac address will be overwritten by the bootloader */
992 local-mac-address = [00 00 00 00 00 00];
993 phy-connection-type = "rgmii";
994 phy-handle = <&menetphy>,<&menet0phy>;
995 mdio {
996 compatible = "apm,xgene-mdio";
997 #address-cells = <1>;
998 #size-cells = <0>;
999 menetphy: menetphy@3 {
1000 compatible = "ethernet-phy-id001c.c915";
1001 reg = <0x3>;
1002 };
1004 };
1005 };
1007 sgenet0: ethernet@1f210000 {
1008 compatible = "apm,xgene1-sgenet";
1009 status = "disabled";
1010 reg = <0x0 0x1f210000 0x0 0xd100>,
1011 <0x0 0x1f200000 0x0 0xc300>,
1012 <0x0 0x1b000000 0x0 0x200>;
1013 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1014 interrupts = <0x0 0xa0 0x4>,
1015 <0x0 0xa1 0x4>;
1016 dma-coherent;
1017 clocks = <&sge0clk 0>;
1018 local-mac-address = [00 00 00 00 00 00];
1019 phy-connection-type = "sgmii";
1020 phy-handle = <&sgenet0phy>;
1021 };
1023 sgenet1: ethernet@1f210030 {
1024 compatible = "apm,xgene1-sgenet";
1025 status = "disabled";
1026 reg = <0x0 0x1f210030 0x0 0xd100>,
1027 <0x0 0x1f200000 0x0 0xc300>,
1028 <0x0 0x1b000000 0x0 0x8000>;
1029 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1030 interrupts = <0x0 0xac 0x4>,
1031 <0x0 0xad 0x4>;
1032 port-id = <1>;
1033 dma-coherent;
1034 local-mac-address = [00 00 00 00 00 00];
1035 phy-connection-type = "sgmii";
1036 phy-handle = <&sgenet1phy>;
1037 };
1039 xgenet: ethernet@1f610000 {
1040 compatible = "apm,xgene1-xgenet";
1041 status = "disabled";
1042 reg = <0x0 0x1f610000 0x0 0xd100>,
1043 <0x0 0x1f600000 0x0 0xc300>,
1044 <0x0 0x18000000 0x0 0x200>;
1045 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1046 interrupts = <0x0 0x60 0x4>,
1047 <0x0 0x61 0x4>,
1048 <0x0 0x62 0x4>,
1049 <0x0 0x63 0x4>,
1050 <0x0 0x64 0x4>,
1051 <0x0 0x65 0x4>,
1052 <0x0 0x66 0x4>,
1053 <0x0 0x67 0x4>;
1054 channel = <0>;
1055 dma-coherent;
1056 clocks = <&xge0clk 0>;
1057 /* mac address will be overwritten by the bootloader */
1058 local-mac-address = [00 00 00 00 00 00];
1059 phy-connection-type = "xgmii";
1060 };
1062 xgenet1: ethernet@1f620000 {
1063 compatible = "apm,xgene1-xgenet";
1064 status = "disabled";
1065 reg = <0x0 0x1f620000 0x0 0xd100>,
1066 <0x0 0x1f600000 0x0 0xc300>,
1067 <0x0 0x18000000 0x0 0x8000>;
1068 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1069 interrupts = <0x0 0x6c 0x4>,
1070 <0x0 0x6d 0x4>;
1071 port-id = <1>;
1072 dma-coherent;
1073 clocks = <&xge1clk 0>;
1074 /* mac address will be overwritten by the bootloader */
1075 local-mac-address = [00 00 00 00 00 00];
1076 phy-connection-type = "xgmii";
1077 };
1079 rng: rng@10520000 {
1080 compatible = "apm,xgene-rng";
1081 reg = <0x0 0x10520000 0x0 0x100>;
1082 interrupts = <0x0 0x41 0x4>;
1083 clocks = <&rngpkaclk 0>;
1084 };
1086 dma: dma@1f270000 {
1087 compatible = "apm,xgene-storm-dma";
1088 device_type = "dma";
1089 reg = <0x0 0x1f270000 0x0 0x10000>,
1090 <0x0 0x1f200000 0x0 0x10000>,
1091 <0x0 0x1b000000 0x0 0x400000>,
1092 <0x0 0x1054a000 0x0 0x100>;
1093 interrupts = <0x0 0x82 0x4>,
1094 <0x0 0xb8 0x4>,
1095 <0x0 0xb9 0x4>,
1096 <0x0 0xba 0x4>,
1097 <0x0 0xbb 0x4>;
1098 dma-coherent;
1099 clocks = <&dmaclk 0>;
1100 };
1101 };
1102 };