| blob | 99aaff0b6d72b6bc971863411b80caa3dd165048 |
1 /*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
35 / {
36 compatible = "brcm,stingray";
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
41 cpus {
42 #address-cells = <2>;
43 #size-cells = <0>;
45 cpu@0 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a72", "arm,armv8";
48 reg = <0x0 0x0>;
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
51 };
53 cpu@1 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a72", "arm,armv8";
56 reg = <0x0 0x1>;
57 enable-method = "psci";
58 next-level-cache = <&CLUSTER0_L2>;
59 };
61 cpu@100 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a72", "arm,armv8";
64 reg = <0x0 0x100>;
65 enable-method = "psci";
66 next-level-cache = <&CLUSTER1_L2>;
67 };
69 cpu@101 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a72", "arm,armv8";
72 reg = <0x0 0x101>;
73 enable-method = "psci";
74 next-level-cache = <&CLUSTER1_L2>;
75 };
77 cpu@200 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a72", "arm,armv8";
80 reg = <0x0 0x200>;
81 enable-method = "psci";
82 next-level-cache = <&CLUSTER2_L2>;
83 };
85 cpu@201 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a72", "arm,armv8";
88 reg = <0x0 0x201>;
89 enable-method = "psci";
90 next-level-cache = <&CLUSTER2_L2>;
91 };
93 cpu@300 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a72", "arm,armv8";
96 reg = <0x0 0x300>;
97 enable-method = "psci";
98 next-level-cache = <&CLUSTER3_L2>;
99 };
101 cpu@301 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a72", "arm,armv8";
104 reg = <0x0 0x301>;
105 enable-method = "psci";
106 next-level-cache = <&CLUSTER3_L2>;
107 };
109 CLUSTER0_L2: l2-cache@0 {
110 compatible = "cache";
111 };
113 CLUSTER1_L2: l2-cache@100 {
114 compatible = "cache";
115 };
117 CLUSTER2_L2: l2-cache@200 {
118 compatible = "cache";
119 };
121 CLUSTER3_L2: l2-cache@300 {
122 compatible = "cache";
123 };
124 };
126 memory: memory@80000000 {
127 device_type = "memory";
128 reg = <0x00000000 0x80000000 0 0x40000000>;
129 };
131 psci {
132 compatible = "arm,psci-0.2";
133 method = "smc";
134 };
136 pmu {
137 compatible = "arm,armv8-pmuv3";
138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
139 };
141 timer {
142 compatible = "arm,armv8-timer";
143 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
144 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
145 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
146 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
147 };
149 scr {
150 compatible = "simple-bus";
151 #address-cells = <1>;
152 #size-cells = <1>;
153 ranges = <0x0 0x0 0x61000000 0x05000000>;
155 ccn: ccn@0 {
156 compatible = "arm,ccn-502";
157 reg = <0x00000000 0x900000>;
158 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
159 };
161 gic: interrupt-controller@2c00000 {
162 compatible = "arm,gic-v3";
163 #interrupt-cells = <3>;
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges;
167 interrupt-controller;
168 reg = <0x02c00000 0x010000>, /* GICD */
169 <0x02e00000 0x600000>; /* GICR */
170 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
172 gic_its: gic-its@63c20000 {
173 compatible = "arm,gic-v3-its";
174 msi-controller;
175 #msi-cells = <1>;
176 reg = <0x02c20000 0x10000>;
177 };
178 };
180 smmu: mmu@3000000 {
181 compatible = "arm,mmu-500";
182 reg = <0x03000000 0x80000>;
183 #global-interrupts = <1>;
184 interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
249 #iommu-cells = <2>;
250 };
251 };
253 crmu: crmu {
254 compatible = "simple-bus";
255 #address-cells = <1>;
256 #size-cells = <1>;
257 ranges = <0x0 0x0 0x66400000 0x100000>;
259 #include "stingray-clock.dtsi"
261 gpio_crmu: gpio@24800 {
262 compatible = "brcm,iproc-gpio";
263 reg = <0x00024800 0x4c>;
264 ngpios = <6>;
265 #gpio-cells = <2>;
266 gpio-controller;
267 };
268 };
270 #include "stingray-fs4.dtsi"
271 #include "stingray-sata.dtsi"
273 hsls {
274 compatible = "simple-bus";
275 #address-cells = <1>;
276 #size-cells = <1>;
277 ranges = <0x0 0x0 0x68900000 0x17700000>;
279 #include "stingray-pinctrl.dtsi"
281 mdio_mux_iproc: mdio-mux@2023c {
282 compatible = "brcm,mdio-mux-iproc";
283 reg = <0x0002023c 0x14>;
284 #address-cells = <1>;
285 #size-cells = <0>;
287 mdio@0 { /* PCIe serdes */
288 reg = <0x0>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 };
293 mdio@2 { /* SATA */
294 reg = <0x2>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 };
299 mdio@3 { /* USB */
300 reg = <0x3>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 };
305 mdio@10 { /* RGMII */
306 reg = <0x10>;
307 #address-cells = <1>;
308 #size-cells = <0>;
309 };
310 };
312 pwm: pwm@10000 {
313 compatible = "brcm,iproc-pwm";
314 reg = <0x00010000 0x1000>;
315 clocks = <&crmu_ref25m>;
316 #pwm-cells = <3>;
317 status = "disabled";
318 };
320 timer0: timer@30000 {
321 compatible = "arm,sp804", "arm,primecell";
322 reg = <0x00030000 0x1000>;
323 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&hsls_25m_div2_clk>,
325 <&hsls_25m_div2_clk>,
326 <&hsls_div4_clk>;
327 clock-names = "timer1", "timer2", "apb_pclk";
328 status = "disabled";
329 };
331 timer1: timer@40000 {
332 compatible = "arm,sp804", "arm,primecell";
333 reg = <0x00040000 0x1000>;
334 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&hsls_25m_div2_clk>,
336 <&hsls_25m_div2_clk>,
337 <&hsls_div4_clk>;
338 clock-names = "timer1", "timer2", "apb_pclk";
339 };
341 timer2: timer@50000 {
342 compatible = "arm,sp804", "arm,primecell";
343 reg = <0x00050000 0x1000>;
344 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&hsls_25m_div2_clk>,
346 <&hsls_25m_div2_clk>,
347 <&hsls_div4_clk>;
348 clock-names = "timer1", "timer2", "apb_pclk";
349 status = "disabled";
350 };
352 timer3: timer@60000 {
353 compatible = "arm,sp804", "arm,primecell";
354 reg = <0x00060000 0x1000>;
355 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&hsls_25m_div2_clk>,
357 <&hsls_25m_div2_clk>,
358 <&hsls_div4_clk>;
359 clock-names = "timer1", "timer2", "apb_pclk";
360 status = "disabled";
361 };
363 timer4: timer@70000 {
364 compatible = "arm,sp804", "arm,primecell";
365 reg = <0x00070000 0x1000>;
366 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&hsls_25m_div2_clk>,
368 <&hsls_25m_div2_clk>,
369 <&hsls_div4_clk>;
370 clock-names = "timer1", "timer2", "apb_pclk";
371 status = "disabled";
372 };
374 timer5: timer@80000 {
375 compatible = "arm,sp804", "arm,primecell";
376 reg = <0x00080000 0x1000>;
377 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&hsls_25m_div2_clk>,
379 <&hsls_25m_div2_clk>,
380 <&hsls_div4_clk>;
381 clock-names = "timer1", "timer2", "apb_pclk";
382 status = "disabled";
383 };
385 timer6: timer@90000 {
386 compatible = "arm,sp804", "arm,primecell";
387 reg = <0x00090000 0x1000>;
388 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&hsls_25m_div2_clk>,
390 <&hsls_25m_div2_clk>,
391 <&hsls_div4_clk>;
392 clock-names = "timer1", "timer2", "apb_pclk";
393 status = "disabled";
394 };
396 timer7: timer@a0000 {
397 compatible = "arm,sp804", "arm,primecell";
398 reg = <0x000a0000 0x1000>;
399 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&hsls_25m_div2_clk>,
401 <&hsls_25m_div2_clk>,
402 <&hsls_div4_clk>;
403 clock-names = "timer1", "timer2", "apb_pclk";
404 status = "disabled";
405 };
407 i2c0: i2c@b0000 {
408 compatible = "brcm,iproc-i2c";
409 reg = <0x000b0000 0x100>;
410 #address-cells = <1>;
411 #size-cells = <0>;
412 interrupts = <GIC_SPI 177 IRQ_TYPE_NONE>;
413 clock-frequency = <100000>;
414 status = "disabled";
415 };
417 wdt0: watchdog@c0000 {
418 compatible = "arm,sp805", "arm,primecell";
419 reg = <0x000c0000 0x1000>;
420 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
422 clock-names = "wdogclk", "apb_pclk";
423 };
425 gpio_hsls: gpio@d0000 {
426 compatible = "brcm,iproc-gpio";
427 reg = <0x000d0000 0x864>;
428 ngpios = <151>;
429 #gpio-cells = <2>;
430 gpio-controller;
431 interrupt-controller;
432 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
433 gpio-ranges = <&pinmux 0 0 16>,
434 <&pinmux 16 71 2>,
435 <&pinmux 18 131 8>,
436 <&pinmux 26 83 6>,
437 <&pinmux 32 123 4>,
438 <&pinmux 36 43 24>,
439 <&pinmux 60 89 2>,
440 <&pinmux 62 73 4>,
441 <&pinmux 66 95 28>,
442 <&pinmux 94 127 4>,
443 <&pinmux 98 139 10>,
444 <&pinmux 108 16 27>,
445 <&pinmux 135 77 6>,
446 <&pinmux 141 67 4>,
447 <&pinmux 145 149 6>,
448 <&pinmux 151 91 4>;
449 };
451 i2c1: i2c@e0000 {
452 compatible = "brcm,iproc-i2c";
453 reg = <0x000e0000 0x100>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 interrupts = <GIC_SPI 178 IRQ_TYPE_NONE>;
457 clock-frequency = <100000>;
458 status = "disabled";
459 };
461 uart0: uart@100000 {
462 device_type = "serial";
463 compatible = "snps,dw-apb-uart";
464 reg = <0x00100000 0x1000>;
465 reg-shift = <2>;
466 clock-frequency = <25000000>;
467 interrupt-parent = <&gic>;
468 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
469 status = "disabled";
470 };
472 uart1: uart@110000 {
473 device_type = "serial";
474 compatible = "snps,dw-apb-uart";
475 reg = <0x00110000 0x1000>;
476 reg-shift = <2>;
477 clock-frequency = <25000000>;
478 interrupt-parent = <&gic>;
479 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
480 status = "disabled";
481 };
483 uart2: uart@120000 {
484 device_type = "serial";
485 compatible = "snps,dw-apb-uart";
486 reg = <0x00120000 0x1000>;
487 reg-shift = <2>;
488 clock-frequency = <25000000>;
489 interrupt-parent = <&gic>;
490 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
491 status = "disabled";
492 };
494 uart3: uart@130000 {
495 device_type = "serial";
496 compatible = "snps,dw-apb-uart";
497 reg = <0x00130000 0x1000>;
498 reg-shift = <2>;
499 clock-frequency = <25000000>;
500 interrupt-parent = <&gic>;
501 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
502 status = "disabled";
503 };
505 ssp0: ssp@180000 {
506 compatible = "arm,pl022", "arm,primecell";
507 reg = <0x00180000 0x1000>;
508 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
510 clock-names = "spiclk", "apb_pclk";
511 num-cs = <1>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 status = "disabled";
515 };
517 ssp1: ssp@190000 {
518 compatible = "arm,pl022", "arm,primecell";
519 reg = <0x00190000 0x1000>;
520 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
522 clock-names = "spiclk", "apb_pclk";
523 num-cs = <1>;
524 #address-cells = <1>;
525 #size-cells = <0>;
526 status = "disabled";
527 };
529 hwrng: hwrng@220000 {
530 compatible = "brcm,iproc-rng200";
531 reg = <0x00220000 0x28>;
532 };
534 dma0: dma@310000 {
535 compatible = "arm,pl330", "arm,primecell";
536 reg = <0x00310000 0x1000>;
537 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
546 #dma-cells = <1>;
547 #dma-channels = <8>;
548 #dma-requests = <32>;
549 clocks = <&hsls_div2_clk>;
550 clock-names = "apb_pclk";
551 iommus = <&smmu 0x6000 0x0000>;
552 };
554 enet: ethernet@340000{
555 compatible = "brcm,amac";
556 reg = <0x00340000 0x1000>;
557 reg-names = "amac_base";
558 dma-coherent;
559 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
560 status= "disabled";
561 };
563 nand: nand@360000 {
564 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
565 reg = <0x00360000 0x600>,
566 <0x0050a408 0x600>,
567 <0x00360f00 0x20>;
568 reg-names = "nand", "iproc-idm", "iproc-ext";
569 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
570 #address-cells = <1>;
571 #size-cells = <0>;
572 brcm,nand-has-wp;
573 status = "disabled";
574 };
576 sdio0: sdhci@3f1000 {
577 compatible = "brcm,sdhci-iproc";
578 reg = <0x003f1000 0x100>;
579 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
580 bus-width = <8>;
581 clocks = <&sdio0_clk>;
582 iommus = <&smmu 0x6002 0x0000>;
583 status = "disabled";
584 };
586 sdio1: sdhci@3f2000 {
587 compatible = "brcm,sdhci-iproc";
588 reg = <0x003f2000 0x100>;
589 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
590 bus-width = <8>;
591 clocks = <&sdio1_clk>;
592 iommus = <&smmu 0x6003 0x0000>;
593 status = "disabled";
594 };
595 };
596 };