| blob | 62f276970174d4db345cd0e3be6a6e05d62e0e22 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos5433 SoC device tree source
4 *
5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 *
7 * Samsung's Exynos5433 SoC device nodes are listed in this file.
8 * Exynos5433 based board files can include this file and provide
9 * values for board specific bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
13 * additional nodes can be added to this file.
14 */
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 / {
20 compatible = "samsung,exynos5433";
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
30 cpu0: cpu@100 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a53", "arm,armv8";
33 enable-method = "psci";
34 reg = <0x100>;
35 clock-frequency = <1300000000>;
36 clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
37 clock-names = "apolloclk";
38 operating-points-v2 = <&cluster_a53_opp_table>;
39 #cooling-cells = <2>;
40 };
42 cpu1: cpu@101 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a53", "arm,armv8";
45 enable-method = "psci";
46 reg = <0x101>;
47 clock-frequency = <1300000000>;
48 operating-points-v2 = <&cluster_a53_opp_table>;
49 #cooling-cells = <2>;
50 };
52 cpu2: cpu@102 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 reg = <0x102>;
57 clock-frequency = <1300000000>;
58 operating-points-v2 = <&cluster_a53_opp_table>;
59 #cooling-cells = <2>;
60 };
62 cpu3: cpu@103 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a53", "arm,armv8";
65 enable-method = "psci";
66 reg = <0x103>;
67 clock-frequency = <1300000000>;
68 operating-points-v2 = <&cluster_a53_opp_table>;
69 #cooling-cells = <2>;
70 };
72 cpu4: cpu@0 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a57", "arm,armv8";
75 enable-method = "psci";
76 reg = <0x0>;
77 clock-frequency = <1900000000>;
78 clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
79 clock-names = "atlasclk";
80 operating-points-v2 = <&cluster_a57_opp_table>;
81 #cooling-cells = <2>;
82 };
84 cpu5: cpu@1 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a57", "arm,armv8";
87 enable-method = "psci";
88 reg = <0x1>;
89 clock-frequency = <1900000000>;
90 operating-points-v2 = <&cluster_a57_opp_table>;
91 #cooling-cells = <2>;
92 };
94 cpu6: cpu@2 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a57", "arm,armv8";
97 enable-method = "psci";
98 reg = <0x2>;
99 clock-frequency = <1900000000>;
100 operating-points-v2 = <&cluster_a57_opp_table>;
101 #cooling-cells = <2>;
102 };
104 cpu7: cpu@3 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a57", "arm,armv8";
107 enable-method = "psci";
108 reg = <0x3>;
109 clock-frequency = <1900000000>;
110 operating-points-v2 = <&cluster_a57_opp_table>;
111 #cooling-cells = <2>;
112 };
113 };
115 cluster_a53_opp_table: opp_table0 {
116 compatible = "operating-points-v2";
117 opp-shared;
119 opp-400000000 {
120 opp-hz = /bits/ 64 <400000000>;
121 opp-microvolt = <900000>;
122 };
123 opp-500000000 {
124 opp-hz = /bits/ 64 <500000000>;
125 opp-microvolt = <925000>;
126 };
127 opp-600000000 {
128 opp-hz = /bits/ 64 <600000000>;
129 opp-microvolt = <950000>;
130 };
131 opp-700000000 {
132 opp-hz = /bits/ 64 <700000000>;
133 opp-microvolt = <975000>;
134 };
135 opp-800000000 {
136 opp-hz = /bits/ 64 <800000000>;
137 opp-microvolt = <1000000>;
138 };
139 opp-900000000 {
140 opp-hz = /bits/ 64 <900000000>;
141 opp-microvolt = <1050000>;
142 };
143 opp-1000000000 {
144 opp-hz = /bits/ 64 <1000000000>;
145 opp-microvolt = <1075000>;
146 };
147 opp-1100000000 {
148 opp-hz = /bits/ 64 <1100000000>;
149 opp-microvolt = <1112500>;
150 };
151 opp-1200000000 {
152 opp-hz = /bits/ 64 <1200000000>;
153 opp-microvolt = <1112500>;
154 };
155 opp-1300000000 {
156 opp-hz = /bits/ 64 <1300000000>;
157 opp-microvolt = <1150000>;
158 };
159 };
161 cluster_a57_opp_table: opp_table1 {
162 compatible = "operating-points-v2";
163 opp-shared;
165 opp-500000000 {
166 opp-hz = /bits/ 64 <500000000>;
167 opp-microvolt = <900000>;
168 };
169 opp-600000000 {
170 opp-hz = /bits/ 64 <600000000>;
171 opp-microvolt = <900000>;
172 };
173 opp-700000000 {
174 opp-hz = /bits/ 64 <700000000>;
175 opp-microvolt = <912500>;
176 };
177 opp-800000000 {
178 opp-hz = /bits/ 64 <800000000>;
179 opp-microvolt = <912500>;
180 };
181 opp-900000000 {
182 opp-hz = /bits/ 64 <900000000>;
183 opp-microvolt = <937500>;
184 };
185 opp-1000000000 {
186 opp-hz = /bits/ 64 <1000000000>;
187 opp-microvolt = <975000>;
188 };
189 opp-1100000000 {
190 opp-hz = /bits/ 64 <1100000000>;
191 opp-microvolt = <1012500>;
192 };
193 opp-1200000000 {
194 opp-hz = /bits/ 64 <1200000000>;
195 opp-microvolt = <1037500>;
196 };
197 opp-1300000000 {
198 opp-hz = /bits/ 64 <1300000000>;
199 opp-microvolt = <1062500>;
200 };
201 opp-1400000000 {
202 opp-hz = /bits/ 64 <1400000000>;
203 opp-microvolt = <1087500>;
204 };
205 opp-1500000000 {
206 opp-hz = /bits/ 64 <1500000000>;
207 opp-microvolt = <1125000>;
208 };
209 opp-1600000000 {
210 opp-hz = /bits/ 64 <1600000000>;
211 opp-microvolt = <1137500>;
212 };
213 opp-1700000000 {
214 opp-hz = /bits/ 64 <1700000000>;
215 opp-microvolt = <1175000>;
216 };
217 opp-1800000000 {
218 opp-hz = /bits/ 64 <1800000000>;
219 opp-microvolt = <1212500>;
220 };
221 opp-1900000000 {
222 opp-hz = /bits/ 64 <1900000000>;
223 opp-microvolt = <1262500>;
224 };
225 };
227 psci {
228 compatible = "arm,psci";
229 method = "smc";
230 cpu_off = <0x84000002>;
231 cpu_on = <0xC4000003>;
232 };
234 reboot: syscon-reboot {
235 compatible = "syscon-reboot";
236 regmap = <&pmu_system_controller>;
237 offset = <0x400>; /* SWRESET */
238 mask = <0x1>;
239 };
241 soc: soc {
242 compatible = "simple-bus";
243 #address-cells = <1>;
244 #size-cells = <1>;
245 ranges = <0x0 0x0 0x0 0x18000000>;
247 arm_a53_pmu {
248 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
249 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
253 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
254 };
256 arm_a57_pmu {
257 compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
258 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
262 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
263 };
265 chipid@10000000 {
266 compatible = "samsung,exynos4210-chipid";
267 reg = <0x10000000 0x100>;
268 };
270 xxti: xxti {
271 compatible = "fixed-clock";
272 clock-output-names = "oscclk";
273 #clock-cells = <0>;
274 };
276 cmu_top: clock-controller@10030000 {
277 compatible = "samsung,exynos5433-cmu-top";
278 reg = <0x10030000 0x1000>;
279 #clock-cells = <1>;
281 clock-names = "oscclk",
282 "sclk_mphy_pll",
283 "sclk_mfc_pll",
284 "sclk_bus_pll";
285 clocks = <&xxti>,
286 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
287 <&cmu_mif CLK_SCLK_MFC_PLL>,
288 <&cmu_mif CLK_SCLK_BUS_PLL>;
289 };
291 cmu_cpif: clock-controller@10fc0000 {
292 compatible = "samsung,exynos5433-cmu-cpif";
293 reg = <0x10fc0000 0x1000>;
294 #clock-cells = <1>;
296 clock-names = "oscclk";
297 clocks = <&xxti>;
298 };
300 cmu_mif: clock-controller@105b0000 {
301 compatible = "samsung,exynos5433-cmu-mif";
302 reg = <0x105b0000 0x2000>;
303 #clock-cells = <1>;
305 clock-names = "oscclk",
306 "sclk_mphy_pll";
307 clocks = <&xxti>,
308 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
309 };
311 cmu_peric: clock-controller@14c80000 {
312 compatible = "samsung,exynos5433-cmu-peric";
313 reg = <0x14c80000 0x1000>;
314 #clock-cells = <1>;
315 };
317 cmu_peris: clock-controller@10040000 {
318 compatible = "samsung,exynos5433-cmu-peris";
319 reg = <0x10040000 0x1000>;
320 #clock-cells = <1>;
321 };
323 cmu_fsys: clock-controller@156e0000 {
324 compatible = "samsung,exynos5433-cmu-fsys";
325 reg = <0x156e0000 0x1000>;
326 #clock-cells = <1>;
328 clock-names = "oscclk",
329 "sclk_ufs_mphy",
330 "aclk_fsys_200",
331 "sclk_pcie_100_fsys",
332 "sclk_ufsunipro_fsys",
333 "sclk_mmc2_fsys",
334 "sclk_mmc1_fsys",
335 "sclk_mmc0_fsys",
336 "sclk_usbhost30_fsys",
337 "sclk_usbdrd30_fsys";
338 clocks = <&xxti>,
339 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
340 <&cmu_top CLK_ACLK_FSYS_200>,
341 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
342 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
343 <&cmu_top CLK_SCLK_MMC2_FSYS>,
344 <&cmu_top CLK_SCLK_MMC1_FSYS>,
345 <&cmu_top CLK_SCLK_MMC0_FSYS>,
346 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
347 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
348 };
350 cmu_g2d: clock-controller@12460000 {
351 compatible = "samsung,exynos5433-cmu-g2d";
352 reg = <0x12460000 0x1000>;
353 #clock-cells = <1>;
355 clock-names = "oscclk",
356 "aclk_g2d_266",
357 "aclk_g2d_400";
358 clocks = <&xxti>,
359 <&cmu_top CLK_ACLK_G2D_266>,
360 <&cmu_top CLK_ACLK_G2D_400>;
361 power-domains = <&pd_g2d>;
362 };
364 cmu_disp: clock-controller@13b90000 {
365 compatible = "samsung,exynos5433-cmu-disp";
366 reg = <0x13b90000 0x1000>;
367 #clock-cells = <1>;
369 clock-names = "oscclk",
370 "sclk_dsim1_disp",
371 "sclk_dsim0_disp",
372 "sclk_dsd_disp",
373 "sclk_decon_tv_eclk_disp",
374 "sclk_decon_vclk_disp",
375 "sclk_decon_eclk_disp",
376 "sclk_decon_tv_vclk_disp",
377 "aclk_disp_333";
378 clocks = <&xxti>,
379 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
380 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
381 <&cmu_mif CLK_SCLK_DSD_DISP>,
382 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
383 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
384 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
385 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
386 <&cmu_mif CLK_ACLK_DISP_333>;
387 power-domains = <&pd_disp>;
388 };
390 cmu_aud: clock-controller@114c0000 {
391 compatible = "samsung,exynos5433-cmu-aud";
392 reg = <0x114c0000 0x1000>;
393 #clock-cells = <1>;
394 clock-names = "oscclk", "fout_aud_pll";
395 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
396 power-domains = <&pd_aud>;
397 };
399 cmu_bus0: clock-controller@13600000 {
400 compatible = "samsung,exynos5433-cmu-bus0";
401 reg = <0x13600000 0x1000>;
402 #clock-cells = <1>;
404 clock-names = "aclk_bus0_400";
405 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
406 };
408 cmu_bus1: clock-controller@14800000 {
409 compatible = "samsung,exynos5433-cmu-bus1";
410 reg = <0x14800000 0x1000>;
411 #clock-cells = <1>;
413 clock-names = "aclk_bus1_400";
414 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
415 };
417 cmu_bus2: clock-controller@13400000 {
418 compatible = "samsung,exynos5433-cmu-bus2";
419 reg = <0x13400000 0x1000>;
420 #clock-cells = <1>;
422 clock-names = "oscclk", "aclk_bus2_400";
423 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
424 };
426 cmu_g3d: clock-controller@14aa0000 {
427 compatible = "samsung,exynos5433-cmu-g3d";
428 reg = <0x14aa0000 0x2000>;
429 #clock-cells = <1>;
431 clock-names = "oscclk", "aclk_g3d_400";
432 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
433 power-domains = <&pd_g3d>;
434 };
436 cmu_gscl: clock-controller@13cf0000 {
437 compatible = "samsung,exynos5433-cmu-gscl";
438 reg = <0x13cf0000 0x1000>;
439 #clock-cells = <1>;
441 clock-names = "oscclk",
442 "aclk_gscl_111",
443 "aclk_gscl_333";
444 clocks = <&xxti>,
445 <&cmu_top CLK_ACLK_GSCL_111>,
446 <&cmu_top CLK_ACLK_GSCL_333>;
447 power-domains = <&pd_gscl>;
448 };
450 cmu_apollo: clock-controller@11900000 {
451 compatible = "samsung,exynos5433-cmu-apollo";
452 reg = <0x11900000 0x2000>;
453 #clock-cells = <1>;
455 clock-names = "oscclk", "sclk_bus_pll_apollo";
456 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
457 };
459 cmu_atlas: clock-controller@11800000 {
460 compatible = "samsung,exynos5433-cmu-atlas";
461 reg = <0x11800000 0x2000>;
462 #clock-cells = <1>;
464 clock-names = "oscclk", "sclk_bus_pll_atlas";
465 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
466 };
468 cmu_mscl: clock-controller@150d0000 {
469 compatible = "samsung,exynos5433-cmu-mscl";
470 reg = <0x150d0000 0x1000>;
471 #clock-cells = <1>;
473 clock-names = "oscclk",
474 "sclk_jpeg_mscl",
475 "aclk_mscl_400";
476 clocks = <&xxti>,
477 <&cmu_top CLK_SCLK_JPEG_MSCL>,
478 <&cmu_top CLK_ACLK_MSCL_400>;
479 power-domains = <&pd_mscl>;
480 };
482 cmu_mfc: clock-controller@15280000 {
483 compatible = "samsung,exynos5433-cmu-mfc";
484 reg = <0x15280000 0x1000>;
485 #clock-cells = <1>;
487 clock-names = "oscclk", "aclk_mfc_400";
488 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
489 power-domains = <&pd_mfc>;
490 };
492 cmu_hevc: clock-controller@14f80000 {
493 compatible = "samsung,exynos5433-cmu-hevc";
494 reg = <0x14f80000 0x1000>;
495 #clock-cells = <1>;
497 clock-names = "oscclk", "aclk_hevc_400";
498 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
499 power-domains = <&pd_hevc>;
500 };
502 cmu_isp: clock-controller@146d0000 {
503 compatible = "samsung,exynos5433-cmu-isp";
504 reg = <0x146d0000 0x1000>;
505 #clock-cells = <1>;
507 clock-names = "oscclk",
508 "aclk_isp_dis_400",
509 "aclk_isp_400";
510 clocks = <&xxti>,
511 <&cmu_top CLK_ACLK_ISP_DIS_400>,
512 <&cmu_top CLK_ACLK_ISP_400>;
513 power-domains = <&pd_isp>;
514 };
516 cmu_cam0: clock-controller@120d0000 {
517 compatible = "samsung,exynos5433-cmu-cam0";
518 reg = <0x120d0000 0x1000>;
519 #clock-cells = <1>;
521 clock-names = "oscclk",
522 "aclk_cam0_333",
523 "aclk_cam0_400",
524 "aclk_cam0_552";
525 clocks = <&xxti>,
526 <&cmu_top CLK_ACLK_CAM0_333>,
527 <&cmu_top CLK_ACLK_CAM0_400>,
528 <&cmu_top CLK_ACLK_CAM0_552>;
529 power-domains = <&pd_cam0>;
530 };
532 cmu_cam1: clock-controller@145d0000 {
533 compatible = "samsung,exynos5433-cmu-cam1";
534 reg = <0x145d0000 0x1000>;
535 #clock-cells = <1>;
537 clock-names = "oscclk",
538 "sclk_isp_uart_cam1",
539 "sclk_isp_spi1_cam1",
540 "sclk_isp_spi0_cam1",
541 "aclk_cam1_333",
542 "aclk_cam1_400",
543 "aclk_cam1_552";
544 clocks = <&xxti>,
545 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
546 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
547 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
548 <&cmu_top CLK_ACLK_CAM1_333>,
549 <&cmu_top CLK_ACLK_CAM1_400>,
550 <&cmu_top CLK_ACLK_CAM1_552>;
551 power-domains = <&pd_cam1>;
552 };
554 pd_gscl: power-domain@105c4000 {
555 compatible = "samsung,exynos5433-pd";
556 reg = <0x105c4000 0x20>;
557 #power-domain-cells = <0>;
558 label = "GSCL";
559 };
561 pd_cam0: power-domain@105c4020 {
562 compatible = "samsung,exynos5433-pd";
563 reg = <0x105c4020 0x20>;
564 #power-domain-cells = <0>;
565 power-domains = <&pd_cam1>;
566 label = "CAM0";
567 };
569 pd_mscl: power-domain@105c4040 {
570 compatible = "samsung,exynos5433-pd";
571 reg = <0x105c4040 0x20>;
572 #power-domain-cells = <0>;
573 label = "MSCL";
574 };
576 pd_g3d: power-domain@105c4060 {
577 compatible = "samsung,exynos5433-pd";
578 reg = <0x105c4060 0x20>;
579 #power-domain-cells = <0>;
580 label = "G3D";
581 };
583 pd_disp: power-domain@105c4080 {
584 compatible = "samsung,exynos5433-pd";
585 reg = <0x105c4080 0x20>;
586 #power-domain-cells = <0>;
587 label = "DISP";
588 };
590 pd_cam1: power-domain@105c40a0 {
591 compatible = "samsung,exynos5433-pd";
592 reg = <0x105c40a0 0x20>;
593 #power-domain-cells = <0>;
594 label = "CAM1";
595 };
597 pd_aud: power-domain@105c40c0 {
598 compatible = "samsung,exynos5433-pd";
599 reg = <0x105c40c0 0x20>;
600 #power-domain-cells = <0>;
601 label = "AUD";
602 };
604 pd_g2d: power-domain@105c4120 {
605 compatible = "samsung,exynos5433-pd";
606 reg = <0x105c4120 0x20>;
607 #power-domain-cells = <0>;
608 label = "G2D";
609 };
611 pd_isp: power-domain@105c4140 {
612 compatible = "samsung,exynos5433-pd";
613 reg = <0x105c4140 0x20>;
614 #power-domain-cells = <0>;
615 power-domains = <&pd_cam0>;
616 label = "ISP";
617 };
619 pd_mfc: power-domain@105c4180 {
620 compatible = "samsung,exynos5433-pd";
621 reg = <0x105c4180 0x20>;
622 #power-domain-cells = <0>;
623 label = "MFC";
624 };
626 pd_hevc: power-domain@105c41c0 {
627 compatible = "samsung,exynos5433-pd";
628 reg = <0x105c41c0 0x20>;
629 #power-domain-cells = <0>;
630 label = "HEVC";
631 };
633 tmu_atlas0: tmu@10060000 {
634 compatible = "samsung,exynos5433-tmu";
635 reg = <0x10060000 0x200>;
636 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
638 <&cmu_peris CLK_SCLK_TMU0>;
639 clock-names = "tmu_apbif", "tmu_sclk";
640 #include "exynos5433-tmu-sensor-conf.dtsi"
641 status = "disabled";
642 };
644 tmu_atlas1: tmu@10068000 {
645 compatible = "samsung,exynos5433-tmu";
646 reg = <0x10068000 0x200>;
647 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
649 <&cmu_peris CLK_SCLK_TMU0>;
650 clock-names = "tmu_apbif", "tmu_sclk";
651 #include "exynos5433-tmu-sensor-conf.dtsi"
652 status = "disabled";
653 };
655 tmu_g3d: tmu@10070000 {
656 compatible = "samsung,exynos5433-tmu";
657 reg = <0x10070000 0x200>;
658 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
660 <&cmu_peris CLK_SCLK_TMU1>;
661 clock-names = "tmu_apbif", "tmu_sclk";
662 #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
663 status = "disabled";
664 };
666 tmu_apollo: tmu@10078000 {
667 compatible = "samsung,exynos5433-tmu";
668 reg = <0x10078000 0x200>;
669 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
671 <&cmu_peris CLK_SCLK_TMU1>;
672 clock-names = "tmu_apbif", "tmu_sclk";
673 #include "exynos5433-tmu-sensor-conf.dtsi"
674 status = "disabled";
675 };
677 tmu_isp: tmu@1007c000 {
678 compatible = "samsung,exynos5433-tmu";
679 reg = <0x1007c000 0x200>;
680 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
682 <&cmu_peris CLK_SCLK_TMU1>;
683 clock-names = "tmu_apbif", "tmu_sclk";
684 #include "exynos5433-tmu-sensor-conf.dtsi"
685 status = "disabled";
686 };
688 mct@101c0000 {
689 compatible = "samsung,exynos4210-mct";
690 reg = <0x101c0000 0x800>;
691 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
704 clock-names = "fin_pll", "mct";
705 };
707 ppmu_d0_cpu: ppmu@10480000 {
708 compatible = "samsung,exynos-ppmu-v2";
709 reg = <0x10480000 0x2000>;
710 status = "disabled";
711 };
713 ppmu_d0_general: ppmu@10490000 {
714 compatible = "samsung,exynos-ppmu-v2";
715 reg = <0x10490000 0x2000>;
716 status = "disabled";
717 };
719 ppmu_d1_cpu: ppmu@104b0000 {
720 compatible = "samsung,exynos-ppmu-v2";
721 reg = <0x104b0000 0x2000>;
722 status = "disabled";
723 };
725 ppmu_d1_general: ppmu@104c0000 {
726 compatible = "samsung,exynos-ppmu-v2";
727 reg = <0x104c0000 0x2000>;
728 status = "disabled";
729 };
731 pinctrl_alive: pinctrl@10580000 {
732 compatible = "samsung,exynos5433-pinctrl";
733 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
735 wakeup-interrupt-controller {
736 compatible = "samsung,exynos7-wakeup-eint";
737 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
738 };
739 };
741 pinctrl_aud: pinctrl@114b0000 {
742 compatible = "samsung,exynos5433-pinctrl";
743 reg = <0x114b0000 0x1000>;
744 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
745 power-domains = <&pd_aud>;
746 };
748 pinctrl_cpif: pinctrl@10fe0000 {
749 compatible = "samsung,exynos5433-pinctrl";
750 reg = <0x10fe0000 0x1000>;
751 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
752 };
754 pinctrl_ese: pinctrl@14ca0000 {
755 compatible = "samsung,exynos5433-pinctrl";
756 reg = <0x14ca0000 0x1000>;
757 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
758 };
760 pinctrl_finger: pinctrl@14cb0000 {
761 compatible = "samsung,exynos5433-pinctrl";
762 reg = <0x14cb0000 0x1000>;
763 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
764 };
766 pinctrl_fsys: pinctrl@15690000 {
767 compatible = "samsung,exynos5433-pinctrl";
768 reg = <0x15690000 0x1000>;
769 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
770 };
772 pinctrl_imem: pinctrl@11090000 {
773 compatible = "samsung,exynos5433-pinctrl";
774 reg = <0x11090000 0x1000>;
775 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
776 };
778 pinctrl_nfc: pinctrl@14cd0000 {
779 compatible = "samsung,exynos5433-pinctrl";
780 reg = <0x14cd0000 0x1000>;
781 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
782 };
784 pinctrl_peric: pinctrl@14cc0000 {
785 compatible = "samsung,exynos5433-pinctrl";
786 reg = <0x14cc0000 0x1100>;
787 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
788 };
790 pinctrl_touch: pinctrl@14ce0000 {
791 compatible = "samsung,exynos5433-pinctrl";
792 reg = <0x14ce0000 0x1100>;
793 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
794 };
796 pmu_system_controller: system-controller@105c0000 {
797 compatible = "samsung,exynos5433-pmu", "syscon";
798 reg = <0x105c0000 0x5008>;
799 #clock-cells = <1>;
800 clock-names = "clkout16";
801 clocks = <&xxti>;
802 };
804 gic: interrupt-controller@11001000 {
805 compatible = "arm,gic-400";
806 #interrupt-cells = <3>;
807 interrupt-controller;
808 reg = <0x11001000 0x1000>,
809 <0x11002000 0x2000>,
810 <0x11004000 0x2000>,
811 <0x11006000 0x2000>;
812 interrupts = <GIC_PPI 9 0xf04>;
813 };
815 mipi_phy: video-phy {
816 compatible = "samsung,exynos5433-mipi-video-phy";
817 #phy-cells = <1>;
818 samsung,pmu-syscon = <&pmu_system_controller>;
819 samsung,cam0-sysreg = <&syscon_cam0>;
820 samsung,cam1-sysreg = <&syscon_cam1>;
821 samsung,disp-sysreg = <&syscon_disp>;
822 };
824 decon: decon@13800000 {
825 compatible = "samsung,exynos5433-decon";
826 reg = <0x13800000 0x2104>;
827 clocks = <&cmu_disp CLK_PCLK_DECON>,
828 <&cmu_disp CLK_ACLK_DECON>,
829 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
830 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
831 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
832 <&cmu_disp CLK_SCLK_DECON_VCLK>,
833 <&cmu_disp CLK_SCLK_DECON_ECLK>;
834 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
835 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
836 "sclk_decon_vclk", "sclk_decon_eclk";
837 power-domains = <&pd_disp>;
838 interrupt-names = "fifo", "vsync", "lcd_sys";
839 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
841 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
842 samsung,disp-sysreg = <&syscon_disp>;
843 status = "disabled";
844 iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
845 iommu-names = "m0", "m1";
847 ports {
848 #address-cells = <1>;
849 #size-cells = <0>;
851 port@0 {
852 reg = <0>;
853 decon_to_mic: endpoint {
854 remote-endpoint =
855 <&mic_to_decon>;
856 };
857 };
858 };
859 };
861 decon_tv: decon@13880000 {
862 compatible = "samsung,exynos5433-decon-tv";
863 reg = <0x13880000 0x20b8>;
864 clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
865 <&cmu_disp CLK_ACLK_DECON_TV>,
866 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
867 <&cmu_disp CLK_ACLK_XIU_TV0X>,
868 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
869 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
870 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
871 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
872 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
873 "sclk_decon_vclk", "sclk_decon_eclk";
874 samsung,disp-sysreg = <&syscon_disp>;
875 power-domains = <&pd_disp>;
876 interrupt-names = "fifo", "vsync", "lcd_sys";
877 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
879 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
880 status = "disabled";
881 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
882 iommu-names = "m0", "m1";
883 };
885 dsi: dsi@13900000 {
886 compatible = "samsung,exynos5433-mipi-dsi";
887 reg = <0x13900000 0xC0>;
888 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
889 phys = <&mipi_phy 1>;
890 phy-names = "dsim";
891 clocks = <&cmu_disp CLK_PCLK_DSIM0>,
892 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
893 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
894 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
895 <&cmu_disp CLK_SCLK_DSIM0>;
896 clock-names = "bus_clk",
897 "phyclk_mipidphy0_bitclkdiv8",
898 "phyclk_mipidphy0_rxclkesc0",
899 "sclk_rgb_vclk_to_dsim0",
900 "sclk_mipi";
901 power-domains = <&pd_disp>;
902 status = "disabled";
903 #address-cells = <1>;
904 #size-cells = <0>;
906 ports {
907 #address-cells = <1>;
908 #size-cells = <0>;
910 port@0 {
911 reg = <0>;
912 dsi_to_mic: endpoint {
913 remote-endpoint = <&mic_to_dsi>;
914 };
915 };
916 };
917 };
919 mic: mic@13930000 {
920 compatible = "samsung,exynos5433-mic";
921 reg = <0x13930000 0x48>;
922 clocks = <&cmu_disp CLK_PCLK_MIC0>,
923 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
924 clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
925 power-domains = <&pd_disp>;
926 samsung,disp-syscon = <&syscon_disp>;
927 status = "disabled";
929 ports {
930 #address-cells = <1>;
931 #size-cells = <0>;
933 port@0 {
934 reg = <0>;
935 mic_to_decon: endpoint {
936 remote-endpoint =
937 <&decon_to_mic>;
938 };
939 };
941 port@1 {
942 reg = <1>;
943 mic_to_dsi: endpoint {
944 remote-endpoint = <&dsi_to_mic>;
945 };
946 };
947 };
948 };
950 hdmi: hdmi@13970000 {
951 compatible = "samsung,exynos5433-hdmi";
952 reg = <0x13970000 0x70000>;
953 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&cmu_disp CLK_PCLK_HDMI>,
955 <&cmu_disp CLK_PCLK_HDMIPHY>,
956 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
957 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
958 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
959 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
960 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
961 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
962 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
963 clock-names = "hdmi_pclk", "hdmi_i_pclk",
964 "i_tmds_clk", "i_pixel_clk",
965 "tmds_clko", "tmds_clko_user",
966 "pixel_clko", "pixel_clko_user",
967 "oscclk", "i_spdif_clk";
968 phy = <&hdmiphy>;
969 ddc = <&hsi2c_11>;
970 samsung,syscon-phandle = <&pmu_system_controller>;
971 samsung,sysreg-phandle = <&syscon_disp>;
972 status = "disabled";
973 };
975 hdmiphy: hdmiphy@13af0000 {
976 reg = <0x13af0000 0x80>;
977 };
979 syscon_disp: syscon@13b80000 {
980 compatible = "syscon";
981 reg = <0x13b80000 0x1010>;
982 };
984 syscon_cam0: syscon@120f0000 {
985 compatible = "syscon";
986 reg = <0x120f0000 0x1020>;
987 };
989 syscon_cam1: syscon@145f0000 {
990 compatible = "syscon";
991 reg = <0x145f0000 0x1038>;
992 };
994 gsc_0: video-scaler@13c00000 {
995 compatible = "samsung,exynos5433-gsc";
996 reg = <0x13c00000 0x1000>;
997 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
998 clock-names = "pclk", "aclk", "aclk_xiu",
999 "aclk_gsclbend";
1000 clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
1001 <&cmu_gscl CLK_ACLK_GSCL0>,
1002 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1003 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1004 iommus = <&sysmmu_gscl0>;
1005 power-domains = <&pd_gscl>;
1006 };
1008 gsc_1: video-scaler@13c10000 {
1009 compatible = "samsung,exynos5433-gsc";
1010 reg = <0x13c10000 0x1000>;
1011 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1012 clock-names = "pclk", "aclk", "aclk_xiu",
1013 "aclk_gsclbend";
1014 clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
1015 <&cmu_gscl CLK_ACLK_GSCL1>,
1016 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1017 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1018 iommus = <&sysmmu_gscl1>;
1019 power-domains = <&pd_gscl>;
1020 };
1022 gsc_2: video-scaler@13c20000 {
1023 compatible = "samsung,exynos5433-gsc";
1024 reg = <0x13c20000 0x1000>;
1025 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1026 clock-names = "pclk", "aclk", "aclk_xiu",
1027 "aclk_gsclbend";
1028 clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
1029 <&cmu_gscl CLK_ACLK_GSCL2>,
1030 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1031 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1032 iommus = <&sysmmu_gscl2>;
1033 power-domains = <&pd_gscl>;
1034 };
1036 jpeg: codec@15020000 {
1037 compatible = "samsung,exynos5433-jpeg";
1038 reg = <0x15020000 0x10000>;
1039 interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
1040 clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1041 clocks = <&cmu_mscl CLK_PCLK_JPEG>,
1042 <&cmu_mscl CLK_ACLK_JPEG>,
1043 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
1044 <&cmu_mscl CLK_SCLK_JPEG>;
1045 iommus = <&sysmmu_jpeg>;
1046 power-domains = <&pd_mscl>;
1047 };
1049 mfc: codec@152e0000 {
1050 compatible = "samsung,exynos5433-mfc";
1051 reg = <0x152E0000 0x10000>;
1052 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1053 clock-names = "pclk", "aclk", "aclk_xiu";
1054 clocks = <&cmu_mfc CLK_PCLK_MFC>,
1055 <&cmu_mfc CLK_ACLK_MFC>,
1056 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
1057 iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
1058 iommu-names = "left", "right";
1059 power-domains = <&pd_mfc>;
1060 };
1062 sysmmu_decon0x: sysmmu@13a00000 {
1063 compatible = "samsung,exynos-sysmmu";
1064 reg = <0x13a00000 0x1000>;
1065 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1066 clock-names = "pclk", "aclk";
1067 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
1068 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
1069 power-domains = <&pd_disp>;
1070 #iommu-cells = <0>;
1071 };
1073 sysmmu_decon1x: sysmmu@13a10000 {
1074 compatible = "samsung,exynos-sysmmu";
1075 reg = <0x13a10000 0x1000>;
1076 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1077 clock-names = "pclk", "aclk";
1078 clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
1079 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
1080 #iommu-cells = <0>;
1081 power-domains = <&pd_disp>;
1082 };
1084 sysmmu_tv0x: sysmmu@13a20000 {
1085 compatible = "samsung,exynos-sysmmu";
1086 reg = <0x13a20000 0x1000>;
1087 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
1088 clock-names = "pclk", "aclk";
1089 clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
1090 <&cmu_disp CLK_ACLK_SMMU_TV0X>;
1091 #iommu-cells = <0>;
1092 power-domains = <&pd_disp>;
1093 };
1095 sysmmu_tv1x: sysmmu@13a30000 {
1096 compatible = "samsung,exynos-sysmmu";
1097 reg = <0x13a30000 0x1000>;
1098 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1099 clock-names = "pclk", "aclk";
1100 clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
1101 <&cmu_disp CLK_ACLK_SMMU_TV1X>;
1102 #iommu-cells = <0>;
1103 power-domains = <&pd_disp>;
1104 };
1106 sysmmu_gscl0: sysmmu@13c80000 {
1107 compatible = "samsung,exynos-sysmmu";
1108 reg = <0x13C80000 0x1000>;
1109 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1110 clock-names = "aclk", "pclk";
1111 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
1112 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
1113 #iommu-cells = <0>;
1114 power-domains = <&pd_gscl>;
1115 };
1117 sysmmu_gscl1: sysmmu@13c90000 {
1118 compatible = "samsung,exynos-sysmmu";
1119 reg = <0x13C90000 0x1000>;
1120 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1121 clock-names = "aclk", "pclk";
1122 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1123 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1124 #iommu-cells = <0>;
1125 power-domains = <&pd_gscl>;
1126 };
1128 sysmmu_gscl2: sysmmu@13ca0000 {
1129 compatible = "samsung,exynos-sysmmu";
1130 reg = <0x13CA0000 0x1000>;
1131 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1132 clock-names = "aclk", "pclk";
1133 clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1134 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1135 #iommu-cells = <0>;
1136 power-domains = <&pd_gscl>;
1137 };
1139 sysmmu_jpeg: sysmmu@15060000 {
1140 compatible = "samsung,exynos-sysmmu";
1141 reg = <0x15060000 0x1000>;
1142 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1143 clock-names = "pclk", "aclk";
1144 clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
1145 <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
1146 #iommu-cells = <0>;
1147 power-domains = <&pd_mscl>;
1148 };
1150 sysmmu_mfc_0: sysmmu@15200000 {
1151 compatible = "samsung,exynos-sysmmu";
1152 reg = <0x15200000 0x1000>;
1153 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1154 clock-names = "pclk", "aclk";
1155 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
1156 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
1157 #iommu-cells = <0>;
1158 power-domains = <&pd_mfc>;
1159 };
1161 sysmmu_mfc_1: sysmmu@15210000 {
1162 compatible = "samsung,exynos-sysmmu";
1163 reg = <0x15210000 0x1000>;
1164 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1165 clock-names = "pclk", "aclk";
1166 clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
1167 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
1168 #iommu-cells = <0>;
1169 power-domains = <&pd_mfc>;
1170 };
1172 serial_0: serial@14c10000 {
1173 compatible = "samsung,exynos5433-uart";
1174 reg = <0x14c10000 0x100>;
1175 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1176 clocks = <&cmu_peric CLK_PCLK_UART0>,
1177 <&cmu_peric CLK_SCLK_UART0>;
1178 clock-names = "uart", "clk_uart_baud0";
1179 pinctrl-names = "default";
1180 pinctrl-0 = <&uart0_bus>;
1181 status = "disabled";
1182 };
1184 serial_1: serial@14c20000 {
1185 compatible = "samsung,exynos5433-uart";
1186 reg = <0x14c20000 0x100>;
1187 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&cmu_peric CLK_PCLK_UART1>,
1189 <&cmu_peric CLK_SCLK_UART1>;
1190 clock-names = "uart", "clk_uart_baud0";
1191 pinctrl-names = "default";
1192 pinctrl-0 = <&uart1_bus>;
1193 status = "disabled";
1194 };
1196 serial_2: serial@14c30000 {
1197 compatible = "samsung,exynos5433-uart";
1198 reg = <0x14c30000 0x100>;
1199 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1200 clocks = <&cmu_peric CLK_PCLK_UART2>,
1201 <&cmu_peric CLK_SCLK_UART2>;
1202 clock-names = "uart", "clk_uart_baud0";
1203 pinctrl-names = "default";
1204 pinctrl-0 = <&uart2_bus>;
1205 status = "disabled";
1206 };
1208 spi_0: spi@14d20000 {
1209 compatible = "samsung,exynos5433-spi";
1210 reg = <0x14d20000 0x100>;
1211 interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1212 dmas = <&pdma0 9>, <&pdma0 8>;
1213 dma-names = "tx", "rx";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1216 clocks = <&cmu_peric CLK_PCLK_SPI0>,
1217 <&cmu_peric CLK_SCLK_SPI0>,
1218 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1219 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1220 samsung,spi-src-clk = <0>;
1221 pinctrl-names = "default";
1222 pinctrl-0 = <&spi0_bus>;
1223 num-cs = <1>;
1224 status = "disabled";
1225 };
1227 spi_1: spi@14d30000 {
1228 compatible = "samsung,exynos5433-spi";
1229 reg = <0x14d30000 0x100>;
1230 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1231 dmas = <&pdma0 11>, <&pdma0 10>;
1232 dma-names = "tx", "rx";
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1235 clocks = <&cmu_peric CLK_PCLK_SPI1>,
1236 <&cmu_peric CLK_SCLK_SPI1>,
1237 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1238 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1239 samsung,spi-src-clk = <0>;
1240 pinctrl-names = "default";
1241 pinctrl-0 = <&spi1_bus>;
1242 num-cs = <1>;
1243 status = "disabled";
1244 };
1246 spi_2: spi@14d40000 {
1247 compatible = "samsung,exynos5433-spi";
1248 reg = <0x14d40000 0x100>;
1249 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1250 dmas = <&pdma0 13>, <&pdma0 12>;
1251 dma-names = "tx", "rx";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 clocks = <&cmu_peric CLK_PCLK_SPI2>,
1255 <&cmu_peric CLK_SCLK_SPI2>,
1256 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1257 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1258 samsung,spi-src-clk = <0>;
1259 pinctrl-names = "default";
1260 pinctrl-0 = <&spi2_bus>;
1261 num-cs = <1>;
1262 status = "disabled";
1263 };
1265 spi_3: spi@14d50000 {
1266 compatible = "samsung,exynos5433-spi";
1267 reg = <0x14d50000 0x100>;
1268 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1269 dmas = <&pdma0 23>, <&pdma0 22>;
1270 dma-names = "tx", "rx";
1271 #address-cells = <1>;
1272 #size-cells = <0>;
1273 clocks = <&cmu_peric CLK_PCLK_SPI3>,
1274 <&cmu_peric CLK_SCLK_SPI3>,
1275 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1276 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1277 samsung,spi-src-clk = <0>;
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&spi3_bus>;
1280 num-cs = <1>;
1281 status = "disabled";
1282 };
1284 spi_4: spi@14d00000 {
1285 compatible = "samsung,exynos5433-spi";
1286 reg = <0x14d00000 0x100>;
1287 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&pdma0 25>, <&pdma0 24>;
1289 dma-names = "tx", "rx";
1290 #address-cells = <1>;
1291 #size-cells = <0>;
1292 clocks = <&cmu_peric CLK_PCLK_SPI4>,
1293 <&cmu_peric CLK_SCLK_SPI4>,
1294 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1295 clock-names = "spi", "spi_busclk0", "spi_ioclk";
1296 samsung,spi-src-clk = <0>;
1297 pinctrl-names = "default";
1298 pinctrl-0 = <&spi4_bus>;
1299 num-cs = <1>;
1300 status = "disabled";
1301 };
1303 adc: adc@14d10000 {
1304 compatible = "samsung,exynos7-adc";
1305 reg = <0x14d10000 0x100>;
1306 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1307 clock-names = "adc";
1308 clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1309 #io-channel-cells = <1>;
1310 io-channel-ranges;
1311 status = "disabled";
1312 };
1314 pwm: pwm@14dd0000 {
1315 compatible = "samsung,exynos4210-pwm";
1316 reg = <0x14dd0000 0x100>;
1317 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1320 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1321 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1322 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1323 clocks = <&cmu_peric CLK_PCLK_PWM>;
1324 clock-names = "timers";
1325 #pwm-cells = <3>;
1326 status = "disabled";
1327 };
1329 hsi2c_0: hsi2c@14e40000 {
1330 compatible = "samsung,exynos7-hsi2c";
1331 reg = <0x14e40000 0x1000>;
1332 interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1335 pinctrl-names = "default";
1336 pinctrl-0 = <&hs_i2c0_bus>;
1337 clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1338 clock-names = "hsi2c";
1339 status = "disabled";
1340 };
1342 hsi2c_1: hsi2c@14e50000 {
1343 compatible = "samsung,exynos7-hsi2c";
1344 reg = <0x14e50000 0x1000>;
1345 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1348 pinctrl-names = "default";
1349 pinctrl-0 = <&hs_i2c1_bus>;
1350 clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1351 clock-names = "hsi2c";
1352 status = "disabled";
1353 };
1355 hsi2c_2: hsi2c@14e60000 {
1356 compatible = "samsung,exynos7-hsi2c";
1357 reg = <0x14e60000 0x1000>;
1358 interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1361 pinctrl-names = "default";
1362 pinctrl-0 = <&hs_i2c2_bus>;
1363 clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1364 clock-names = "hsi2c";
1365 status = "disabled";
1366 };
1368 hsi2c_3: hsi2c@14e70000 {
1369 compatible = "samsung,exynos7-hsi2c";
1370 reg = <0x14e70000 0x1000>;
1371 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1374 pinctrl-names = "default";
1375 pinctrl-0 = <&hs_i2c3_bus>;
1376 clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1377 clock-names = "hsi2c";
1378 status = "disabled";
1379 };
1381 hsi2c_4: hsi2c@14ec0000 {
1382 compatible = "samsung,exynos7-hsi2c";
1383 reg = <0x14ec0000 0x1000>;
1384 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1385 #address-cells = <1>;
1386 #size-cells = <0>;
1387 pinctrl-names = "default";
1388 pinctrl-0 = <&hs_i2c4_bus>;
1389 clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1390 clock-names = "hsi2c";
1391 status = "disabled";
1392 };
1394 hsi2c_5: hsi2c@14ed0000 {
1395 compatible = "samsung,exynos7-hsi2c";
1396 reg = <0x14ed0000 0x1000>;
1397 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1400 pinctrl-names = "default";
1401 pinctrl-0 = <&hs_i2c5_bus>;
1402 clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1403 clock-names = "hsi2c";
1404 status = "disabled";
1405 };
1407 hsi2c_6: hsi2c@14ee0000 {
1408 compatible = "samsung,exynos7-hsi2c";
1409 reg = <0x14ee0000 0x1000>;
1410 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1411 #address-cells = <1>;
1412 #size-cells = <0>;
1413 pinctrl-names = "default";
1414 pinctrl-0 = <&hs_i2c6_bus>;
1415 clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1416 clock-names = "hsi2c";
1417 status = "disabled";
1418 };
1420 hsi2c_7: hsi2c@14ef0000 {
1421 compatible = "samsung,exynos7-hsi2c";
1422 reg = <0x14ef0000 0x1000>;
1423 interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1424 #address-cells = <1>;
1425 #size-cells = <0>;
1426 pinctrl-names = "default";
1427 pinctrl-0 = <&hs_i2c7_bus>;
1428 clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1429 clock-names = "hsi2c";
1430 status = "disabled";
1431 };
1433 hsi2c_8: hsi2c@14d90000 {
1434 compatible = "samsung,exynos7-hsi2c";
1435 reg = <0x14d90000 0x1000>;
1436 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1439 pinctrl-names = "default";
1440 pinctrl-0 = <&hs_i2c8_bus>;
1441 clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1442 clock-names = "hsi2c";
1443 status = "disabled";
1444 };
1446 hsi2c_9: hsi2c@14da0000 {
1447 compatible = "samsung,exynos7-hsi2c";
1448 reg = <0x14da0000 0x1000>;
1449 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1452 pinctrl-names = "default";
1453 pinctrl-0 = <&hs_i2c9_bus>;
1454 clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1455 clock-names = "hsi2c";
1456 status = "disabled";
1457 };
1459 hsi2c_10: hsi2c@14de0000 {
1460 compatible = "samsung,exynos7-hsi2c";
1461 reg = <0x14de0000 0x1000>;
1462 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1463 #address-cells = <1>;
1464 #size-cells = <0>;
1465 pinctrl-names = "default";
1466 pinctrl-0 = <&hs_i2c10_bus>;
1467 clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1468 clock-names = "hsi2c";
1469 status = "disabled";
1470 };
1472 hsi2c_11: hsi2c@14df0000 {
1473 compatible = "samsung,exynos7-hsi2c";
1474 reg = <0x14df0000 0x1000>;
1475 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1478 pinctrl-names = "default";
1479 pinctrl-0 = <&hs_i2c11_bus>;
1480 clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1481 clock-names = "hsi2c";
1482 status = "disabled";
1483 };
1485 usbdrd30: usbdrd {
1486 compatible = "samsung,exynos5250-dwusb3";
1487 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1488 <&cmu_fsys CLK_SCLK_USBDRD30>;
1489 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1490 #address-cells = <1>;
1491 #size-cells = <1>;
1492 ranges;
1493 status = "disabled";
1495 usbdrd_dwc3: dwc3@15400000 {
1496 compatible = "snps,dwc3";
1497 reg = <0x15400000 0x10000>;
1498 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1499 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1500 phy-names = "usb2-phy", "usb3-phy";
1501 };
1502 };
1504 usbdrd30_phy: phy@15500000 {
1505 compatible = "samsung,exynos5433-usbdrd-phy";
1506 reg = <0x15500000 0x100>;
1507 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1508 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1509 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1510 <&cmu_fsys CLK_SCLK_USBDRD30>;
1511 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1512 "itp";
1513 #phy-cells = <1>;
1514 samsung,pmu-syscon = <&pmu_system_controller>;
1515 status = "disabled";
1516 };
1518 usbhost30_phy: phy@15580000 {
1519 compatible = "samsung,exynos5433-usbdrd-phy";
1520 reg = <0x15580000 0x100>;
1521 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1522 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1523 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1524 <&cmu_fsys CLK_SCLK_USBHOST30>;
1525 clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1526 "itp";
1527 #phy-cells = <1>;
1528 samsung,pmu-syscon = <&pmu_system_controller>;
1529 status = "disabled";
1530 };
1532 usbhost30: usbhost {
1533 compatible = "samsung,exynos5250-dwusb3";
1534 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1535 <&cmu_fsys CLK_SCLK_USBHOST30>;
1536 clock-names = "usbdrd30", "usbdrd30_susp_clk";
1537 #address-cells = <1>;
1538 #size-cells = <1>;
1539 ranges;
1540 status = "disabled";
1542 usbhost_dwc3: dwc3@15a00000 {
1543 compatible = "snps,dwc3";
1544 reg = <0x15a00000 0x10000>;
1545 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1546 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1547 phy-names = "usb2-phy", "usb3-phy";
1548 };
1549 };
1551 mshc_0: mshc@15540000 {
1552 compatible = "samsung,exynos7-dw-mshc-smu";
1553 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1556 reg = <0x15540000 0x2000>;
1557 clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1558 <&cmu_fsys CLK_SCLK_MMC0>;
1559 clock-names = "biu", "ciu";
1560 fifo-depth = <0x40>;
1561 status = "disabled";
1562 };
1564 mshc_1: mshc@15550000 {
1565 compatible = "samsung,exynos7-dw-mshc-smu";
1566 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1567 #address-cells = <1>;
1568 #size-cells = <0>;
1569 reg = <0x15550000 0x2000>;
1570 clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1571 <&cmu_fsys CLK_SCLK_MMC1>;
1572 clock-names = "biu", "ciu";
1573 fifo-depth = <0x40>;
1574 status = "disabled";
1575 };
1577 mshc_2: mshc@15560000 {
1578 compatible = "samsung,exynos7-dw-mshc-smu";
1579 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1582 reg = <0x15560000 0x2000>;
1583 clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1584 <&cmu_fsys CLK_SCLK_MMC2>;
1585 clock-names = "biu", "ciu";
1586 fifo-depth = <0x40>;
1587 status = "disabled";
1588 };
1590 amba {
1591 compatible = "simple-bus";
1592 #address-cells = <1>;
1593 #size-cells = <1>;
1594 ranges;
1596 pdma0: pdma@15610000 {
1597 compatible = "arm,pl330", "arm,primecell";
1598 reg = <0x15610000 0x1000>;
1599 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1600 clocks = <&cmu_fsys CLK_PDMA0>;
1601 clock-names = "apb_pclk";
1602 #dma-cells = <1>;
1603 #dma-channels = <8>;
1604 #dma-requests = <32>;
1605 };
1607 pdma1: pdma@15600000 {
1608 compatible = "arm,pl330", "arm,primecell";
1609 reg = <0x15600000 0x1000>;
1610 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1611 clocks = <&cmu_fsys CLK_PDMA1>;
1612 clock-names = "apb_pclk";
1613 #dma-cells = <1>;
1614 #dma-channels = <8>;
1615 #dma-requests = <32>;
1616 };
1617 };
1619 audio-subsystem@11400000 {
1620 compatible = "samsung,exynos5433-lpass";
1621 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1622 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1623 clock-names = "sfr0_ctrl";
1624 samsung,pmu-syscon = <&pmu_system_controller>;
1625 power-domains = <&pd_aud>;
1626 #address-cells = <1>;
1627 #size-cells = <1>;
1628 ranges;
1630 adma: adma@11420000 {
1631 compatible = "arm,pl330", "arm,primecell";
1632 reg = <0x11420000 0x1000>;
1633 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1634 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1635 clock-names = "apb_pclk";
1636 #dma-cells = <1>;
1637 #dma-channels = <8>;
1638 #dma-requests = <32>;
1639 power-domains = <&pd_aud>;
1640 };
1642 i2s0: i2s0@11440000 {
1643 compatible = "samsung,exynos7-i2s";
1644 reg = <0x11440000 0x100>;
1645 dmas = <&adma 0 &adma 2>;
1646 dma-names = "tx", "rx";
1647 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cells = <1>;
1649 #size-cells = <0>;
1650 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1651 <&cmu_aud CLK_SCLK_AUD_I2S>,
1652 <&cmu_aud CLK_SCLK_I2S_BCLK>;
1653 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1654 pinctrl-names = "default";
1655 pinctrl-0 = <&i2s0_bus>;
1656 power-domains = <&pd_aud>;
1657 status = "disabled";
1658 };
1660 serial_3: serial@11460000 {
1661 compatible = "samsung,exynos5433-uart";
1662 reg = <0x11460000 0x100>;
1663 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1664 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1665 <&cmu_aud CLK_SCLK_AUD_UART>;
1666 clock-names = "uart", "clk_uart_baud0";
1667 pinctrl-names = "default";
1668 pinctrl-0 = <&uart_aud_bus>;
1669 power-domains = <&pd_aud>;
1670 status = "disabled";
1671 };
1672 };
1673 };
1675 timer: timer {
1676 compatible = "arm,armv8-timer";
1677 interrupts = <GIC_PPI 13
1678 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1679 <GIC_PPI 14
1680 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1681 <GIC_PPI 11
1682 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1683 <GIC_PPI 10
1684 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1685 };
1686 };
1688 #include "exynos5433-bus.dtsi"
1689 #include "exynos5433-pinctrl.dtsi"
1690 #include "exynos5433-tmu.dtsi"