| blob | 375026867342dd6522167e75f4954a4136c993ec |
1 /*
2 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
3 *
4 * Copyright (C) 2016 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 / {
50 model = "Marvell Armada 37xx SoC";
51 compatible = "marvell,armada3700";
52 interrupt-parent = <&gic>;
53 #address-cells = <2>;
54 #size-cells = <2>;
56 aliases {
57 serial0 = &uart0;
58 serial1 = &uart1;
59 };
61 cpus {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 cpu@0 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a53", "arm,armv8";
67 reg = <0>;
68 clocks = <&nb_periph_clk 16>;
69 enable-method = "psci";
70 };
71 };
73 psci {
74 compatible = "arm,psci-0.2";
75 method = "smc";
76 };
78 timer {
79 compatible = "arm,armv8-timer";
80 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
84 };
86 pmu {
87 compatible = "arm,armv8-pmuv3";
88 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
89 };
91 soc {
92 compatible = "simple-bus";
93 #address-cells = <2>;
94 #size-cells = <2>;
95 ranges;
97 internal-regs@d0000000 {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 compatible = "simple-bus";
101 /* 32M internal register @ 0xd000_0000 */
102 ranges = <0x0 0x0 0xd0000000 0x2000000>;
104 spi0: spi@10600 {
105 compatible = "marvell,armada-3700-spi";
106 #address-cells = <1>;
107 #size-cells = <0>;
108 reg = <0x10600 0xA00>;
109 clocks = <&nb_periph_clk 7>;
110 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
111 num-cs = <4>;
112 status = "disabled";
113 };
115 i2c0: i2c@11000 {
116 compatible = "marvell,armada-3700-i2c";
117 reg = <0x11000 0x24>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 clocks = <&nb_periph_clk 10>;
121 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
122 mrvl,i2c-fast-mode;
123 status = "disabled";
124 };
126 i2c1: i2c@11080 {
127 compatible = "marvell,armada-3700-i2c";
128 reg = <0x11080 0x24>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 clocks = <&nb_periph_clk 9>;
132 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
133 mrvl,i2c-fast-mode;
134 status = "disabled";
135 };
137 uart0: serial@12000 {
138 compatible = "marvell,armada-3700-uart";
139 reg = <0x12000 0x200>;
140 clocks = <&xtalclk>;
141 interrupts =
142 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
145 interrupt-names = "uart-sum", "uart-tx", "uart-rx";
146 status = "disabled";
147 };
149 uart1: serial@12200 {
150 compatible = "marvell,armada-3700-uart-ext";
151 reg = <0x12200 0x30>;
152 clocks = <&xtalclk>;
153 interrupts =
154 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
155 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
156 interrupt-names = "uart-tx", "uart-rx";
157 status = "disabled";
158 };
160 nb_periph_clk: nb-periph-clk@13000 {
161 compatible = "marvell,armada-3700-periph-clock-nb";
162 reg = <0x13000 0x100>;
163 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
164 <&tbg 3>, <&xtalclk>;
165 #clock-cells = <1>;
166 };
168 sb_periph_clk: sb-periph-clk@18000 {
169 compatible = "marvell,armada-3700-periph-clock-sb";
170 reg = <0x18000 0x100>;
171 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
172 <&tbg 3>, <&xtalclk>;
173 #clock-cells = <1>;
174 };
176 tbg: tbg@13200 {
177 compatible = "marvell,armada-3700-tbg-clock";
178 reg = <0x13200 0x100>;
179 clocks = <&xtalclk>;
180 #clock-cells = <1>;
181 };
183 pinctrl_nb: pinctrl@13800 {
184 compatible = "marvell,armada3710-nb-pinctrl",
185 "syscon", "simple-mfd";
186 reg = <0x13800 0x100>, <0x13C00 0x20>;
187 gpionb: gpio {
188 #gpio-cells = <2>;
189 gpio-ranges = <&pinctrl_nb 0 0 36>;
190 gpio-controller;
191 interrupts =
192 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
204 };
206 xtalclk: xtal-clk {
207 compatible = "marvell,armada-3700-xtal-clock";
208 clock-output-names = "xtal";
209 #clock-cells = <0>;
210 };
212 spi_quad_pins: spi-quad-pins {
213 groups = "spi_quad";
214 function = "spi";
215 };
217 i2c1_pins: i2c1-pins {
218 groups = "i2c1";
219 function = "i2c";
220 };
222 i2c2_pins: i2c2-pins {
223 groups = "i2c2";
224 function = "i2c";
225 };
227 uart1_pins: uart1-pins {
228 groups = "uart1";
229 function = "uart";
230 };
232 uart2_pins: uart2-pins {
233 groups = "uart2";
234 function = "uart";
235 };
236 };
238 nb_pm: syscon@14000 {
239 compatible = "marvell,armada-3700-nb-pm",
240 "syscon";
241 reg = <0x14000 0x60>;
242 };
244 pinctrl_sb: pinctrl@18800 {
245 compatible = "marvell,armada3710-sb-pinctrl",
246 "syscon", "simple-mfd";
247 reg = <0x18800 0x100>, <0x18C00 0x20>;
248 gpiosb: gpio {
249 #gpio-cells = <2>;
250 gpio-ranges = <&pinctrl_sb 0 0 30>;
251 gpio-controller;
252 interrupts =
253 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
258 };
260 rgmii_pins: mii-pins {
261 groups = "rgmii";
262 function = "mii";
263 };
265 };
267 eth0: ethernet@30000 {
268 compatible = "marvell,armada-3700-neta";
269 reg = <0x30000 0x4000>;
270 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&sb_periph_clk 8>;
272 status = "disabled";
273 };
275 mdio: mdio@32004 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "marvell,orion-mdio";
279 reg = <0x32004 0x4>;
280 };
282 eth1: ethernet@40000 {
283 compatible = "marvell,armada-3700-neta";
284 reg = <0x40000 0x4000>;
285 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&sb_periph_clk 7>;
287 status = "disabled";
288 };
290 usb3: usb@58000 {
291 compatible = "marvell,armada3700-xhci",
292 "generic-xhci";
293 reg = <0x58000 0x4000>;
294 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&sb_periph_clk 12>;
296 status = "disabled";
297 };
299 usb2: usb@5e000 {
300 compatible = "marvell,armada-3700-ehci";
301 reg = <0x5e000 0x2000>;
302 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
303 status = "disabled";
304 };
306 xor@60900 {
307 compatible = "marvell,armada-3700-xor";
308 reg = <0x60900 0x100>,
309 <0x60b00 0x100>;
311 xor10 {
312 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
313 };
314 xor11 {
315 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
316 };
317 };
319 crypto: crypto@90000 {
320 compatible = "inside-secure,safexcel-eip97";
321 reg = <0x90000 0x20000>;
322 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
328 interrupt-names = "mem", "ring0", "ring1",
329 "ring2", "ring3", "eip";
330 clocks = <&nb_periph_clk 15>;
331 };
333 sdhci1: sdhci@d0000 {
334 compatible = "marvell,armada-3700-sdhci",
335 "marvell,sdhci-xenon";
336 reg = <0xd0000 0x300>,
337 <0x1e808 0x4>;
338 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&nb_periph_clk 0>;
340 clock-names = "core";
341 status = "disabled";
342 };
344 sdhci0: sdhci@d8000 {
345 compatible = "marvell,armada-3700-sdhci",
346 "marvell,sdhci-xenon";
347 reg = <0xd8000 0x300>,
348 <0x17808 0x4>;
349 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&nb_periph_clk 0>;
351 clock-names = "core";
352 status = "disabled";
353 };
355 sata: sata@e0000 {
356 compatible = "marvell,armada-3700-ahci";
357 reg = <0xe0000 0x2000>;
358 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
359 status = "disabled";
360 };
362 gic: interrupt-controller@1d00000 {
363 compatible = "arm,gic-v3";
364 #interrupt-cells = <3>;
365 interrupt-controller;
366 reg = <0x1d00000 0x10000>, /* GICD */
367 <0x1d40000 0x40000>, /* GICR */
368 <0x1d80000 0x2000>, /* GICC */
369 <0x1d90000 0x2000>, /* GICH */
370 <0x1da0000 0x20000>; /* GICV */
371 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
372 };
373 };
375 pcie0: pcie@d0070000 {
376 compatible = "marvell,armada-3700-pcie";
377 device_type = "pci";
378 status = "disabled";
379 reg = <0 0xd0070000 0 0x20000>;
380 #address-cells = <3>;
381 #size-cells = <2>;
382 bus-range = <0x00 0xff>;
383 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
384 #interrupt-cells = <1>;
385 msi-parent = <&pcie0>;
386 msi-controller;
387 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
388 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
389 interrupt-map-mask = <0 0 0 7>;
390 interrupt-map = <0 0 0 1 &pcie_intc 0>,
391 <0 0 0 2 &pcie_intc 1>,
392 <0 0 0 3 &pcie_intc 2>,
393 <0 0 0 4 &pcie_intc 3>;
394 pcie_intc: interrupt-controller {
395 interrupt-controller;
396 #interrupt-cells = <1>;
397 };
398 };
399 };
400 };