2 * Copyright (C) 2015 Marvell Technology Group Ltd.
4 * Author: Jisheng Zhang <jszhang@marvell.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPLv2 or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 compatible = "marvell,berlin4ct", "marvell,berlin";
49 interrupt-parent = <&gic>;
58 compatible = "arm,psci-1.0", "arm,psci-0.2";
67 compatible = "arm,cortex-a53", "arm,armv8";
70 enable-method = "psci";
71 next-level-cache = <&l2>;
72 cpu-idle-states = <&CPU_SLEEP_0>;
76 compatible = "arm,cortex-a53", "arm,armv8";
79 enable-method = "psci";
80 next-level-cache = <&l2>;
81 cpu-idle-states = <&CPU_SLEEP_0>;
85 compatible = "arm,cortex-a53", "arm,armv8";
88 enable-method = "psci";
89 next-level-cache = <&l2>;
90 cpu-idle-states = <&CPU_SLEEP_0>;
94 compatible = "arm,cortex-a53", "arm,armv8";
97 enable-method = "psci";
98 next-level-cache = <&l2>;
99 cpu-idle-states = <&CPU_SLEEP_0>;
103 compatible = "cache";
107 entry-method = "psci";
108 CPU_SLEEP_0: cpu-sleep-0 {
109 compatible = "arm,idle-state";
111 arm,psci-suspend-param = <0x0010000>;
112 entry-latency-us = <75>;
113 exit-latency-us = <155>;
114 min-residency-us = <1000>;
120 compatible = "fixed-clock";
122 clock-frequency = <25000000>;
126 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
127 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-affinity = <&cpu0>,
138 compatible = "arm,armv8-timer";
139 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
140 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
141 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
142 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
146 compatible = "simple-bus";
147 #address-cells = <1>;
149 ranges = <0 0 0xf7000000 0x1000000>;
151 gic: interrupt-controller@901000 {
152 compatible = "arm,gic-400";
153 #interrupt-cells = <3>;
154 interrupt-controller;
155 reg = <0x901000 0x1000>,
159 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
163 compatible = "simple-bus";
164 #address-cells = <1>;
167 ranges = <0 0xe80000 0x10000>;
168 interrupt-parent = <&aic>;
171 compatible = "snps,dw-apb-gpio";
172 reg = <0x0400 0x400>;
173 #address-cells = <1>;
177 compatible = "snps,dw-apb-gpio-port";
180 snps,nr-gpios = <32>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
189 compatible = "snps,dw-apb-gpio";
190 reg = <0x0800 0x400>;
191 #address-cells = <1>;
195 compatible = "snps,dw-apb-gpio-port";
198 snps,nr-gpios = <32>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
207 compatible = "snps,dw-apb-gpio";
208 reg = <0x0c00 0x400>;
209 #address-cells = <1>;
213 compatible = "snps,dw-apb-gpio-port";
216 snps,nr-gpios = <32>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
225 compatible = "snps,dw-apb-gpio";
226 reg = <0x1000 0x400>;
227 #address-cells = <1>;
231 compatible = "snps,dw-apb-gpio-port";
234 snps,nr-gpios = <32>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
242 aic: interrupt-controller@3800 {
243 compatible = "snps,dw-apb-ictl";
245 interrupt-controller;
246 #interrupt-cells = <1>;
247 interrupt-parent = <&gic>;
248 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
252 soc_pinctrl: pin-controller@ea8000 {
253 compatible = "marvell,berlin4ct-soc-pinctrl";
254 reg = <0xea8000 0x14>;
257 avio_pinctrl: pin-controller@ea8400 {
258 compatible = "marvell,berlin4ct-avio-pinctrl";
259 reg = <0xea8400 0x8>;
263 compatible = "simple-bus";
264 #address-cells = <1>;
266 ranges = <0 0xfc0000 0x10000>;
267 interrupt-parent = <&sic>;
269 sic: interrupt-controller@1000 {
270 compatible = "snps,dw-apb-ictl";
272 interrupt-controller;
273 #interrupt-cells = <1>;
274 interrupt-parent = <&gic>;
275 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
278 wdt0: watchdog@3000 {
279 compatible = "snps,dw-wdt";
280 reg = <0x3000 0x100>;
285 wdt1: watchdog@4000 {
286 compatible = "snps,dw-wdt";
287 reg = <0x4000 0x100>;
292 wdt2: watchdog@5000 {
293 compatible = "snps,dw-wdt";
294 reg = <0x5000 0x100>;
299 sm_gpio0: gpio@8000 {
300 compatible = "snps,dw-apb-gpio";
301 reg = <0x8000 0x400>;
302 #address-cells = <1>;
306 compatible = "snps,dw-apb-gpio-port";
309 snps,nr-gpios = <32>;
314 sm_gpio1: gpio@9000 {
315 compatible = "snps,dw-apb-gpio";
316 reg = <0x9000 0x400>;
317 #address-cells = <1>;
321 compatible = "snps,dw-apb-gpio-port";
324 snps,nr-gpios = <32>;
330 compatible = "snps,dw-apb-uart";
331 reg = <0xd000 0x100>;
336 pinctrl-0 = <&uart0_pmux>;
337 pinctrl-names = "default";
341 system_pinctrl: pin-controller@fe2200 {
342 compatible = "marvell,berlin4ct-system-pinctrl";
343 reg = <0xfe2200 0xc>;
345 uart0_pmux: uart0-pmux {
346 groups = "SM_URT0_TXD", "SM_URT0_RXD";