arch/arm64/boot/dts/nvidia/tegra186.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra186-clock.h>
   3 #include <dt-bindings/gpio/tegra186-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/memory/tegra186-mc.h>
   7 #include <dt-bindings/power/tegra186-powergate.h>
   8 #include <dt-bindings/reset/tegra186-reset.h>
   9 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
  10
  11 / {
  12         compatible = "nvidia,tegra186";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         misc@100000 {
  18                 compatible = "nvidia,tegra186-misc";
  19                 reg = <0x0 0x00100000 0x0 0xf000>,
  20                       <0x0 0x0010f000 0x0 0x1000>;
  21         };
  22
  23         gpio: gpio@2200000 {
  24                 compatible = "nvidia,tegra186-gpio";
  25                 reg-names = "security", "gpio";
  26                 reg = <0x0 0x2200000 0x0 0x10000>,
  27                       <0x0 0x2210000 0x0 0x10000>;
  28                 interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
  29                              <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
  30                              <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
  31                              <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
  32                              <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
  33                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  34                 #interrupt-cells = <2>;
  35                 interrupt-controller;
  36                 #gpio-cells = <2>;
  37                 gpio-controller;
  38         };
  39
  40         ethernet@2490000 {
  41                 compatible = "nvidia,tegra186-eqos",
  42                              "snps,dwc-qos-ethernet-4.10";
  43                 reg = <0x0 0x02490000 0x0 0x10000>;
  44                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
  45                              <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
  46                              <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
  47                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
  48                              <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
  49                              <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
  50                              <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
  51                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
  52                              <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
  53                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
  54                 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
  55                          <&bpmp TEGRA186_CLK_EQOS_AXI>,
  56                          <&bpmp TEGRA186_CLK_EQOS_RX>,
  57                          <&bpmp TEGRA186_CLK_EQOS_TX>,
  58                          <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
  59                 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  60                 resets = <&bpmp TEGRA186_RESET_EQOS>;
  61                 reset-names = "eqos";
  62                 status = "disabled";
  63
  64                 snps,write-requests = <1>;
  65                 snps,read-requests = <3>;
  66                 snps,burst-map = <0x7>;
  67                 snps,txpbl = <32>;
  68                 snps,rxpbl = <8>;
  69         };
  70
  71         memory-controller@2c00000 {
  72                 compatible = "nvidia,tegra186-mc";
  73                 reg = <0x0 0x02c00000 0x0 0xb0000>;
  74                 status = "disabled";
  75         };
  76
  77         uarta: serial@3100000 {
  78                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  79                 reg = <0x0 0x03100000 0x0 0x40>;
  80                 reg-shift = <2>;
  81                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  82                 clocks = <&bpmp TEGRA186_CLK_UARTA>;
  83                 clock-names = "serial";
  84                 resets = <&bpmp TEGRA186_RESET_UARTA>;
  85                 reset-names = "serial";
  86                 status = "disabled";
  87         };
  88
  89         uartb: serial@3110000 {
  90                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  91                 reg = <0x0 0x03110000 0x0 0x40>;
  92                 reg-shift = <2>;
  93                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  94                 clocks = <&bpmp TEGRA186_CLK_UARTB>;
  95                 clock-names = "serial";
  96                 resets = <&bpmp TEGRA186_RESET_UARTB>;
  97                 reset-names = "serial";
  98                 status = "disabled";
  99         };
 100
 101         uartd: serial@3130000 {
 102                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 103                 reg = <0x0 0x03130000 0x0 0x40>;
 104                 reg-shift = <2>;
 105                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 106                 clocks = <&bpmp TEGRA186_CLK_UARTD>;
 107                 clock-names = "serial";
 108                 resets = <&bpmp TEGRA186_RESET_UARTD>;
 109                 reset-names = "serial";
 110                 status = "disabled";
 111         };
 112
 113         uarte: serial@3140000 {
 114                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 115                 reg = <0x0 0x03140000 0x0 0x40>;
 116                 reg-shift = <2>;
 117                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 118                 clocks = <&bpmp TEGRA186_CLK_UARTE>;
 119                 clock-names = "serial";
 120                 resets = <&bpmp TEGRA186_RESET_UARTE>;
 121                 reset-names = "serial";
 122                 status = "disabled";
 123         };
 124
 125         uartf: serial@3150000 {
 126                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 127                 reg = <0x0 0x03150000 0x0 0x40>;
 128                 reg-shift = <2>;
 129                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 130                 clocks = <&bpmp TEGRA186_CLK_UARTF>;
 131                 clock-names = "serial";
 132                 resets = <&bpmp TEGRA186_RESET_UARTF>;
 133                 reset-names = "serial";
 134                 status = "disabled";
 135         };
 136
 137         gen1_i2c: i2c@3160000 {
 138                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 139                 reg = <0x0 0x03160000 0x0 0x10000>;
 140                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 141                 #address-cells = <1>;
 142                 #size-cells = <0>;
 143                 clocks = <&bpmp TEGRA186_CLK_I2C1>;
 144                 clock-names = "div-clk";
 145                 resets = <&bpmp TEGRA186_RESET_I2C1>;
 146                 reset-names = "i2c";
 147                 status = "disabled";
 148         };
 149
 150         cam_i2c: i2c@3180000 {
 151                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 152                 reg = <0x0 0x03180000 0x0 0x10000>;
 153                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 154                 #address-cells = <1>;
 155                 #size-cells = <0>;
 156                 clocks = <&bpmp TEGRA186_CLK_I2C3>;
 157                 clock-names = "div-clk";
 158                 resets = <&bpmp TEGRA186_RESET_I2C3>;
 159                 reset-names = "i2c";
 160                 status = "disabled";
 161         };
 162
 163         /* shares pads with dpaux1 */
 164         dp_aux_ch1_i2c: i2c@3190000 {
 165                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 166                 reg = <0x0 0x03190000 0x0 0x10000>;
 167                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170                 clocks = <&bpmp TEGRA186_CLK_I2C4>;
 171                 clock-names = "div-clk";
 172                 resets = <&bpmp TEGRA186_RESET_I2C4>;
 173                 reset-names = "i2c";
 174                 status = "disabled";
 175         };
 176
 177         /* controlled by BPMP, should not be enabled */
 178         pwr_i2c: i2c@31a0000 {
 179                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 180                 reg = <0x0 0x031a0000 0x0 0x10000>;
 181                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 clocks = <&bpmp TEGRA186_CLK_I2C5>;
 185                 clock-names = "div-clk";
 186                 resets = <&bpmp TEGRA186_RESET_I2C5>;
 187                 reset-names = "i2c";
 188                 status = "disabled";
 189         };
 190
 191         /* shares pads with dpaux0 */
 192         dp_aux_ch0_i2c: i2c@31b0000 {
 193                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 194                 reg = <0x0 0x031b0000 0x0 0x10000>;
 195                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 196                 #address-cells = <1>;
 197                 #size-cells = <0>;
 198                 clocks = <&bpmp TEGRA186_CLK_I2C6>;
 199                 clock-names = "div-clk";
 200                 resets = <&bpmp TEGRA186_RESET_I2C6>;
 201                 reset-names = "i2c";
 202                 status = "disabled";
 203         };
 204
 205         gen7_i2c: i2c@31c0000 {
 206                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 207                 reg = <0x0 0x031c0000 0x0 0x10000>;
 208                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 209                 #address-cells = <1>;
 210                 #size-cells = <0>;
 211                 clocks = <&bpmp TEGRA186_CLK_I2C7>;
 212                 clock-names = "div-clk";
 213                 resets = <&bpmp TEGRA186_RESET_I2C7>;
 214                 reset-names = "i2c";
 215                 status = "disabled";
 216         };
 217
 218         gen9_i2c: i2c@31e0000 {
 219                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 220                 reg = <0x0 0x031e0000 0x0 0x10000>;
 221                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 222                 #address-cells = <1>;
 223                 #size-cells = <0>;
 224                 clocks = <&bpmp TEGRA186_CLK_I2C9>;
 225                 clock-names = "div-clk";
 226                 resets = <&bpmp TEGRA186_RESET_I2C9>;
 227                 reset-names = "i2c";
 228                 status = "disabled";
 229         };
 230
 231         sdmmc1: sdhci@3400000 {
 232                 compatible = "nvidia,tegra186-sdhci";
 233                 reg = <0x0 0x03400000 0x0 0x10000>;
 234                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 235                 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
 236                 clock-names = "sdhci";
 237                 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
 238                 reset-names = "sdhci";
 239                 status = "disabled";
 240         };
 241
 242         sdmmc2: sdhci@3420000 {
 243                 compatible = "nvidia,tegra186-sdhci";
 244                 reg = <0x0 0x03420000 0x0 0x10000>;
 245                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
 247                 clock-names = "sdhci";
 248                 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
 249                 reset-names = "sdhci";
 250                 status = "disabled";
 251         };
 252
 253         sdmmc3: sdhci@3440000 {
 254                 compatible = "nvidia,tegra186-sdhci";
 255                 reg = <0x0 0x03440000 0x0 0x10000>;
 256                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 257                 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
 258                 clock-names = "sdhci";
 259                 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
 260                 reset-names = "sdhci";
 261                 status = "disabled";
 262         };
 263
 264         sdmmc4: sdhci@3460000 {
 265                 compatible = "nvidia,tegra186-sdhci";
 266                 reg = <0x0 0x03460000 0x0 0x10000>;
 267                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 268                 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
 269                 clock-names = "sdhci";
 270                 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
 271                 reset-names = "sdhci";
 272                 status = "disabled";
 273         };
 274
 275         fuse@3820000 {
 276                 compatible = "nvidia,tegra186-efuse";
 277                 reg = <0x0 0x03820000 0x0 0x10000>;
 278                 clocks = <&bpmp TEGRA186_CLK_FUSE>;
 279                 clock-names = "fuse";
 280         };
 281
 282         gic: interrupt-controller@3881000 {
 283                 compatible = "arm,gic-400";
 284                 #interrupt-cells = <3>;
 285                 interrupt-controller;
 286                 reg = <0x0 0x03881000 0x0 0x1000>,
 287                       <0x0 0x03882000 0x0 0x2000>;
 288                 interrupts = <GIC_PPI 9
 289                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 290                 interrupt-parent = <&gic>;
 291         };
 292
 293         hsp_top0: hsp@3c00000 {
 294                 compatible = "nvidia,tegra186-hsp";
 295                 reg = <0x0 0x03c00000 0x0 0xa0000>;
 296                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 297                 interrupt-names = "doorbell";
 298                 #mbox-cells = <2>;
 299                 status = "disabled";
 300         };
 301
 302         gen2_i2c: i2c@c240000 {
 303                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 304                 reg = <0x0 0x0c240000 0x0 0x10000>;
 305                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308                 clocks = <&bpmp TEGRA186_CLK_I2C2>;
 309                 clock-names = "div-clk";
 310                 resets = <&bpmp TEGRA186_RESET_I2C2>;
 311                 reset-names = "i2c";
 312                 status = "disabled";
 313         };
 314
 315         gen8_i2c: i2c@c250000 {
 316                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 317                 reg = <0x0 0x0c250000 0x0 0x10000>;
 318                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 319                 #address-cells = <1>;
 320                 #size-cells = <0>;
 321                 clocks = <&bpmp TEGRA186_CLK_I2C8>;
 322                 clock-names = "div-clk";
 323                 resets = <&bpmp TEGRA186_RESET_I2C8>;
 324                 reset-names = "i2c";
 325                 status = "disabled";
 326         };
 327
 328         uartc: serial@c280000 {
 329                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 330                 reg = <0x0 0x0c280000 0x0 0x40>;
 331                 reg-shift = <2>;
 332                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&bpmp TEGRA186_CLK_UARTC>;
 334                 clock-names = "serial";
 335                 resets = <&bpmp TEGRA186_RESET_UARTC>;
 336                 reset-names = "serial";
 337                 status = "disabled";
 338         };
 339
 340         uartg: serial@c290000 {
 341                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 342                 reg = <0x0 0x0c290000 0x0 0x40>;
 343                 reg-shift = <2>;
 344                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 345                 clocks = <&bpmp TEGRA186_CLK_UARTG>;
 346                 clock-names = "serial";
 347                 resets = <&bpmp TEGRA186_RESET_UARTG>;
 348                 reset-names = "serial";
 349                 status = "disabled";
 350         };
 351
 352         gpio_aon: gpio@c2f0000 {
 353                 compatible = "nvidia,tegra186-gpio-aon";
 354                 reg-names = "security", "gpio";
 355                 reg = <0x0 0xc2f0000 0x0 0x1000>,
 356                       <0x0 0xc2f1000 0x0 0x1000>;
 357                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 358                 gpio-controller;
 359                 #gpio-cells = <2>;
 360                 interrupt-controller;
 361                 #interrupt-cells = <2>;
 362         };
 363
 364         pmc@c360000 {
 365                 compatible = "nvidia,tegra186-pmc";
 366                 reg = <0 0x0c360000 0 0x10000>,
 367                       <0 0x0c370000 0 0x10000>,
 368                       <0 0x0c380000 0 0x10000>,
 369                       <0 0x0c390000 0 0x10000>;
 370                 reg-names = "pmc", "wake", "aotag", "scratch";
 371         };
 372
 373         ccplex@e000000 {
 374                 compatible = "nvidia,tegra186-ccplex-cluster";
 375                 reg = <0x0 0x0e000000 0x0 0x3fffff>;
 376
 377                 nvidia,bpmp = <&bpmp>;
 378         };
 379
 380         pcie@10003000 {
 381                 compatible = "nvidia,tegra186-pcie";
 382                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
 383                 device_type = "pci";
 384                 reg = <0x0 0x10003000 0x0 0x00000800   /* PADS registers */
 385                        0x0 0x10003800 0x0 0x00000800   /* AFI registers */
 386                        0x0 0x40000000 0x0 0x10000000>; /* configuration space */
 387                 reg-names = "pads", "afi", "cs";
 388
 389                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 390                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 391                 interrupt-names = "intr", "msi";
 392
 393                 #interrupt-cells = <1>;
 394                 interrupt-map-mask = <0 0 0 0>;
 395                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 396
 397                 bus-range = <0x00 0xff>;
 398                 #address-cells = <3>;
 399                 #size-cells = <2>;
 400
 401                 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000   /* port 0 configuration space */
 402                           0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */
 403                           0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */
 404                           0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */
 405                           0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
 406                           0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
 407
 408                 clocks = <&bpmp TEGRA186_CLK_AFI>,
 409                          <&bpmp TEGRA186_CLK_PCIE>,
 410                          <&bpmp TEGRA186_CLK_PLLE>;
 411                 clock-names = "afi", "pex", "pll_e";
 412
 413                 resets = <&bpmp TEGRA186_RESET_AFI>,
 414                          <&bpmp TEGRA186_RESET_PCIE>,
 415                          <&bpmp TEGRA186_RESET_PCIEXCLK>;
 416                 reset-names = "afi", "pex", "pcie_x";
 417
 418                 status = "disabled";
 419
 420                 pci@1,0 {
 421                         device_type = "pci";
 422                         assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
 423                         reg = <0x000800 0 0 0 0>;
 424                         status = "disabled";
 425
 426                         #address-cells = <3>;
 427                         #size-cells = <2>;
 428                         ranges;
 429
 430                         nvidia,num-lanes = <2>;
 431                 };
 432
 433                 pci@2,0 {
 434                         device_type = "pci";
 435                         assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
 436                         reg = <0x001000 0 0 0 0>;
 437                         status = "disabled";
 438
 439                         #address-cells = <3>;
 440                         #size-cells = <2>;
 441                         ranges;
 442
 443                         nvidia,num-lanes = <1>;
 444                 };
 445
 446                 pci@3,0 {
 447                         device_type = "pci";
 448                         assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
 449                         reg = <0x001800 0 0 0 0>;
 450                         status = "disabled";
 451
 452                         #address-cells = <3>;
 453                         #size-cells = <2>;
 454                         ranges;
 455
 456                         nvidia,num-lanes = <1>;
 457                 };
 458         };
 459
 460         smmu: iommu@12000000 {
 461                 compatible = "arm,mmu-500";
 462                 reg = <0 0x12000000 0 0x800000>;
 463                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 464                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 465                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 466                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 467                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 468                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 469                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 470                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 471                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 472                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 473                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 474                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 475                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 476                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 477                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 478                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 479                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 480                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 481                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 482                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 483                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 484                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 485                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 486                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 487                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 488                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 489                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 490                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 491                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 492                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 493                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 494                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 495                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 496                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 497                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 498                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 499                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 500                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 501                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 502                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 503                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 504                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 505                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 506                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 507                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 508                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 509                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 510                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 511                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 512                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 513                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 514                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 515                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 516                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 517                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 518                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 519                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 520                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 521                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 522                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 523                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 524                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 525                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 526                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 527                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 528                 stream-match-mask = <0x7f80>;
 529                 #global-interrupts = <1>;
 530                 #iommu-cells = <1>;
 531         };
 532
 533         host1x@13e00000 {
 534                 compatible = "nvidia,tegra186-host1x", "simple-bus";
 535                 reg = <0x0 0x13e00000 0x0 0x10000>,
 536                       <0x0 0x13e10000 0x0 0x10000>;
 537                 reg-names = "hypervisor", "vm";
 538                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 539                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 540                 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
 541                 clock-names = "host1x";
 542                 resets = <&bpmp TEGRA186_RESET_HOST1X>;
 543                 reset-names = "host1x";
 544
 545                 #address-cells = <1>;
 546                 #size-cells = <1>;
 547
 548                 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
 549                 iommus = <&smmu TEGRA186_SID_HOST1X>;
 550
 551                 dpaux1: dpaux@15040000 {
 552                         compatible = "nvidia,tegra186-dpaux";
 553                         reg = <0x15040000 0x10000>;
 554                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
 555                         clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
 556                                  <&bpmp TEGRA186_CLK_PLLDP>;
 557                         clock-names = "dpaux", "parent";
 558                         resets = <&bpmp TEGRA186_RESET_DPAUX1>;
 559                         reset-names = "dpaux";
 560                         status = "disabled";
 561
 562                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 563
 564                         state_dpaux1_aux: pinmux-aux {
 565                                 groups = "dpaux-io";
 566                                 function = "aux";
 567                         };
 568
 569                         state_dpaux1_i2c: pinmux-i2c {
 570                                 groups = "dpaux-io";
 571                                 function = "i2c";
 572                         };
 573
 574                         state_dpaux1_off: pinmux-off {
 575                                 groups = "dpaux-io";
 576                                 function = "off";
 577                         };
 578
 579                         i2c-bus {
 580                                 #address-cells = <1>;
 581                                 #size-cells = <0>;
 582                         };
 583                 };
 584
 585                 display-hub@15200000 {
 586                         compatible = "nvidia,tegra186-display", "simple-bus";
 587                         resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
 588                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
 589                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
 590                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
 591                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
 592                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
 593                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
 594                         reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
 595                                       "wgrp3", "wgrp4", "wgrp5";
 596                         clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
 597                                  <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
 598                                  <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
 599                         clock-names = "disp", "dsc", "hub";
 600                         status = "disabled";
 601
 602                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 603
 604                         #address-cells = <1>;
 605                         #size-cells = <1>;
 606
 607                         ranges = <0x15200000 0x15200000 0x40000>;
 608
 609                         display@15200000 {
 610                                 compatible = "nvidia,tegra186-dc";
 611                                 reg = <0x15200000 0x10000>;
 612                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 613                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
 614                                 clock-names = "dc";
 615                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
 616                                 reset-names = "dc";
 617
 618                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 619                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 620
 621                                 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 622                                 nvidia,head = <0>;
 623                         };
 624
 625                         display@15210000 {
 626                                 compatible = "nvidia,tegra186-dc";
 627                                 reg = <0x15210000 0x10000>;
 628                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 629                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
 630                                 clock-names = "dc";
 631                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
 632                                 reset-names = "dc";
 633
 634                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
 635                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 636
 637                                 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 638                                 nvidia,head = <1>;
 639                         };
 640
 641                         display@15220000 {
 642                                 compatible = "nvidia,tegra186-dc";
 643                                 reg = <0x15220000 0x10000>;
 644                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 645                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
 646                                 clock-names = "dc";
 647                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
 648                                 reset-names = "dc";
 649
 650                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
 651                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 652
 653                                 nvidia,outputs = <&sor0 &sor1>;
 654                                 nvidia,head = <2>;
 655                         };
 656                 };
 657
 658                 dsia: dsi@15300000 {
 659                         compatible = "nvidia,tegra186-dsi";
 660                         reg = <0x15300000 0x10000>;
 661                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 662                         clocks = <&bpmp TEGRA186_CLK_DSI>,
 663                                  <&bpmp TEGRA186_CLK_DSIA_LP>,
 664                                  <&bpmp TEGRA186_CLK_PLLD>;
 665                         clock-names = "dsi", "lp", "parent";
 666                         resets = <&bpmp TEGRA186_RESET_DSI>;
 667                         reset-names = "dsi";
 668                         status = "disabled";
 669
 670                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 671                 };
 672
 673                 vic@15340000 {
 674                         compatible = "nvidia,tegra186-vic";
 675                         reg = <0x15340000 0x40000>;
 676                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 677                         clocks = <&bpmp TEGRA186_CLK_VIC>;
 678                         clock-names = "vic";
 679                         resets = <&bpmp TEGRA186_RESET_VIC>;
 680                         reset-names = "vic";
 681
 682                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
 683                 };
 684
 685                 dsib: dsi@15400000 {
 686                         compatible = "nvidia,tegra186-dsi";
 687                         reg = <0x15400000 0x10000>;
 688                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 689                         clocks = <&bpmp TEGRA186_CLK_DSIB>,
 690                                  <&bpmp TEGRA186_CLK_DSIB_LP>,
 691                                  <&bpmp TEGRA186_CLK_PLLD>;
 692                         clock-names = "dsi", "lp", "parent";
 693                         resets = <&bpmp TEGRA186_RESET_DSIB>;
 694                         reset-names = "dsi";
 695                         status = "disabled";
 696
 697                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 698                 };
 699
 700                 sor0: sor@15540000 {
 701                         compatible = "nvidia,tegra186-sor";
 702                         reg = <0x15540000 0x10000>;
 703                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 704                         clocks = <&bpmp TEGRA186_CLK_SOR0>,
 705                                  <&bpmp TEGRA186_CLK_SOR0_OUT>,
 706                                  <&bpmp TEGRA186_CLK_PLLD2>,
 707                                  <&bpmp TEGRA186_CLK_PLLDP>,
 708                                  <&bpmp TEGRA186_CLK_SOR_SAFE>,
 709                                  <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
 710                         clock-names = "sor", "out", "parent", "dp", "safe",
 711                                       "pad";
 712                         resets = <&bpmp TEGRA186_RESET_SOR0>;
 713                         reset-names = "sor";
 714                         pinctrl-0 = <&state_dpaux_aux>;
 715                         pinctrl-1 = <&state_dpaux_i2c>;
 716                         pinctrl-2 = <&state_dpaux_off>;
 717                         pinctrl-names = "aux", "i2c", "off";
 718                         status = "disabled";
 719
 720                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 721                         nvidia,interface = <0>;
 722                 };
 723
 724                 sor1: sor@15580000 {
 725                         compatible = "nvidia,tegra186-sor1";
 726                         reg = <0x15580000 0x10000>;
 727                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 728                         clocks = <&bpmp TEGRA186_CLK_SOR1>,
 729                                  <&bpmp TEGRA186_CLK_SOR1_OUT>,
 730                                  <&bpmp TEGRA186_CLK_PLLD3>,
 731                                  <&bpmp TEGRA186_CLK_PLLDP>,
 732                                  <&bpmp TEGRA186_CLK_SOR_SAFE>,
 733                                  <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
 734                         clock-names = "sor", "out", "parent", "dp", "safe",
 735                                       "pad";
 736                         resets = <&bpmp TEGRA186_RESET_SOR1>;
 737                         reset-names = "sor";
 738                         pinctrl-0 = <&state_dpaux1_aux>;
 739                         pinctrl-1 = <&state_dpaux1_i2c>;
 740                         pinctrl-2 = <&state_dpaux1_off>;
 741                         pinctrl-names = "aux", "i2c", "off";
 742                         status = "disabled";
 743
 744                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 745                         nvidia,interface = <1>;
 746                 };
 747
 748                 dpaux: dpaux@155c0000 {
 749                         compatible = "nvidia,tegra186-dpaux";
 750                         reg = <0x155c0000 0x10000>;
 751                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 752                         clocks = <&bpmp TEGRA186_CLK_DPAUX>,
 753                                  <&bpmp TEGRA186_CLK_PLLDP>;
 754                         clock-names = "dpaux", "parent";
 755                         resets = <&bpmp TEGRA186_RESET_DPAUX>;
 756                         reset-names = "dpaux";
 757                         status = "disabled";
 758
 759                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 760
 761                         state_dpaux_aux: pinmux-aux {
 762                                 groups = "dpaux-io";
 763                                 function = "aux";
 764                         };
 765
 766                         state_dpaux_i2c: pinmux-i2c {
 767                                 groups = "dpaux-io";
 768                                 function = "i2c";
 769                         };
 770
 771                         state_dpaux_off: pinmux-off {
 772                                 groups = "dpaux-io";
 773                                 function = "off";
 774                         };
 775
 776                         i2c-bus {
 777                                 #address-cells = <1>;
 778                                 #size-cells = <0>;
 779                         };
 780                 };
 781
 782                 padctl@15880000 {
 783                         compatible = "nvidia,tegra186-dsi-padctl";
 784                         reg = <0x15880000 0x10000>;
 785                         resets = <&bpmp TEGRA186_RESET_DSI>;
 786                         reset-names = "dsi";
 787                         status = "disabled";
 788                 };
 789
 790                 dsic: dsi@15900000 {
 791                         compatible = "nvidia,tegra186-dsi";
 792                         reg = <0x15900000 0x10000>;
 793                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 794                         clocks = <&bpmp TEGRA186_CLK_DSIC>,
 795                                  <&bpmp TEGRA186_CLK_DSIC_LP>,
 796                                  <&bpmp TEGRA186_CLK_PLLD>;
 797                         clock-names = "dsi", "lp", "parent";
 798                         resets = <&bpmp TEGRA186_RESET_DSIC>;
 799                         reset-names = "dsi";
 800                         status = "disabled";
 801
 802                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 803                 };
 804
 805                 dsid: dsi@15940000 {
 806                         compatible = "nvidia,tegra186-dsi";
 807                         reg = <0x15940000 0x10000>;
 808                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 809                         clocks = <&bpmp TEGRA186_CLK_DSID>,
 810                                  <&bpmp TEGRA186_CLK_DSID_LP>,
 811                                  <&bpmp TEGRA186_CLK_PLLD>;
 812                         clock-names = "dsi", "lp", "parent";
 813                         resets = <&bpmp TEGRA186_RESET_DSID>;
 814                         reset-names = "dsi";
 815                         status = "disabled";
 816
 817                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 818                 };
 819         };
 820
 821         gpu@17000000 {
 822                 compatible = "nvidia,gp10b";
 823                 reg = <0x0 0x17000000 0x0 0x1000000>,
 824                       <0x0 0x18000000 0x0 0x1000000>;
 825                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
 826                               GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 827                 interrupt-names = "stall", "nonstall";
 828
 829                 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
 830                          <&bpmp TEGRA186_CLK_GPU>;
 831                 clock-names = "gpu", "pwr";
 832                 resets = <&bpmp TEGRA186_RESET_GPU>;
 833                 reset-names = "gpu";
 834                 status = "disabled";
 835
 836                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
 837         };
 838
 839         sysram@30000000 {
 840                 compatible = "nvidia,tegra186-sysram", "mmio-sram";
 841                 reg = <0x0 0x30000000 0x0 0x50000>;
 842                 #address-cells = <2>;
 843                 #size-cells = <2>;
 844                 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
 845
 846                 cpu_bpmp_tx: shmem@4e000 {
 847                         compatible = "nvidia,tegra186-bpmp-shmem";
 848                         reg = <0x0 0x4e000 0x0 0x1000>;
 849                         label = "cpu-bpmp-tx";
 850                         pool;
 851                 };
 852
 853                 cpu_bpmp_rx: shmem@4f000 {
 854                         compatible = "nvidia,tegra186-bpmp-shmem";
 855                         reg = <0x0 0x4f000 0x0 0x1000>;
 856                         label = "cpu-bpmp-rx";
 857                         pool;
 858                 };
 859         };
 860
 861         cpus {
 862                 #address-cells = <1>;
 863                 #size-cells = <0>;
 864
 865                 cpu@0 {
 866                         compatible = "nvidia,tegra186-denver", "arm,armv8";
 867                         device_type = "cpu";
 868                         reg = <0x000>;
 869                 };
 870
 871                 cpu@1 {
 872                         compatible = "nvidia,tegra186-denver", "arm,armv8";
 873                         device_type = "cpu";
 874                         reg = <0x001>;
 875                 };
 876
 877                 cpu@2 {
 878                         compatible = "arm,cortex-a57", "arm,armv8";
 879                         device_type = "cpu";
 880                         reg = <0x100>;
 881                 };
 882
 883                 cpu@3 {
 884                         compatible = "arm,cortex-a57", "arm,armv8";
 885                         device_type = "cpu";
 886                         reg = <0x101>;
 887                 };
 888
 889                 cpu@4 {
 890                         compatible = "arm,cortex-a57", "arm,armv8";
 891                         device_type = "cpu";
 892                         reg = <0x102>;
 893                 };
 894
 895                 cpu@5 {
 896                         compatible = "arm,cortex-a57", "arm,armv8";
 897                         device_type = "cpu";
 898                         reg = <0x103>;
 899                 };
 900         };
 901
 902         bpmp: bpmp {
 903                 compatible = "nvidia,tegra186-bpmp";
 904                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
 905                                     TEGRA_HSP_DB_MASTER_BPMP>;
 906                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
 907                 #clock-cells = <1>;
 908                 #reset-cells = <1>;
 909                 #power-domain-cells = <1>;
 910
 911                 bpmp_i2c: i2c {
 912                         compatible = "nvidia,tegra186-bpmp-i2c";
 913                         nvidia,bpmp-bus-id = <5>;
 914                         #address-cells = <1>;
 915                         #size-cells = <0>;
 916                         status = "disabled";
 917                 };
 918
 919                 bpmp_thermal: thermal {
 920                         compatible = "nvidia,tegra186-bpmp-thermal";
 921                         #thermal-sensor-cells = <1>;
 922                 };
 923         };
 924
 925         thermal-zones {
 926                 a57 {
 927                         polling-delay = <0>;
 928                         polling-delay-passive = <1000>;
 929
 930                         thermal-sensors =
 931                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
 932
 933                         trips {
 934                                 critical {
 935                                         temperature = <101000>;
 936                                         hysteresis = <0>;
 937                                         type = "critical";
 938                                 };
 939                         };
 940
 941                         cooling-maps {
 942                         };
 943                 };
 944
 945                 denver {
 946                         polling-delay = <0>;
 947                         polling-delay-passive = <1000>;
 948
 949                         thermal-sensors =
 950                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
 951
 952                         trips {
 953                                 critical {
 954                                         temperature = <101000>;
 955                                         hysteresis = <0>;
 956                                         type = "critical";
 957                                 };
 958                         };
 959
 960                         cooling-maps {
 961                         };
 962                 };
 963
 964                 gpu {
 965                         polling-delay = <0>;
 966                         polling-delay-passive = <1000>;
 967
 968                         thermal-sensors =
 969                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
 970
 971                         trips {
 972                                 critical {
 973                                         temperature = <101000>;
 974                                         hysteresis = <0>;
 975                                         type = "critical";
 976                                 };
 977                         };
 978
 979                         cooling-maps {
 980                         };
 981                 };
 982
 983                 pll {
 984                         polling-delay = <0>;
 985                         polling-delay-passive = <1000>;
 986
 987                         thermal-sensors =
 988                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
 989
 990                         trips {
 991                                 critical {
 992                                         temperature = <101000>;
 993                                         hysteresis = <0>;
 994                                         type = "critical";
 995                                 };
 996                         };
 997
 998                         cooling-maps {
 999                         };
1000                 };
1001
1002                 always_on {
1003                         polling-delay = <0>;
1004                         polling-delay-passive = <1000>;
1005
1006                         thermal-sensors =
1007                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1008
1009                         trips {
1010                                 critical {
1011                                         temperature = <101000>;
1012                                         hysteresis = <0>;
1013                                         type = "critical";
1014                                 };
1015                         };
1016
1017                         cooling-maps {
1018                         };
1019                 };
1020         };
1021
1022         timer {
1023                 compatible = "arm,armv8-timer";
1024                 interrupts = <GIC_PPI 13
1025                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1026                              <GIC_PPI 14
1027                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1028                              <GIC_PPI 11
1029                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1030                              <GIC_PPI 10
1031                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1032                 interrupt-parent = <&gic>;
1033         };
1034 };